CN102412293B - 5V PMOS (P-channel Metal Oxide Semiconductor) device in SONOS (Silicon Oxide Nitride Oxide Semiconductor) technique and fabrication method thereof - Google Patents
5V PMOS (P-channel Metal Oxide Semiconductor) device in SONOS (Silicon Oxide Nitride Oxide Semiconductor) technique and fabrication method thereof Download PDFInfo
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- CN102412293B CN102412293B CN 201010290313 CN201010290313A CN102412293B CN 102412293 B CN102412293 B CN 102412293B CN 201010290313 CN201010290313 CN 201010290313 CN 201010290313 A CN201010290313 A CN 201010290313A CN 102412293 B CN102412293 B CN 102412293B
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Abstract
The invention discloses a 5V PMOS (P-channel Metal Oxide Semiconductor) device in the SONOS (Silicon Oxide Nitride Oxide Semiconductor) technique, and the junction depth of the side of a P-type source-drain region of the PMOS device close to a shallow trench field oxide is greater than the junction depth of the side of the P-type source-drain region close to an N-type trench region. The inventionalso discloses a fabrication method for the 5V PMOS device in the SONOS technique. The invention can improve the topography of the source/drain PN junction of the PMOS device, thus increasing the breakdown voltage of the 5V PMOS device, and moreover, the invention can further increase the information-erasing and information-writing operation voltages of an SONOS flash memory, increase the operation speed, improve the performance of the SONOS flash memory, shorten the test time of the SONOS flash memory and save the test cost.
Description
Technical field
The present invention relates to semiconductor integrated circuit and make the field, particularly relate to 5 volts of PMOS devices in a kind of SONOS technology; The invention still further relates to the manufacture method of 5 volts of PMOS devices in a kind of SONOS technology.
Background technology
At present, existing SONOS flash memory becomes one of main flow of existing flash type because possessing advantage such as high density, big capacity, and is widely used in digital camera, in the electronic products such as smart mobile phone.Existing SONOS flash memory is to need not to provide high tension apparatus in one of circuit and technologic advantage, namely the general voltage that is used for information erasing and writes can be in 12 volts for maximum operating voltage, and the maximum operating voltage of the FLASH flash memory of the floating grid of comparing will hang down much.So one of shortcoming of existing SONOS technology is exactly that service speed is slower, the time erasable by FN tunnelling mechanism generally arrives the hundreds of millisecond at several milliseconds.Further improve existing SONOS flash memory wiping/writing speed, one of approach is the bottom oxide layer of attenuate ONO film, and its risk is that data holding ability reduces.
Another method that improves existing SONOS flash disk operation speed is the erasable voltage of increase information.But in the existing SONOS technology, this operating voltage be the raising of the erasable voltage of described information be subjected to the source/leakage PN junction of 5 volts of PMOS devices the highest withstand voltage be the restriction of puncture voltage, the highest safety operation voltage that has adopted can't further improve.If operating voltage exceeds area of safety operaton, leakage current can be well beyond circuit specification, and leakage current has also limited charge pump (Charge Pump) circuit simultaneously more high-tension ability is provided.As shown in Figure 1, structural representation for 5 volts of PMOS devices in the existing SONOS technology, existing PMOS device is formed on the silicon substrate, described silicon substrate is the N-type silicon substrate or is formed with the N trap at silicon substrate, active area is that STI shown in Fig. 1 isolates by shallow slot field oxygen, existing PMOS device comprises: be formed at the grid structure on the described active area, described grid structure is made up of gate oxide and polysilicon gate, and also being formed with side wall at the sidewall of described grid structure is the grid sidewalls.The P type source-drain area that is formed in described grid structure both sides, the described active area is source/leakage shown in Fig. 1.And be formed at N-type channel region (not indicating among Fig. 1) in the described active area in the middle of described grid structure bottom, the described P type source-drain area.Described P type source-drain area and its N-type substrate or the N trap of active area on every side can form source/leakage PN junction, the shallow slot field oxygen that can extend out from the silicon of active area by entering owing to the boron that injects in source-drain area in the existing PMOS device is that shallow trench isolation is from (STI), can cause the perk on the close side direction of STI of source/leakage PN junction, at the more shallow knot of side formation of described STI.The perk structure of described source/leakage PN junction is the weakness of the source/drain terminal PN junction of existing 5 volts of PMOS devices, has limited the raising of the puncture voltage of existing 5 volts of PMOS devices.
So the key that will improve the service speed of existing SONOS flash memory is the high-voltage safety working region of improving circuit, thereby the space is provided for the erasable operating voltage of raising information.If but by introducing the method for high-pressure process or introducing high tension apparatus, process complexity and technology cost will increase much, properties of product are improved the competitiveness of bringing and also can be weakened.Therefore the method more attractive of the puncture voltage of the source/leakage PN junction by improving 5 volts of PMOS devices.
Summary of the invention
Technical problem to be solved by this invention provides 5 volts of PMOS devices in a kind of SONOS technology, can improve the puncture voltage of 5 volts of PMOS devices, thus can improve operating voltage that the SONOS information of flash memory wipes and write, improve service speed, improve the SONOS flash memory performance, reduce the SONOS flash memory testing time, save testing cost.
For solving the problems of the technologies described above, 5 volts of PMOS devices are formed on the silicon substrate in the SONOS technology provided by the invention, and active area is isolated by shallow slot field oxygen.Described PMOS device comprises: be formed at the grid structure on the described active area, be formed at the P type source-drain area in described grid structure both sides, the described active area and be formed at N-type channel region in the described active area in the middle of described grid structure bottom, the described P type source-drain area; Wherein, the junction depth near described shallow slot field oxygen one side of described P type source-drain area is darker than the junction depth near described N-type channel region one side.
More preferably be selected as, described P type source-drain area is made up of autoregistration source-drain area and non-autoregistration source-drain area.Described autoregistration source-drain area is formed at described N-type channel region edge between oxygen edge, described shallow slot field by self-registered technology.The formation zone of described non-autoregistration source-drain area defines by photoetching process, the opposite side of adjacent, the described non-autoregistration source-drain area of a side of described non-autoregistration source-drain area and oxygen edge, described shallow slot field and the described channel region edge lateral separation of being separated by; The junction depth of described non-autoregistration source-drain area is greater than the junction depth of described autoregistration source-drain area.Described non-autoregistration source-drain area inject to form by P type ion, and the process conditions that the P type ion of described non-autoregistration source-drain area injects are: implanted dopant is that boron or boron difluoride, implantation dosage are 1e13cm
-2～5e14cm
-2, the injection energy is 20KeV～100KeV.
More preferably be selected as, the junction depth of close described shallow slot field oxygen one side of described P type source-drain area is 1.1 times～2 times near the junction depth of described N-type channel region one side.
For solving the problems of the technologies described above, the manufacture method of 5 volts of PMOS devices in the SONOS technology provided by the invention comprises step:
Step 1, form shallow slot field oxygen and active area at silicon substrate.
Step 4, be that the described active area of mask in described grid structure both sides carries out a P type ion and inject to form the autoregistration source-drain area with described grid structure.
The process conditions that the 2nd P type ion of non-autoregistration source-drain area described in the step 5 injects are: implanted dopant is that boron or boron difluoride, implantation dosage are 1e13cm
-2～5e14cm
-2, the injection energy is 20KeV～100KeV.The junction depth of described non-autoregistration source-drain area is 1.1 times～2 times of junction depth of described autoregistration source-drain area.
The present invention can improve the pattern of 5 volts of PMOS device source/leakage PN junctions, thereby has improved the puncture voltage of its PN junction.5 FuPMOSYuan/leakage PN junction puncture voltage raising amount after optimizing is greater than 1 volt, and fashionable operating voltage is wiped and write to corresponding SONOS information of flash memory also can improve 1 volt on original basis, so the erasable speed of SONOS flash memory can improve greatly.When properties of product improved, the testing time of SONOS flash memory also can reduce, thereby can save the product test cost.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is the structural representation of 5 volts of PMOS devices in the existing SONOS technology;
Fig. 2 is the structural representation in the manufacture method of 5 volts of PMOS devices in the embodiment of the invention SONOS technology;
Fig. 3 is the structural representation of 5 volts of PMOS devices in the embodiment of the invention SONOS technology;
Fig. 4 is the structure of 5 volts of PMOS devices schematic diagram relatively in 5 volts of PMOS devices and the embodiment of the invention SONOS technology in the existing SONOS technology.
Embodiment
As shown in Figure 3, be the structural representation of 5 volts of PMOS devices in the embodiment of the invention SONOS technology.5 volts of PMOS devices are formed on the silicon substrate 6 in the embodiment of the invention SONOS technology, and described silicon substrate 6 is formed with a N trap for the N-type silicon substrate or at silicon substrate; Active area is that shallow slot field oxygen 2 is isolated by shallow trench isolation from (STI).Described PMOS device comprises:
Be formed at the grid structure on the described active area, described grid structure comprises gate oxide 5 and polysilicon gate 3, also is formed with gate lateral wall 4 at the sidewall of described grid structure.
Be formed at the P type source-drain area 1 in described grid structure both sides, the described active area and be formed at N-type channel region in the described active area in the middle of described grid structure bottom, the described P type source-drain area.Wherein, the junction depth near described shallow slot field oxygen 2 one sides of described P type source-drain area 1 is darker than the junction depth near described N-type channel region one side, and the junction depth of close described shallow slot field oxygen one side of described P type source-drain area 1 is 1.1 times～2 times of junction depth of close described N-type channel region one side.Wherein, described P type source-drain area 1 is made up of autoregistration source-drain area and non-autoregistration source-drain area.Described autoregistration source-drain area is formed at described N-type channel region edge between oxygen 2 edges, described shallow slot field by self-registered technology.The formation zone of described non-autoregistration source-drain area defines by photoetching process, the opposite side of adjacent, the described non-autoregistration source-drain area of a side of described non-autoregistration source-drain area and oxygen edge, described shallow slot field and the described channel region edge lateral separation of being separated by; The junction depth of described non-autoregistration source-drain area is greater than the junction depth of described autoregistration source-drain area.Described non-autoregistration source-drain area inject to form by P type ion, and the process conditions that the P type ion of described non-autoregistration source-drain area injects are: implanted dopant is that boron or boron difluoride, implantation dosage are 1e13cm
-2～5e14cm
-2, the injection energy is 20KeV～100KeV.
Fig. 2 is the manufacture method of 5 volts of PMOS devices in the embodiment of the invention SONOS technology
The manufacture method of 5 volts of PMOS devices in the embodiment of the invention SONOS technology comprises step:
Step 1, as shown in Figure 2 forms shallow slot field oxygen 2 and active areas at silicon substrate 6.Described silicon substrate 6 is formed with a N trap for the N-type silicon substrate or at silicon substrate.
Step 4, as shown in Figure 2 is that the described active area of mask in described grid structure both sides carries out a P type ion and inject and form the autoregistration source-drain area with described grid structure.Described autoregistration source-drain area can comprise that one is that the lightly-doped source drain region (LDD) and of mask is the heavy-doped source drain region of mask with polysilicon gate 3 and gate lateral wall 4 with polysilicon gate 3.
As shown in Figure 4, be the structure of 5 volts of PMOS devices schematic diagram relatively in 5 volts of PMOS devices and the embodiment of the invention SONOS technology in the existing SONOS technology.The source of 5 volts of PMOS devices/leakage PN junction 9 can upwarp in described shallow slot field oxygen 2 one sides in the existing SONOS technology, the source of 5 volts of PMOS devices/leakage PN junction 8 has then improved the pattern that upwarps of the prior art in the SONOS technology of the present invention, the present invention is by adding described non-autoregistration source-drain area, increase described P type source-drain area near the junction depth at oxygen 2 places, described shallow slot field, thereby can increase the puncture voltage of the source/leakage PN junction 8 of 5 volts of PMOS devices in the SONOS technology of the present invention.
More than by specific embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (6)
1. 5 volts of PMOS devices in the SONOS technology, be formed on the silicon substrate, active area is isolated by shallow slot field oxygen, the PMOS device comprises: be formed at the grid structure on the described active area, be formed at the P type source-drain area in described grid structure both sides, the described active area and be formed at N-type channel region in the described active area in the middle of described grid structure bottom, the described P type source-drain area; It is characterized in that: the junction depth near described shallow slot field oxygen one side of described P type source-drain area is darker than the junction depth near described N-type channel region one side;
Described P type source-drain area is made up of autoregistration source-drain area and non-autoregistration source-drain area; Described autoregistration source-drain area is formed at described N-type channel region edge between oxygen edge, described shallow slot field by self-registered technology; The formation zone of described non-autoregistration source-drain area defines by photoetching process, the opposite side of adjacent, the described non-autoregistration source-drain area of a side of described non-autoregistration source-drain area and oxygen edge, described shallow slot field and the described channel region edge lateral separation of being separated by; The junction depth of described non-autoregistration source-drain area is greater than the junction depth of described autoregistration source-drain area.
2. 5 volts of PMOS devices in the SONOS technology as claimed in claim 1, it is characterized in that: described non-autoregistration source-drain area inject to form by P type ion, and the process conditions that the P type ion of described non-autoregistration source-drain area injects are: implanted dopant is that boron or boron difluoride, implantation dosage are 1e13cm
-2～5e14cm
-2, the injection energy is 20KeV～100KeV.
3. 5 volts of PMOS devices in the SONOS technology as claimed in claim 1 is characterized in that: the junction depth of close described shallow slot field oxygen one side of described P type source-drain area is 1.1 times～2 times near the junction depth of described N-type channel region one side.
4. the manufacture method of 5 volts of PMOS devices in the SONOS technology comprises step:
Step 1, form shallow slot field oxygen and active area at silicon substrate;
Step 2, in described active area, form the N-type channel region;
Step 3, form grid structure at described active area;
Step 4, be that the described active area of mask in described grid structure both sides carries out a P type ion and inject to form the autoregistration source-drain area with described grid structure;
It is characterized in that, also comprise the steps:
Step 5, define the formation zone of non-autoregistration source-drain area with photoetching process, the opposite side in the formation zone of adjacent, the described non-autoregistration source-drain area of a side in the formation zone of described non-autoregistration source-drain area and oxygen edge, described shallow slot field and the described channel region edge lateral separation of being separated by; In the formation zone of described non-autoregistration source-drain area, carry out the 2nd P type ion and inject the non-autoregistration source-drain area of formation; The junction depth of the described non-autoregistration source-drain area that forms is greater than the junction depth of described autoregistration source-drain area.
5. method as claimed in claim 4 is characterized in that: the process conditions that the 2nd P type ion of non-autoregistration source-drain area described in the step 5 injects are: implanted dopant is that boron or boron difluoride, implantation dosage are 1e13cm
-2～5e14cm
-2, the injection energy is 20KeV～100KeV.
6. method as claimed in claim 4 is characterized in that: the junction depth of described non-autoregistration source-drain area is 1.1 times～2 times of junction depth of described autoregistration source-drain area.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010290313 CN102412293B (en) | 2010-09-25 | 2010-09-25 | 5V PMOS (P-channel Metal Oxide Semiconductor) device in SONOS (Silicon Oxide Nitride Oxide Semiconductor) technique and fabrication method thereof |
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|---|---|---|---|
| CN 201010290313 CN102412293B (en) | 2010-09-25 | 2010-09-25 | 5V PMOS (P-channel Metal Oxide Semiconductor) device in SONOS (Silicon Oxide Nitride Oxide Semiconductor) technique and fabrication method thereof |
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| CN102412293B true CN102412293B (en) | 2013-09-11 |
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| CN100342506C (en) * | 2004-04-14 | 2007-10-10 | 中芯国际集成电路制造(上海)有限公司 | High operation voltage double spreading drain MOS device using twice ion injection |
| KR20050116976A (en) * | 2004-06-09 | 2005-12-14 | 동부아남반도체 주식회사 | Flash memory device and method for programming/erasing the same |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131223 |
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Effective date of registration: 20131223 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |