CN1221025C - Nitride ROM and its manufacture - Google Patents
Nitride ROM and its manufacture Download PDFInfo
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- CN1221025C CN1221025C CN 01123714 CN01123714A CN1221025C CN 1221025 C CN1221025 C CN 1221025C CN 01123714 CN01123714 CN 01123714 CN 01123714 A CN01123714 A CN 01123714A CN 1221025 C CN1221025 C CN 1221025C
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- separator
- silicon
- nitride
- clearance wall
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Abstract
The present invention relates to a manufacturing method of a nitride read only memory (NROM), which comprises: when an NROM unit is manufactured, firstly, one or a plurality of isolation layers are formed to cover an oxide-nitride-oxide (ONO) structure and a grid, and a SiN<x> spacer is formed to protect the NROM unit. Because if the SiN<x> spacer is directly in contact with the grid, the threshold voltage of NROM assemblies is caused to be increased, and thus, the single or multiple isolation layers made of SiO<y> is used for isolating the NROM assemblies from the SiN<x> spacer in the present invention. Not only can the NROM assemblies be protected, but also side effect caused by the SiN<x> spacer and a leakage current produced between assemblies can be avoided.
Description
Invention field
The present invention relates to a kind of nitride ROM (NitrideReadOnlyMemory; NROM) and manufacture method, particularly relate to a kind of manufacture method that on NROM, forms clearance wall (Spacer) with buffer action.
Background of invention
Please refer to Fig. 1, it is the profile of the structure of existing NROM unit.The forming process of this NROM unit is as follows: at first, utilize photoetching and for example Wet-type etching mode to define active region (ActiveArea) on base material 100, inject phosphonium ion (P with ion implantation (IonImplantation) in base material 100 again
-), and form channel (Channel) 104.Subsequently, deposit first oxide layer 108 and nitration case 110 in regular turn on base material 100, reoxidize deposition and form second oxide layer 112, wherein nitration case 110 is between first oxide layer 108 and second oxide layer 112.Utilize photoetching and etch process to define first oxide layer 108, nitration case 110 and second oxide layer 112 again, and form silicon oxide/silicon nitride/silicon oxide (Oxide-Nitride-Oxide; ONO) structure 114, and expose base material 100.
Then, deposit spathic silicon (Polysilicon) layer 116 covers second oxide layer 112, deposit metal silicide (Silicide) layer 118 again and cover polysilicon layer 116, utilize photoetching and etch process definition polysilicon layer 116 and metal silicide layer 118 equally, and form grid 120, and expose ONO structure 114.Subsequently, for example with chemical vapour deposition technique (ChemicalVaporDeposition; CVD) deposition layer of material layer covering substrates 100, ONO structure 114 and grid 120, wherein this material layer for example is silicon dioxide (SiO
2), four oxygen ethyl silicate (Tetra-Ethyl-Ortho-Silicate; TEOS) or silicon nitride (Si
3N
4) etc.And define this material layer with photoetching and anisotropic etching (AnisotropicEtch) mode, and form clearance wall 122.
Then, the structure of being formed with clearance wall 122 and grid 120 is a mask, and with phosphorus (P) or to the higher arsenic (As) of the solid solubility (SolidSolubility) of silicon (Si) is ion source (IonSource), base material 100 is carried out high concentration and the darker heavy doping (HeavyDoping) of the degree of depth, and form drain electrode (Drain) 102 and source electrode (Source) 106.After depositing a layer insulating 124 covering substrates 100, clearance wall 122 and grid 120, deposit internal layer medium (Inter-LevelDielectrics again; ILD) 126 cover insulating barrier 124.At this moment, the structure of existing NROM unit is finished.
Yet; in semiconductor fabrication backward; the NROM assembly can be subjected to the irradiation of ultraviolet ray (Ultra-Violet Light) or the intrusion of plasma ion usually; and excite atom in the NROM assembly; make the atom in the assembly become charged ion; therefore can cause the quantity of electric charge in the NROM assembly to increase, influence the electrical stability of assembly, and assembly is damaged.
Therefore, in the manufacture method of above-mentioned existing NROM, formed NROM unit can't shielding of ultraviolet or the penetrating of plasma ion, thereby makes the quantity of electric charge in the assembly increase, what cause assembly electrically presents labile state, and causes the qualification rate of product to reduce.
Summary of the invention
In order to overcome the deficiencies in the prior art; the manufacture method that the purpose of this invention is to provide a kind of nitride ROM; method of the present invention is when making the NROM unit; on grid and ONO structure, form protective layer; but the irradiation of this protective layer shielding of ultraviolet or the invasion of plasma ion; form charged ion to prevent that atom in the NROM assembly is subjected to exciting, and then protection and keep the electrical stability of assembly.
Another object of the present invention provides a kind of manufacture method of nitride ROM, uses the formed NROM of method of the present invention unit to have protective layer, and this protective layer is positioned on grid and the ONO structure, and by one or more layers isolated material and silicon nitride (Si
3N
4) clearance wall constitutes.Therefore, not only ultraviolet ray or plasma penetration can be prevented, and silicon nitride (Si can be avoided
3N
4) clearance wall directly contacts caused side effect with for example ONO assembly, for example threshold voltage raises, and also can avoid the injury of leakage current (LeakageCurrent) to assembly.
Another object of the present invention provides a kind of nitride ROM.
To achieve the above object, the invention provides the manufacture method of a kind of NROM, it comprises at least: a base material is provided, wherein is formed with silicon monoxide/nitrogenize silicon/oxidative silicon structure on this base material; Form the part that a grid covers this silicon oxide/silicon nitride/silicon oxide structure; Form another part that a separator covers this grid and this silicon oxide/silicon nitride/silicon oxide structure; Form a clearance wall, wherein this clearance wall is positioned at the sidewall of this separator; And form an insulating barrier and cover this base material, this clearance wall and this separator.
The present invention also provides a kind of nitride ROM, and it comprises at least: a base material wherein is formed with silicon monoxide nitrogenize silicon/oxidative silicon structure on this base material; One grid is positioned on this silicon oxide/silicon nitride/silicon oxide structure of part; One separator is positioned on another part of this grid and this silicon oxide/silicon nitride/silicon oxide structure; One clearance wall is positioned at the sidewall of this separator; And one insulating barrier be positioned on this base material, this clearance wall and this separator.
In other words, method of the present invention is on the ONO of NROM unit structure and grid, forms one deck separator at least earlier, forms silicon nitride gap wall again and constitutes the protection structure, and wherein the material of separator can for example be silica (SiO
y), and this separator is in order to isolate NROM assembly and silicon nitride gap wall.Because silicon nitride (Si
3N
4) directly contact the threshold voltage rising that can cause assembly with the NROM assembly; therefore; utilization the present invention formed protection structure can prevent the injury of ultraviolet ray or plasma and the threshold voltage of avoiding improving assembly simultaneously, and avoids producing leakage current between the assembly and injure assembly.
Advantage of the present invention is: method of the present invention is to utilize silicon nitride (Si
3N
4) clearance wall and one deck silica (SiO at least
y) separator, protect the NROM assembly.Wherein, separator is between NROM assembly and clearance wall, in order to isolate NROM assembly and clearance wall.Therefore, utilization the present invention not only can protect the NROM assembly, ultraviolet ray and plasma ion can't be penetrated and injures the electrical stability of assembly, and can avoid NROM assembly and silicon nitride (Si
3N
4) the high threshold voltage that caused of clearance wall contact, and can prevent the generation of NROM inter-module leakage current.
Description of drawings
The present invention is described in detail below in conjunction with drawings and Examples:
Fig. 1 is the profile of existing NROM cellular construction;
Fig. 2 is the profile of the NROM cellular construction of a preferred embodiment of the present invention;
Fig. 3 is the profile of another preferred embodiment of the present invention NROM cellular construction.
Symbol description among the figure
102 drain electrodes of 100 base materials
104 channels, 106 source electrodes
108 first oxide layers, 110 nitration cases
112 second oxide layers, 114 ONO structures
116 polysilicon layers, 118 metal silicide layers
120 grids, 122 clearance walls
124 insulating barriers, 126 internal layer media
202 drain electrodes of 200 base materials
204 channels, 206 source electrodes
208 first oxide layers, 210 nitration cases
212 second oxide layers, 214 ONO structures
216 polysilicon layers, 218 metal silicide layers
220 grids, 222 separators
224 clearance walls, 226 insulating barriers
228 internal layer media, 252 first separators
254 second separators 256 the 3rd separator
258 clearance walls, 260 insulating barriers
262 internal layer media
Embodiment
Generally, if will delete EPROM (Erasable Programmable Read Only Memory) (ErasableProgrammableReadOnlyMemory; EPROM) in during stored data, be that whole EPROM is placed ultraviolet ray approximate number ten minutes down, make the ultraviolet energy of Electron absorption in the floating grid (FloatingGate) that sinks into (Trap) EPROM and from floating grid, escape, to finish the deletion of data.Yet, NROM is different with EPROM, NROM not only can't utilize ultraviolet ray to delete its stored data, and the atom in the NROM assembly is subjected to ultraviolet irradiation and but can be excited into charged ion, and cause the electric charge in the NROM assembly to increase, influence the electrical stability of assembly, and then assembly is damaged.Therefore, NROM need have the structure that ultraviolet ray can be isolated in outside the assembly.
On the other hand, in the manufacture process of NROM, employed plasma ion unavoidablely can penetrate and enter in the NROM unit, atomic reaction in plasma ion and the NROM and make atom become charged ion, therefore cause the quantity of electric charge in the assembly to increase, reduce the electrical stability of NROM assembly.By above narration as can be known, the structure that the NROM unit needs protection is with shielding of ultraviolet and plasma.
Please refer to Fig. 2, it is the profile of structure of the NROM unit of a preferred embodiment of the present invention.At first, utilize photoetching and for example Wet-type etching mode to define base material 200, and on base material 200, be formed with source region.Utilize ion implantation in base material 200, to inject phosphonium ion (P again
-), and form channel 204.Then, deposit first oxide layer, 208 covering substrates 200, cvd nitride layer 210 covers first oxide layer 208 again, and last oxide deposition forms second oxide layer 212 and covers nitration case 210.Equally with photoetching and etching mode, first oxide layer 208, nitration case 210 and second oxide layer 212 are defined again, form the ONO structure 214 of silicon oxide/silicon nitride/silicon oxide, and expose base material 200.
Then, deposit spathic silicon layer 216 covers ONO structure 214, deposits metal silicide layer 218 again and covers polysilicon layer 216, and wherein polysilicon layer 216 is to adopt for example Low Pressure Chemical Vapor Deposition (LowPressureCVD with the deposition of metal silicide layer 218; LPCVD), and the material of metal silicide layer 218 for example be tungsten silicide (WSi
2) or titanium silicide (TiSi
2).Utilize photoetching and dry etch process again, define polysilicon layer 216 and metal silicide layer 218,, and expose ONO structure 214 with formation grid 220.
(Conformal) layer deposited isolating 222 conformally on grid 220 and ONO structure 214, wherein the material of separator 222 is silica (SiO
y).Afterwards, for example with plasma enhanced chemical vapor deposition method (PlasmaEnhancedCVD; PECVD) deposition one deck silicon nitride (Si
3N
4) covering substrates 200 and separator 222, and define this silicon nitride layer with photoetching and anisotropic etching mode, and form the clearance wall 224 of silicon nitride at separator 222 sidewalls.
Of the present invention one is characterised in that and utilizes silica (SiO
y) separator 222 and silicon nitride (Si
3N
4) the combination of clearance wall 224, be used as the protection structure of NROM assembly.This protection structure is by silicon nitride (Si
3N
4) clearance wall 224 prevent penetrating of ultraviolet ray and plasma ion, and by silica (SiO
y) separator 222 isolate silicon nitride and directly contact with the NROM assembly, raise with the threshold voltage of avoiding the NROM assembly, and can prevent to produce between the assembly leakage current phenomenon.
Subsequently, with phosphorus (P) or to the higher arsenic (As) of the solid solubility of silicon (Si) is ion source, and the structure of utilizing clearance wall 224 and separator 222 to be formed is mask, base material 200 carried out the heavy doping step of high depth and high concentration, and form drain electrode 202 and source electrode 206.Afterwards, behind depositing insulating layer 226 covering substrates 200, clearance wall 224 and the separator 222, deposit internal layer medium 228 again.
Please refer to Fig. 3, it is the profile of structure of the NROM unit of another preferred embodiment of the present invention.The structure of this NROM unit is conformally to deposit first separator 252, second separator 254 and the 3rd separator 256 in regular turn on the ONO structure 214 of the NROM of Fig. 2 cellular construction and grid 220, and wherein the material of first separator 252, second separator 254 and the 3rd separator 256 is silica (SiO
y), but the component prescription of these three layers of separators is not quite similar.
Then, for example with plasma enhanced chemical vapor deposition method (PlasmaEnhancedCVD; PECVD) deposition one deck silicon nitride (Si
3N
4) covering substrates 200 and the 3rd separator 256, and utilize photoetching and anisotropic etching mode to define this silicon nitride layer, and form the clearance wall 258 of silicon nitride at the 3rd separator 256 sidewalls.Then, depositing insulating layer 260 covering substrates 200, clearance wall 258 and the 3rd separator 256 deposit internal layer medium 262 again.
Because above-mentioned NROM structure forms three layers of separator on 220 layers of ONO structure 214 and grids, i.e. first separator 252, second separator 254 and the 3rd separator 256 are though its material is all silica (SiO
y), but adjacently in three layers of silica appoint two-layer prescription inequality.Therefore, this NROM structure has more multiple tracks separator, not only can avoid silicon nitride (Si
3N
4) directly contact the side effect that is caused with the NROM assembly, for example threshold voltage improves, also can avoid assembly between produce leakage current and injure assembly.
As understood by those skilled in the art, the above is preferred embodiment of the present invention only, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in protection scope of the present invention.
Claims (21)
1. the manufacture method of a nitride ROM comprises at least:
One base material is provided, wherein is formed with silicon monoxide/nitrogenize silicon/oxidative silicon structure on this base material;
Form the part that a grid covers this silicon oxide/silicon nitride/silicon oxide structure;
Form another part that a separator covers this grid and this silicon oxide/silicon nitride/silicon oxide structure;
Form a clearance wall, wherein this clearance wall is positioned at the sidewall of this separator; And
Form an insulating barrier and cover this base material, this clearance wall and this separator.
2. manufacture method according to claim 1 is characterized in that: this grid comprises a polysilicon layer and a metal silicide layer.
3. manufacture method according to claim 1 is characterized in that: the step that forms this separator is to adopt a conformal deposition.
4. manufacture method according to claim 1 is characterized in that: the material of this separator is a silicon monoxide.
5. according to the described manufacture method of claim, it is characterized in that: this separator and this clearance wall constitute a protection structure.
6. manufacture method according to claim 1 is characterized in that: the material of this clearance wall is a silicon nitride.
7. nitride ROM comprises at least:
One base material wherein is formed with silicon monoxide/nitrogenize silicon/oxidative silicon structure on this base material;
One grid is positioned on this silicon oxide/silicon nitride/silicon oxide structure of part;
One separator is positioned on another part of this grid and this silicon oxide/silicon nitride/silicon oxide structure;
One clearance wall is positioned at the sidewall of this separator; And
One insulating barrier is positioned on this base material, this clearance wall and this separator.
8. nitride ROM according to claim 7 is characterized in that: the formation of this separator is to utilize a conformal deposition step.
9. nitride ROM according to claim 7 is characterized in that: the material of this separator is a silicon monoxide.
10. nitride ROM according to claim 7 is characterized in that: this separator and this clearance wall constitute a protection structure.
11. nitride ROM according to claim 7 is characterized in that: the material of this clearance wall is a silicon nitride.
12. the manufacture method of a nitride ROM comprises at least:
One base material is provided, wherein is formed with silicon monoxide/nitrogenize silicon/oxidative silicon structure on this base material;
Form the part that a grid covers this silicon oxide/silicon nitride/silicon oxide structure;
Form another part that a plurality of separators cover this grid and this silicon oxide/silicon nitride/silicon oxide structure;
Form a clearance wall, wherein this clearance wall is positioned at the sidewall of this separator; And
Form an insulating barrier and cover this base material, this clearance wall and this separator.
13. manufacture method according to claim 12 is characterized in that: the step that forms this separator is to adopt a conformal deposition.
14. manufacture method according to claim 12 is characterized in that: the material of this separator is to be selected from silica, and adjacently in this separator appoints two-layer material composition inequality.
15. manufacture method according to claim 12 is characterized in that: this separator and this clearance wall constitute a protection structure.
16. manufacture method according to claim 12 is characterized in that: and the material of this clearance wall is a silicon nitride.
17. a nitride ROM comprises at least:
One base material wherein is formed with silicon monoxide/nitrogenize silicon/oxidative silicon structure on this base material;
One grid is positioned on this silicon oxide/silicon nitride/silicon oxide structure of part;
A plurality of separators are positioned on another part of this grid and this silicon oxide/silicon nitride/silicon oxide structure;
One clearance wall is positioned at the sidewall of this separator; And
One insulating barrier is positioned on this base material, this clearance wall and this separator.
18. nitride ROM according to claim 17 is characterized in that: the formation of this separator is to utilize a conformal deposition step.
19. nitride ROM according to claim 17 is characterized in that: the material of this separator is to be selected from silica, and adjacently in this separator appoints two-layer material composition inequality.
20. nitride ROM according to claim 17 is characterized in that: this separator and this clearance wall constitute a protection structure.
21. nitride ROM according to claim 17 is characterized in that: the material of this clearance wall is a silicon nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01123714 CN1221025C (en) | 2001-07-27 | 2001-07-27 | Nitride ROM and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01123714 CN1221025C (en) | 2001-07-27 | 2001-07-27 | Nitride ROM and its manufacture |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1399331A CN1399331A (en) | 2003-02-26 |
| CN1221025C true CN1221025C (en) | 2005-09-28 |
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ID=4665238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01123714 Expired - Fee Related CN1221025C (en) | 2001-07-27 | 2001-07-27 | Nitride ROM and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1221025C (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7184315B2 (en) * | 2003-11-04 | 2007-02-27 | Micron Technology, Inc. | NROM flash memory with self-aligned structural charge separation |
| KR100525448B1 (en) * | 2004-04-30 | 2005-11-02 | 동부아남반도체 주식회사 | Method for fabricating of flash memory device |
| US7205186B2 (en) * | 2004-12-29 | 2007-04-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for suppressing oxide formation |
| US20060223267A1 (en) * | 2005-03-31 | 2006-10-05 | Stefan Machill | Method of production of charge-trapping memory devices |
| CN100468780C (en) * | 2006-06-09 | 2009-03-11 | 北京大学 | Preparation method of NROM flash control grid and flash unit |
| CN102412293B (en) * | 2010-09-25 | 2013-09-11 | 上海华虹Nec电子有限公司 | 5V PMOS (P-channel Metal Oxide Semiconductor) device in SONOS (Silicon Oxide Nitride Oxide Semiconductor) technique and fabrication method thereof |
-
2001
- 2001-07-27 CN CN 01123714 patent/CN1221025C/en not_active Expired - Fee Related
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| CN1399331A (en) | 2003-02-26 |
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