KR20040095975A - Method for fabricating semiconductor device having electro static discharge device - Google Patents

Abstract

PURPOSE: A method for manufacturing semiconductor device is provided to raise doping density of a low doped P-type impurity region sufficiently, thereby preventing junction leakage current by selectively forming a high doped N-type impurity region under only drain region of the electro static discharge device. CONSTITUTION: A normal device region and an electro static discharge device region are designated in a substrate(11). The normal device region includes a gate electrode(15a), a source and a drain regions(16a,17a). The electro static discharge device region includes a gate electrode(15b), a source and a drain regions(16b,17b). The electro static discharge device region further includes a first conductive type(high doped N-type) impurity region(19) formed under the drain region and a second conductive type(low doped P-type) impurity region(20) formed under the first conductive type impurity region.

Description

Method for manufacturing a semiconductor device having an electrostatic discharge device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING ELECTRO STATIC DISCHARGE DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an electrostatic discharge element, and more particularly, to a method for manufacturing a semiconductor element with an electrostatic discharge element capable of preventing the occurrence of a junction leakage current.

In general, a semiconductor device is used after being fabricated in a wafer state and then cut and packaged into chips. When an electrostatic discharge (ESD) generated by a human body is applied during a manufacturing process or transportation in a wafer state or a package state, an instant is applied. A high voltage above 4000V is applied to destroy the device.

Such internal circuit damage is caused by joule heat caused by the charge injected through the input pad when ESD is applied and finally exits to another terminal through the internal circuit. That is, damage to the internal circuit as described above occurs due to junction spiking and oxide rupture caused by the Joule heat.

To solve this problem, insert an electrostatic discharge protection circuit that discharges the charge injected into the input pad directly to the power supply terminal before the injected charge is discharged through the internal circuit. prevent.

On the other hand, the ESD protection device is a field transistor that consumes most of the current when the ESD is applied between the input pad and the internal circuit, a gate ground NMOS transistor to protect the gate insulating film of the internal circuit, and excessive current flow into the NMOS transistor. It consists of a circuit with a resistance to prevent it.

In the ESD protection field transistor, an N + impurity diffusion region, which is a source / drain region of the field transistor, is formed on one side and the other side of the device isolation layer formed on the semiconductor substrate having the P well. The N + impurity diffusion region on one side is connected to an input pin, and the N + impurity diffusion region on the other side is connected to VSS.

Such an ESD protection device destroys the protection element itself when ESD is applied, among which the drain region of the field transistor is mainly damaged. This is because the drain region is integrated with the input pin.

In addition, the conventional electrostatic discharge device forms a P- impurity diffusion region by implanting P− ions under an N + impurity diffusion region on one side to form a Zener Breakdown to improve its characteristics.

As a result, the doping concentration of the P well under the N + impurity diffusion region increases due to the implantation of P- ions, and the boundary of the junction moves to the surface. Problems causing junction leakage currents occur.

In particular, as the thickness of the sub-micron increases, the thickness of the gate oxide layer becomes thinner, and thus, a greater width reduction of the junction breakdown voltage is urgently required. This requires an increase in the doping concentration of P- ions. However, in the prior art, there is a limit to increasing the doping concentration of P- ions due to the concern of junction leakage current.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and has a semiconductor device having an electrostatic discharge device suitable for sufficiently increasing the doping concentration of P- ions and preventing the occurrence of junction leakage current. The purpose is to provide a method.

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device having an electrostatic discharge device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

11: semiconductor substrate 12: device isolation film

13: first conductivity type well region 14: gate insulating film

15a, 15b: gate electrodes 16a, 16b: source region

17a, 17b: drain region 18: photosensitive film

19: second conductivity type (N +) impurity region 20: first conductivity type (P−) impurity region

21: silicide layer

According to an aspect of the present invention for achieving the above technical problem, a step of stacking a gate insulating film and a gate electrode in each region of the substrate in which the general element region and the electrostatic discharge element region defined; Forming a source / drain region on the substrate on both sides of the gate electrode; Forming a first conductivity type impurity region only below the drain region of the electrostatic discharge element region by using an ion implantation mask; Forming a second conductivity type impurity region only below the first conductivity type impurity region of the electrostatic discharge element region; There is provided a method of manufacturing a semiconductor device having an electrostatic discharge device, comprising the step of selectively forming a silicide layer in the source / drain regions of each region.

Or less, to introduce a method of manufacturing a semiconductor device having a capacitive discharge device according to a preferred embodiment of the present invention in order to enable those skilled in the art to more easily carry out the present invention. do.

In the method of manufacturing a semiconductor device having an electrostatic discharge device according to the present invention, as shown in FIG. 1A, the device isolation film 12 is formed in an isolation region of the semiconductor substrate 11 in which an active region and an isolation region are defined. Thereafter, a first conductivity type (P type) well 13 is formed in the active region.

Next, gate insulating films 14a and 14b and gate electrodes 15a and 15b are stacked in one direction in the active regions of the general element region and the electrostatic discharge (ESD) element region, respectively. At this time, the gate insulating films 14a and 14b are formed to have a thickness of approximately 10 to 200 Å.

Hereinafter, the general device region is referred to as a first region, and the electrostatic discharge (ESD) device region is referred to as a second region.

In addition, second concentration ion-conductive ions (N +) are first injected into the semiconductor substrate 11 on both sides of the gate electrodes 15a and 15b of the first and second regions, so that the source regions 16a and 16b and the drain region ( 17a, 17b) are formed, respectively. At this time, the high concentration of the second conductivity type ions (N +) is implanted to have a dose of 1E15 ~ 5E16, the ion implantation energy proceeds to 20KeV ~ 80KeV.

Thereafter, sidewall spacers are formed on both side surfaces of the gate electrodes 15a and 15b.

Subsequently, as illustrated in FIG. 1B, the photosensitive film 18 is coated on the entire surface of the semiconductor substrate 11, and the photosensitive film 18 is patterned so that the drain region 17b of the second region is opened by the exposure and development processes.

At this time, the open area is sufficiently spaced apart from the gate electrode in order not to affect the characteristics of the transistor, which is a general device. For example, spaced apart by 0.7 to 2 times the joint depth.

Subsequently, in order to deepen the junction depth of the drain region 17b of the second region, as shown in FIG. 1C, the patterned photosensitive film 18 is masked with a second concentration at a lower portion of the drain region 17b of the second region. The second conductivity type ions (N +) are implanted to form a second conductivity type impurity region (N + impurity region) 19. At this time, a high concentration of the second conductivity type ion (N +) is implanted to have a dose amount of 1E15 to 5E16, and the ion implantation energy proceeds to 50KeV to 200KeV.

Next, a low concentration of first conductivity type ions P- is implanted into the lower portion of the second conductivity type impurity region 19 to form a zener diode using the patterned photoresist 18 as a mask. P- impurity region) 20 is formed. Thereafter, the photosensitive film 18 is removed. At this time, the low concentration of the first conductivity type ions P- is implanted to have a dose of 1E13 to 1E15, and the ion implantation energy proceeds to 50KeV to 200KeV.

As described above, the second conductivity type impurity region (N + impurity region) 19 is further formed only below the drain region 17b of the second region, thereby increasing the P-ion implantation concentration of the first conductivity type impurity region 20. The range which can be made can be expanded, and it can prevent that a junction leakage current arises by this.

Subsequently, as illustrated in FIG. 1D, the silicide layer 21 is selectively formed on the source regions 16a and 16b and the drain regions 17a and 17b of the first and second regions.

In this case, the silicide layer 21 may be formed by forming a mask on the gate electrodes 15a and 15b and depositing a metal layer on the entire surface, followed by heat treatment, and then removing the unreacted metal layer. 15b) It may be formed by sputter deposition to be formed only on the source regions 16a and 16b and the drain regions 17a and 17b except for the surface.

After that, although not shown in the drawing, an insulating film is deposited on the entire surface of the semiconductor substrate 11, and the insulating film is etched to open each source / drain region, thereby forming a contact hole, and then applying an electrode on the contact hole and the insulating film adjacent thereto. The process of forming a metal layer for further proceeds.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The manufacturing method of the semiconductor device provided with the static discharge element of this invention mentioned above has the following effects.

By selectively forming a second conductivity type impurity region (N + impurity region) only below the drain region of the electrostatic discharge element region, the range in which the P-ion implantation concentration of the first conductivity type impurity region can be increased can be increased. This can prevent the junction leakage current from occurring.

Claims (7)

Stacking a gate insulating film and a gate electrode on each region of the substrate in which the general device region and the electrostatic discharge device region are defined; Forming a source / drain region on the substrate on both sides of the gate electrode; Forming a first conductivity type impurity region only below the drain region of the electrostatic discharge element region by using an ion implantation mask; Forming a second conductivity type impurity region only below the first conductivity type impurity region of the electrostatic discharge element region; And selectively forming a silicide layer in the source / drain regions of each of the regions. The method of claim 1, The first conductive impurity region is a semiconductor device manufacturing method having an electrostatic discharge element, characterized in that the N + impurity region. The method of claim 1, And said second conductivity type impurity region is a P- impurity region. The method of claim 1, The source / drain region is implanted with a first conductive ions having a dose of 1E15 ~ 5E16, the ion implantation energy is formed to be 20KeV ~ 80KeV, the method of manufacturing a semiconductor device having a static discharge device. The method of claim 1, The first conductivity type impurity region implants the first conductivity type ion to have a dose of 1E15 to 5E16, and the ion implantation energy is formed to be 50KeV to 200KeV. Way. The method of claim 1, The second conductivity type impurity region is implanted with a second conductivity type ion having a dose amount of 1E13 ~ 1E15, and the ion implantation energy is formed to be 20KeV ~ 200KeV, manufacturing a semiconductor device having a static discharge device Way. The method of claim 1, The ion implantation mask is a method of manufacturing a semiconductor device having an electrostatic discharge device, characterized in that the portion of the electrostatic discharge device region of the gate electrode from the gate electrode of 0.7 to 2 times the junction depth is opened.