KR20040081940A - Electro static discharge protection device - Google Patents

Abstract

PURPOSE: An ESD(Electro-Static Discharge) protection device is provided to reduce chip size and to prevent focusing of ESD stress current by increasing electrical resistance of an active region using counter doping. CONSTITUTION: An ESD protection device includes a well pick-up part(30) formed by the second dopant, an isolation layer(20), an active region doped by the first dopant, a source(40), a drain(50), and a gate(60). The active region further includes a resistance part(100). The resistance part is formed by counter doping of the second dopant.

Description

ESD protection device {ELECTRO STATIC DISCHARGE PROTECTION DEVICE}

The present invention relates to an ESD protection device, and more particularly, by counter-doping a dopant having an opposite polarity to an active region of a semiconductor device in which a single ion is irradiated to increase the electrical resistance of the active region. The present invention relates to an ESD protection device that not only distributes stress current flowing in an ESD situation but also improves ESD protection by securing a uniform stability resistance between fingers in a multi-finger structure.

As silicon chips become smaller and more integrated, the role of ESD protection devices that protect the chip's internal circuits from electrostatic discharge (ESD) is becoming important.

As shown in FIG. 1, in the case of a gate grounded N-type MOSFET (GGNMOS) or a gate grounded P-type MOSFET (GGPMOS), the source 40 and the drain ( 50, the depth of the active region constituting the active region is reduced, and there is a problem that the difference between the electrical resistance of the surface of the active region and the electrical resistance within the active region becomes large.

In particular, in the case of applying the process of forming the silicide layer 70 for forming the metallic pass on the surface of the active region, the difference in electrical resistance between the surface and the inside becomes large, and thus, from the input pad 15 in the event of ESD. Since most of the stress current flowing into the drain 50 is concentrated on the surface of the active region, there is a problem in that the characteristics of the ESD protection device are deteriorated.

In addition, in order to maximize the effectiveness of the ESD protection and the layout area (area required to configure the circuit), the important factor to consider when designing the ESD protection device of the multi-finger structure as shown in FIG. In order to effectively cope with ESD stress as a matter of triggering efficiency, each finger should be triggered uniformly. This is done between the contact 80 and the gate 60 inside the source 40 and drain 50. The existing electrical resistance, Ballast Resistance, must be maintained above a certain value.

On the other hand, in the case of a Very Large Scale Integration (VLSI) CMOS chip requiring high integration and high-speed operation of the chip, the silicide process is known as an efficient method for obtaining low contact resistance and low capacitance, and thus is almost practically used. It is true. However, as mentioned above, when the silicide process is performed, the electric resistance of the drain 50 side of the ESD protection device is inevitably lowered, resulting in a significant decrease in ESD protection. Therefore, in order to prevent silicide from being applied only to a portion that operates a general integrated circuit as shown in FIG. 3 and to prevent ESD, a process of separating the two portions is disclosed in US Pat. No. 5,994,176. have.

As shown here, a silicide layer 70 is formed in the gate electrode 60 and the source 40 / drain 50 region of the transistor 110 in the portion of the general integrated circuit that operates for the ESD protection. It can be seen that the silicide layer 70 is not formed by the blocking film 90 in the gate electrode 60 and the source 40 / drain 50 region of the transistor 120. That is, the part for general operation and the part for ESD protection are separated to form a silicide layer 70 to obtain characteristics such as speed, and the part for the ESD protection circuit is a silicide layer 70. We tried to get good characteristics during ESD operation by implementing stability resistor without applying.

However, in order to implement such an ESD protection device, an additional additional process such as the formation of the blocking film 90 is required, and in this case, there are problems in that the cost increases as the number of process steps increases. In addition, even if the portion for the ESD protection device does not apply the silicide layer 70, the surface resistance of the active region including the drain 50 is still smaller than the internal resistance of the active region, thereby preventing stress current concentration on the surface. There is no problem.

The above problems are summarized as follows.

First, as chip sizes shrink and their density increases, the layout area that can be allowed for the layout of ESD protection devices also becomes smaller. Therefore, when the area that can be used for the layout of the ESD protection device is reduced, the distance between the contact and the gate in the source / drain is inevitably reduced and it is difficult to maintain the stability resistance above a certain value. As such, when the stability resistance falls below a certain value, there is a problem in that the characteristics of the ESD protection device are deteriorated. In addition, even when employing a multi-finger ESD protection device it is difficult to ensure that each finger is uniformly triggered.

Second, as the integration density increases, the depth of the active region constituting the source / drain in GGNMOS or GGPMOS, which is generally used as an ESD protection device, is reduced, and the difference between the electrical resistance of the surface of the active region and the electrical resistance inside the active region is reduced. Becomes large. As the difference in electrical resistance between the active area surface and the inside increases, stress current flowing from the input pad to the drain is mostly concentrated on the surface of the active area in the event of ESD, thereby degrading the characteristics of the ESD protection device. There is this.

Third, in the case of VLSI CMOS chips requiring high integration and high-speed operation of the chip, the silicide process of forming a metallic path on the surface of the active region is known as an efficient method for obtaining low contact resistance and low capacitance. In the case of applying the actual or silicide process, it is more difficult to guarantee the characteristics of the ESD protection device or the uniform triggering of the multi-finger structure.

Fourth, in order to prevent the deterioration of the ESD protection device that occurs when the silicide process is applied, a process method that forms a silicide layer and a silicide layer is not developed on the ESD protection device has been developed. In order to implement a circuit, an additional additional process such as forming a barrier film is required, which increases the number of process steps as the additional process proceeds. As a result, there is a problem in that the cost increases and the part for the ESD protection device does not form a silicide layer. Even though the surface resistance of the active region including the drain is still smaller than the internal resistance of the active region, there is a problem in that stress current concentration on the surface cannot be prevented.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to counter-dope a dopant having an opposite polarity to an active region of a semiconductor device in which a single ion is irradiated, thereby counteracting the electrical resistance of the active region. In addition, the present invention provides an ESD protection device that not only uniformly distributes the stress current flowing in the ESD occurrence situation, but also improves the ESD protection function by securing a uniform stability resistance between the fingers in the multi-finger structure.

1 is a cross-sectional view showing a general ESD protection device.

2 is a plan view illustrating an ESD protection device having a general multi-finger structure.

3 is a cross-sectional view illustrating a state in which a silicide process is partially applied in a general ESD protection device.

4 is a cross-sectional view illustrating an ESD protection device according to an embodiment of the present invention.

5 is a cross-sectional view illustrating an ESD protection device according to another embodiment of the present invention.

6 is a cross-sectional view illustrating an ESD protection device according to still another embodiment of the present invention.

7 to 13 are plan views showing the layout of the resistor unit of the ESD protection device according to the present invention.

14 is a cross-sectional view illustrating a state in which a resistor unit according to the present invention is applied to an ESD protection device in which a silicide layer is not formed.

15 is a cross-sectional view illustrating a state in which a resistor unit according to the present invention is applied to an ESD protection device in which a silicide layer is formed in a block form.

16 is a plan view showing a state in which a resistor unit according to the present invention is applied to an ESD protection device having a multifinger structure.

17 is a cross-sectional view illustrating a state in which a resistor unit according to the present invention is applied to an ESD protection device having a stack gate structure.

-Explanation of symbols for the main parts of the drawings-

10: well 20: device isolation membrane

30: well pick-up unit 40: source

50: drain 60: gate

70: silicide layer 80: contact

90: blocking film 100: resistance portion

The present invention for achieving the above object is an ESD protection comprising a well pick-up portion formed by a second dopant, an isolation layer, an active region doped with the first dopant and a source / drain and a gate in the active region. The device may further include a resistor in which the second dopant having a polarity opposite to that of the first dopant is counter-doped.

The resistance unit is characterized in that the doped by the well pick-up unit implant.

In addition, the resistor portion is characterized in that the doped with the LDD implant by the second dopant.

In addition, the concentration of the second dopant is lower than the concentration of the first dopant.

In addition, the resistor unit is characterized in that one drain of the active region, or two sources and drains.

In addition, the resistor portion doped by the LDD implant is characterized in that applied to the CMOS device.

As described above, by forming a resistor part counter-doped with a drain of the active region or a concentration of a second dopant having a concentration lower than that of the first dopant doped in the active region in both the source and the drain, the contact between the drain and the source and the gate inside the source is formed. The ESD resistance can be improved by maintaining a stable resistance, which is an electrical resistance of the existing substrate, above a certain value.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

4 is a cross-sectional view showing an ESD protection device according to an embodiment of the present invention.

As shown here, a well 10 is formed on a semiconductor substrate, and the active region and the well pick-up portion 30 are separated by the device isolation layer 20, and the source 40 / drain 50 is disposed in the active region. And gate 60 are formed.

An LDD region is formed in an upper layer portion of the source 40, the drain 50, and the well pick-up portion 30, and a portion of the source 40 and the drain 50 is formed in a predetermined region of the source 40 and the drain 50. A counter-doped resistor unit 100 having a depth smaller than the depth is formed, and a silicide layer 70 is formed on the surfaces of the source 40 / drain 50 and the gate 60.

That is, the doping of n + ions pre-doped with a doping concentration of p ions counter-doped with p ions to the drain 50 of the GGNMOS doped n + ions or a portion of the source 40 and the drain 50, respectively. Doping is adjusted to less than the concentration.

Alternatively, a doping concentration of p + ions pre-doped with a doping concentration of n ions counter-doped with n ions to the drain 50 of the GGPMOS doped with p + ions or a portion of the source 40 and the drain 50, respectively. Adjust to smaller doping.

In this way, the electrical characteristics of the existing GGNMOS / GGPMOS are maintained as they are, but the high electrical portion of the drain 50 of the GGNMOS / GGPMOS, or a part of the source 40 and the drain 50, in particular, the upper layer of each region, is maintained. A resistor unit 100 having a resistance is formed.

Therefore, it is possible to maintain relatively high stability compared to the conventional method. In addition, since the resistance of the lower portion of the drain 50 or the source 40 and the drain 50, respectively, remains the same as in the conventional method, only the resistance of the upper portion is increased, so that the drain 50 or the source 40 and It is possible to alleviate the problem that the ESD stress current is concentrated in the upper portion of each of the drains 50.

5 is a cross-sectional view showing an ESD protection device according to another embodiment of the present invention.

In the present embodiment, when the well pick-up part 30 of the GGNMOS or the GGPMOS is formed as an ESD protection device, the dopant concentration of the well pick-up part 30 is increased by comparing the dopant concentration of the well pick-up part 30 with the dopant concentration of the active region. If low, the dopant of the well pick-up unit 30 is counter-doped to form the resistor unit 100. In this case, the depth of the resistor unit 100 is doped to be equal to the depth of the well pick-up unit 30.

That is, when the doping concentration of the p + implant of the well pick-up unit 30 in the GGNMOS is lower than the n + implant doping concentration of the active region, the p + implant of the well pick-up unit 30 is the drain 50 or the source 40 of the GGNMOS. Counter doping to each of the and drains 50 improves the ESD protection characteristics of the GGNMOS.

In this case, compared to the conventional process method, it is only necessary to change the photomask used for the p + implant of the well pick-up unit 30 and does not need to further manufacture the photomask or proceed the process further.

On the other hand, when the doping concentration of the n + implant of the well pick-up unit 30 in the GGPMOS is lower than the p + doping concentration of the active region, the n + implant of the well pick-up unit 30 is connected to the drain 50 or the source 40 of the GGPMOS. Counter doping of each of the drains 50 can improve the ESD protection characteristics of the GGPMOS.

In this case, compared with the conventional process method, it is only necessary to change the photomask used for the n + implant of the well pick-up unit 30, and there is no need to further manufacture the photomask or proceed the process further.

6 is a cross-sectional view showing an ESD protection device according to still another embodiment of the present invention.

As shown here, the resistor unit 100 is formed by doping with an LDD implant using a second dopant.

In other words, due to the nature of the LDD process of a CMOS chip, the p-LDD implant (or p + active implant) doping concentration is generally small compared to the n + active implant (or p + active implant) doping concentration. (Or n-LDD implant) can be counter-doped to the drain 50 of the GGNMOS / GGPMOS or each of the source 40 and the drain 50 to improve the ESD protection characteristics of the GGNMOS / GGPMOS.

In this case, the mask used for the p-LDD implant (or n-LDD implant) and the photomask used for the p + active implant (or n + active implant) could be used in the same manner as compared to the conventional process method. During the LDD implant (or n-LDD implant) process, the photomask is changed to allow the doping of the GGNMOS / GGPMOS drain 50 or the source 40 and drain 50 respectively. It is necessary to make one photomask each because it needs to be used differently from the photomask used for n + active implants). However, in the CMOS process, during the p-LDD implantation of GGPMOS, the counter region is doped in the active region of GGNMOS. 100) and counter-doped the active region of the GGPMOS to form the resistor unit 100 during the n-LDD implant of the GGNMOS. There is no need to proceed.

On the other hand, irrespective of the method of counter-doping the resistor unit 100 when forming the well pick-up unit 30 as described above, or counter-doping the resistor unit 100 at the time of the LDD implant, the implant is additionally p-type of the GGNMOS / GGPMOS. By counter-doping each of the drain 50 or the source 40 and the drain 50 to form the resistor unit 100 as shown in FIG. 4, the ESD protection characteristics of the GGNMOS can be improved. At this time, the concentration of the p-type additional implant is controlled lower than the doping concentration of the n + active implant.

In addition, the n-type additional implant may be counter-doped to the drain 50 of the GGPMOS or each of the source 40 and the drain 50 to form the resistor unit 100, thereby improving ESD protection characteristics of the GGPMOS. In this case, the doping concentration of the n-type additional implant is controlled lower than that of the p + active implant.

In this case, it is necessary to manufacture one additional photomask for each p-type additional implant, and it is necessary to add a process for proceeding with each additional implant. However, since it is possible to freely adjust the doping concentration and the doping depth of the counter-doped ions, there is a feature that it is easy to implement an optimal ESD protection operation.

In addition, the layout of the resistor unit 100 to increase the electrical resistance of the upper layer of the active region as described above can be configured as follows.

That is, as illustrated in FIG. 7, the resistor unit 100 may be formed by counter doping in a rectangular form including a drain 50 or a contact 80 formed in each of the source 40 and the drain 50, or FIG. 8. As shown in FIG. 9, except for the contact 80, the resistor 100 is formed by counter doping in a ring form around the contact 80, or as shown in FIG. 9, in the direction parallel to the gate 60. Counter doping is performed between the 80 and the gate 60 and between the contact 80 and the device isolation layer 20 to form the resistor unit 100, or as shown in FIG. 10, parallel to the gate 60. Counter-doped only between the contact 80 and the gate 60 in the direction to form the resistor unit 100, or as shown in FIG. 11, the contact 80 and the device isolation film 20 in a direction parallel to the gate 60. ) To form the resistor unit 100 only by counter doping, or as shown in FIG. The outer edge of the resistive portion 100 to be doped may be formed to contact the edge of the gate 60 or the edge of the isolation layer 20, and as shown in FIG. 13, the outer edge of the resistive portion 100 which is counter-doped. May be formed beyond the edge of the gate 60 or beyond the edge of the isolation layer 20.

The ESD protection device described above has been described in the case where the resistor portion 100 is formed by counter doping when the silicide layer is formed in the gate electrode and the source / drain regions, but as shown in FIG. 14, the silicide layer is formed in the gate electrode and the source / drain regions. The same applies even when this is not formed.

In addition, even when the silicide layer is formed as a block 75 in the source / drain region of the ESD protection device as shown in FIG. 15, the counter-doped resistor unit 100 is applied in the same manner to the source / drain region.

In addition, as shown in FIG. 16, each of the fingers may be uniformly triggered by applying the resistor unit 100 by counter-doping the source / drain regions of the ESD protection device having the multi-finger structure.

In addition, the counter-doped resistor unit 100 may be applied to the source / drain regions of the stack gate GGPMOS / GGNMOS as shown in FIG. 17.

As described above, according to the present invention, when the dopant having the opposite polarity in the active region of a semiconductor device irradiated with a single ion is counter-doped to the active region, the electrical resistance of the active region is increased to form an ESD protection device. Reduced area and increased integration reduces the area available for the layout of ESD protection devices. As a result, the stability resistance can be kept above a certain value even if the distance between the contact and the gate inside the drain / source is reduced. There is an advantage that can be improved.

In addition, since the stability resistance is maintained above a certain value, it is possible to ensure that the fingers are uniformly triggered even when the ESD protection element of the multi-finger structure is adopted.

In addition, the electrical resistance of the upper layer is increased, thereby improving the problem that the stress current flowing from the input pad to the drain is concentrated on the surface of the active region in the event of ESD.

In addition, even in the case of applying the silicide process of forming a metallic path on the surface of the active region in a VLSI CMOS chip requiring high-speed operation of the chip, it is possible to prevent the ESD stress current concentration by increasing the resistance by counter doping. There is an advantage to that.

In addition, when forming the counter-doped resistor in the active region, there is an advantage that it can be formed without additional processing by forming during well pick-up implant or LDD implant.

Claims (17)

An ESD protection device including a well pick-up part formed by a second dopant, an isolation layer, an active region doped with a first dopant, and a source / drain and a gate in the active region, And the resistive part counter-doped with a second dopant having a polarity opposite to that of the first dopant in the active region. The ESD protection device of claim 1, wherein the resistor unit is doped by the well pick-up unit implant. The ESD protection device of claim 1, wherein the resistor unit is doped by an LDD implant by a second dopant. 2. The ESD protection device according to claim 1, wherein the resistance part is one drain of the active region or two sources and drains. The ESD protection device according to any one of claims 1 to 4, wherein the concentration of the second dopant is lower than that of the first dopant. 4. The ESD protection device of claim 3, wherein the resistor portion doped by the LDD implant is applied to a CMOS device. The ESD protection device of claim 1, wherein a silicide layer is formed on the source / drain and the gate. The ESD protection device of claim 7, wherein the silicide layer is formed of blocks. The ESD protection device of claim 1, wherein the resistor unit has a rectangular shape including a contact formed in the drain or the source and the drain, respectively. The ESD protection device of claim 1, wherein the resistor unit has a ring shape around the contact except the contact. The ESD protection device of claim 1, wherein the resistor unit is formed in both the contact and the gate in a direction parallel to the gate and between the contact and the device isolation layer. The ESD protection device of claim 1, wherein the resistor unit is formed only between the contact and the gate in a direction parallel to the gate. The ESD protection device of claim 1, wherein the resistor unit is formed only between the contact and the device isolation layer in a direction parallel to the gate. The ESD protection device of claim 1, wherein the resistor unit is formed such that an outer edge of the resistor unit contacts the gate edge or the device isolation layer edge. The ESD protection device of claim 1, wherein the resistor unit is formed such that an outer edge of the resistor unit exceeds the gate edge or exceeds the device isolation layer edge. The ESD protection device of claim 1, wherein the ESD protection device has a multi-finger structure. 2. The ESD protection device of claim 1, wherein the ESD protection device has a stacked gate Morse structure.