KR20050108147A - Electro static discharge protection device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic discharge protection device such as transistors constituting a circuit in an electrostatic discharge protection circuit, wherein a well portion which contacts a bottom of a drain region or a drain / source region of a transistor by doping at a low concentration with impurities of a type opposite to the well. Since the impurity doping region for reducing the junction capacitance is formed by lowering the impurity doping concentration of, the junction capacitance of the electrostatic discharge protection device is reduced, thereby reducing the pin capacitance of the semiconductor integrated circuit mounted in the electronic system.

Description

Electrostatic discharge protection device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic discharge protection device constituting an electrostatic discharge protection circuit, and more particularly, to an electrostatic discharge protection device capable of reducing the junction capacitance of an electrostatic discharge protection device that occupies most of the pin capacitance.

When the semiconductor integrated circuit contacts the charged human body or machine, the static electricity that was charged on the human body or machine is discharged into the semiconductor integrated circuit through the input / output pads through the external pins of the semiconductor integrated circuit. It can seriously damage the internal circuit. Or static electricity, which has been charged in the internal circuits, can flow through the machine due to the machine's contact and damage the circuit. Most semiconductor integrated circuits install an electrostatic discharge protection circuit between the input / output pads and the internal circuits to protect the main circuit from such damage, and the input / output buffers also often provide static protection.

In general, an electrostatic discharge protection circuit is formed by configuring a circuit with an electrostatic discharge protection element such as a transistor and a resistor. 1 is a cross-sectional view of an NMOS transistor in a conventional electrostatic discharge protection device.

The NMOS transistor is an impurity concentration of 10 ¹⁵ dopant / cm ³ in the impurity concentration in the semiconductor substrate 100 of P-type is about 10 ¹⁷ to 10 ^19-well of the P-type dopant / cm ³ about the conventional electrostatic discharge protection device ( 110, an N-type drain region 120 and a source region 130 having an impurity concentration of about 10 ²⁰ to 10 ²² dopants / cm ³ are formed in the well 110, and the drain region ( A gate structure in which the gate insulating layer 140 and the gate 142 are stacked is formed on the well 110 between the 120 and the source region 130, and the interlayer insulating layer 150 is formed on the entire structure including the gate structure. A portion of the interlayer insulating layer 150 may be etched by a contact process, and a conductive material may be filled in the etched portion to form a drain contact 160 electrically connected to the drain region 120 and a source contact electrically connected to the source region 130. 162 and gate electrically connected to gate 142 Selecting (164), and a configuration is formed, a drain contact 160 is electrically connected to the I / O pad 190. The

FIG. 2 is an enlarged cross-sectional view of a drain region or a source region formed in the well of FIG. 1.

Due to the difference in carrier concentration at the PN junction where the N type drain region or source region 120 or 130 and the P type well 110 meet, the holes of the well 110 are either drain region or source region 120 or 130. The negative charge atom 220 is formed due to the negative ion atoms remaining on the well 110 side while moving toward the drain 110 and the electrons of the drain region or the source region 120 or 130 move toward the well 110, and the drain region or the source region 120 is formed. Or the positive charge layer 210 is formed due to the positive ion atoms remaining on the 130 side, and thus, a depletion layer 230 including the positive charge layer 210 and the negative charge layer 220 along the PN junction portion. Is formed. The depletion layer 230 is called a depletion layer because only ions are present in the depletion layer 230 and there are no holes or free electrons capable of conducting electricity, and wells 110 having opposite polarities with the depletion layer 230 interposed therebetween. ) And the drain region 120, or the well 110 and the source region 130 exhibit capacitance characteristics, which are called junction capacitances. Junction capacitance is proportional to the square root of the well 110 concentration of the PN junction portion. That is, the impurity concentration of the well (110) N _A La when C _j α _A √N.

Recently, with the development of manufacturing technology and the demand of the market, the speed of the electronic system is increasing rapidly, and the parasitic resistance, inductance, and capacitance, which are limiting factors in the high speed, have been continuously reduced. In response, the pin capacitance of semiconductor integrated circuits in these systems has been steadily decreasing, and the demand for reduction is expected to increase further in the future.

When a semiconductor integrated circuit is mounted in an electronic system and processes a signal, the input / output of the signal is made through an external pin of the chip. The pin capacitor is a parasitic capacitance felt as the signal is input / output through the pin. As is well known, this parasitic capacitance adversely affects signal transmission speed and signal integrity, so that the reduction of pin capacitance is necessary for the high speed of the electronic system. The pin capacitance of a semiconductor integrated circuit is largely a package capacitance generated from a package such as a lead or ball, and an on-chip capacitance generated from pads, transistors, and metal wirings inside the chip. Can be divided. Among these, the most contributing component to the pin capacitance is transistors used in large-size electrostatic protection circuits located near the input / output pads. Among the capacitances generated in the transistors, the junction capacitances generated in the drain region or the source region occupy 50% or more of the total fin capacitance.

Until now, various efforts have been made to reduce the pin capacitance, such as reducing the size of a transistor used in an electrostatic protection circuit. However, such an attempt has a side effect of damaging an input / output circuit characteristic or an electrostatic protection characteristic. Conventional electrostatic discharge protection device has a limit to cope with the speed of the semiconductor integrated circuit in the future.

Accordingly, an object of the present invention is to provide an electrostatic discharge protection device capable of improving the speed and reliability of a semiconductor integrated circuit by reducing the junction capacitance of the electrostatic discharge protection device that occupies most of the pin capacitance.

Electrostatic discharge protection device according to the first aspect of the present invention for achieving this object is a well formed in the semiconductor substrate by doping the first type impurities; First and second impurity diffusion regions formed to be spaced apart from each other in the well by doping a second type impurity of a type opposite to the first type impurity; And a third impurity diffusion region formed in contact with a bottom of the first impurity diffusion region and lower than an impurity doping concentration of the well.

The method further includes a fourth impurity diffusion region formed in contact with a bottom of the second impurity diffusion region and lower than an impurity doping concentration of the well.

The first impurity diffusion region is electrically connected to an input / output pad.

Since the third impurity diffusion region is doped with a third type impurity of the same type as the second type impurity, the well is formed by counter doping. When the first type impurities are P type, the second and third type impurities are N type, and when the first type impurities are N type, the second and third type impurities are P type.

In addition, the electrostatic discharge protection device according to the first aspect of the present invention comprises a well formed in the semiconductor substrate by doping the first type impurities; A drain region and a source region formed to be spaced apart from each other in the well by doping a second type impurity of a type opposite to the first type impurity; A gate structure formed between the drain region and the source region; And a first impurity diffusion region formed in contact with a bottom of the drain region and lower than an impurity doping concentration of the well.

The semiconductor device may further include a second impurity diffusion region formed in contact with a bottom of the source region and lower than an impurity doping concentration of the well.

An interlayer insulating film formed over the entire structure including the drain region, the source region and the gate structure; A drain contact electrically connected to the drain region; A source contact electrically connected to the source region; And a gate contact electrically connected with the gate.

A transistor including the drain region, the source region, and the gate structure formed in the well and having the first impurity diffusion region has a basic structure, and another transistor having the same structure as the transistor of the basic structure is added. Here, the transistors commonly use a drain region. The semiconductor device may further include a second impurity diffusion region formed in contact with a bottom of each of the source regions of the transistors and lower than an impurity doping concentration of the well.

A transistor including the drain region, the source region, and the gate structure formed in the well and having the first impurity diffusion region has a basic structure, and a plurality of other transistors having the same structure as the transistor of the basic structure are added. Here, the transistors commonly use a drain region and a source region formed between the gates of each transistor. The semiconductor device may further include a second impurity diffusion region formed in contact with a bottom of each of the source regions of the transistors and lower than an impurity doping concentration of the well.

The drain region is electrically connected to the input / output pads.

Since the first impurity diffusion region is doped with a third type impurity of the same type as the second type impurity, the well is formed by counter doping. When the first type impurities are P type, the second and third type impurities are N type, and when the first type impurities are N type, the second and third type impurities are P type.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only the present embodiment is provided to make the disclosure of the present invention complete, and to fully convey the scope of the invention to those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

On the other hand, when a film is described as being "on" another film or semiconductor substrate, the film may exist in direct contact with the other film or semiconductor substrate, or a third film may be interposed therebetween. In addition, the thickness or size of each layer in the drawings may be exaggerated for convenience and clarity of description. In the drawings, like numerals refer to like elements.

3 is a cross-sectional view of an electrostatic discharge protection device according to a first embodiment of the present invention having a structure in which two impurity diffusion regions are separated by a predetermined distance without a gate structure.

Referring to FIG. 3, the well 310 is formed in the semiconductor substrate 300 by doping the first type impurities. By doping a second type impurity of a type opposite to the first type impurity, a first impurity diffusion region 320 is formed in a portion of the well 310, spaced apart from the first impurity diffusion region 320 by a predetermined distance, and The second impurity diffusion region 330 is formed in another portion within 310. Since the third type impurity of the same type as the second type impurity (the type opposite to the first type impurity) is doped, the well 310 is counter-doped to contact the whole or part of the bottom of the first impurity diffusion region 320. The third impurity diffusion region 370 is formed at a lower impurity doping concentration than the impurity doping concentration of 310, and is in contact with the entire or a part of the bottom of the second impurity diffusion region 330 in comparison with the impurity doping concentration of the well 310. The fourth impurity diffusion region 380 is formed at a low impurity doping concentration. The input / output pad 390 is electrically connected to the first impurity diffusion region 320 or the second impurity diffusion region 330. As such, the impurity doping concentration of the well 310 in contact with the first and second impurity diffusion regions 320 and 330 is reduced by forming the third and fourth impurity diffusion regions 370 and 380, so that the junction capacitance is PN junction portion. By the principle of being proportional to the square root of the well concentration of the junction capacitance of the electrostatic discharge protection element is reduced, thereby reducing the pin capacitance of the semiconductor integrated circuit mounted in the electronic system.

On the other hand, the third and fourth impurity diffusion regions 370 and 380 are formed to reduce the junction capacitance of the electrostatic discharge protection element, and the input / output pads of the first and second impurity diffusion regions 320 and 330 ( 390 may be selectively formed only at the portion where the electrical connection is made. That is, when the input / output pad 390 is electrically connected to the first impurity diffusion region 320, only the third impurity diffusion region 370 is formed, and the input / output pad (the second impurity diffusion region 330) is formed. When the 390 is electrically connected, only the fourth impurity diffusion region 380 may be formed. This may be less effective in reducing the overall junction capacitance than when forming both the third and fourth impurity diffusion regions 370 and 380, but selectively in areas where junction capacitance most affects the input / output pad 390. Since the third or fourth impurity diffusion regions 370 or 380 are formed, the junction capacitance can be reduced to reduce the pin capacitance of the semiconductor integrated circuit mounted in the electronic system.

In the above, when the first type impurity is P type, the second and third type impurities are N type, and conversely, when the first type impurity is N type, the second and third type impurities are P type.

The well 310 is formed by a general well ion implantation process, and the impurity doping concentration value may vary depending on the characteristics of the device, and is not limited thereto. The first and second impurity diffusion regions 320 and 330 are formed by a general source / drain ion implantation process, and the impurity doping concentration values may vary depending on the characteristics of the device, and thus, the first and second impurity diffusion regions 320 and 330 are not limited thereto.

Since the third and fourth impurity diffusion regions 370 and 380 are formed in the bottom portions of the first and second impurity diffusion regions 320 and 330, the depths of the first and second impurity diffusion regions 320 and 330 are increased. The ion implantation energy that is considered is set, and since the impurity type to be implanted is the same type as the first and second impurity diffusion regions 320 and 330, the impurity ions pass through the first and second impurity regions 320 and 330. Dose amount of dopant ions adjusted to a low level does not affect the intrinsic impurity doping concentrations of the first and second impurity diffusion regions 320 and 330, so that the same type of region as the well 310 It is formed below the impurity doping concentration of the well 310. The impurity doping concentrations of the third and fourth impurity diffusion regions 370 and 380 may approximate or be substantially lower than the impurity doping concentration of the well 310 according to the dose of impurity ions to be implanted. It is not limited to a specific number because it can.

As described above, the impurity doping concentrations of the wells 310, the first and second impurity diffusion regions 320 and 330, and the third and fourth impurity diffusion regions 370 and 380, respectively, have a specific value according to the surrounding environment. Although it is difficult to limit, the case of a specific electrostatic discharge protection device having a structure in which two impurity diffusion regions are separated by a certain distance without a gate structure will be described as an embodiment. 10 ¹⁷ to 10 ¹⁹ dopant / cm ³ is formed of a P-type region, the first and second impurity diffusion regions 320 and 330 doped with N-type impurities, the impurity doping concentration is 10 ²⁰ to 10 ²² dopant / cm is formed in a ^third of the N-type region, the third and fourth impurity diffusion regions (370 and 380) is part of the well 310 is doped with a counter, so doped with N-type impurities 10 ¹⁵ to 5 × 10 ¹⁶ dopant It is formed into a P-type region of about ³ cm ³ . A process of forming the third and fourth impurity diffusion regions 370 and 380 will now be described in detail.

The third and fourth impurity diffusion regions 370 and 380 should be formed in contact with the whole or part of the bottom of the first and second impurity diffusion regions 320 and 330, and if the first and second impurity diffusion regions 320 and When formed on the side surface of the 330, the device acts as a cause of deteriorating the electrical characteristics between the third and fourth impurity diffusion regions 370 and 380 during the operation of the device, thereby lowering the electrical properties and reliability of the device. Accordingly, the third and fourth impurity diffusion regions 370 and 380 form a photoresist pattern such that only the bottom portions of the first and second impurity diffusion regions 320 and 330 are opened, and the first and second impurity diffusion regions ( Doping the N-type impurity with ion implantation energy considering the depth of 320 and 330, wherein the N-type impurity is the same type as the impurity doped in the first and second impurity diffusion regions 320 and 330 The concentration of the N-type impurity is about 10 ⁻⁴ lower than that of the first and second impurity diffusion regions 320 and 330 so as not to affect the impurity doping concentrations of the second impurity diffusion regions 320 and 330. As a result of this process, the P-type well 310 in contact with the bottom of the first and second impurity diffusion regions 320 and 330 is counter-doped so that the impurity doping concentration of the well 310 in this portion is 10 ¹⁵ to 5 x 10. P-type third and fourth impurity diffusion regions 370 and 380 of about ¹⁶ dopant / cm ³ are formed.

Since the junction capacitance of the electrostatic discharge protection device is proportional to the square root of the well concentration of the PN junction portion, the impurity doping concentration as in the present invention and the case where only the P type well 310 having an impurity doping concentration of about 10 ¹⁷ dopant / cm ³ exist compared to the 10 ¹⁵ to 5 × 10 ¹⁶ dopant / cm ³ around the P-type impurity diffusion regions (370 and 380), if present, the invention is ^{√ (5 × 10 16/10} 17) ~ √ (10 15 / 10 ¹⁷ ), that is, the junction capacitance is greatly reduced by about 2/3 to 1/10.

4 is a cross-sectional view of an electrostatic discharge protection device according to a second embodiment of the present invention having a transistor structure.

Referring to FIG. 4, the well 410 is formed in the semiconductor substrate 400 by doping the first type impurities. By doping a second type impurity of a type opposite to the first type impurity, a drain region 420 is formed in a portion within the well 410, spaced a distance from the drain region 420, and in another portion within the well 410 Source region 430 is formed. Since the third type impurity of the same type as the second type impurity (the type opposite to the first type impurity) is doped, the well 410 is counter-doped to contact the whole or part of the bottom of the drain region 420 so as to contact the well 410. The first impurity diffusion region 470 is formed at a lower impurity doping concentration than the impurity doping concentration, and the impurity doping concentration is lower than the impurity doping concentration of the well 410 in contact with the entire or part of the bottom of the source region 430. 2 impurity diffusion regions 480 are formed. A gate structure in which the gate insulating layer 440 and the gate 442 are stacked is formed on the well 410 between the drain region 420 and the source region 430. An interlayer insulating film 450 is formed on the entire structure including the gate structure. A portion of the interlayer insulating layer 450 is etched through a contact process and a conductive material is filled in the etched portion to drain the contact 460 and the source contact 462 electrically connected to the source region 430. And gate contacts 464 electrically connected to the gates 442, respectively. The drain contact 460 is electrically connected to the input / output pad 490. As such, the impurity doping concentration of the wells 410 in contact with the drain and source regions 420 and 430 is reduced by forming the first and second impurity diffusion regions 470 and 480, so that the junction capacitance is lower than the well concentration of the PN junction portion. The principle of proportional to the square root reduces the junction capacitance of the electrostatic discharge protection device, thereby reducing the pin capacitance of the semiconductor integrated circuit mounted in the electronic system.

On the other hand, the first and second impurity diffusion regions 470 and 480 are formed to reduce the junction capacitance of the electrostatic discharge protection element, and the input / output pads 490 of the drain and source regions 420 and 430 are electrically Only portions of the drain region 420 connected to each other may be selectively formed. This may be less effective in reducing the overall junction capacitance than when forming both the first and second impurity diffusion regions 470 and 480, but the drain region 420 where junction capacitance has the greatest impact on the input / output pad 490. Since the first impurity diffusion region 470 is selectively formed only in the ()) portion, the junction capacitance can be reduced to reduce the pin capacitance of the semiconductor integrated circuit mounted in the electronic system.

In the above, when the first type impurity is P type, the second and third type impurities are N type, and conversely, when the first type impurity is N type, the second and third type impurities are P type.

The well 410 is formed by a general well ion implantation process, and the impurity doping concentration value may vary depending on the characteristics of the device, and is not limited thereto. The drain and source regions 420 and 430 are formed by a general source / drain ion implantation process, and the impurity doping concentration values may vary depending on the characteristics of the device, and thus are not limited thereto.

Since the first and second impurity diffusion regions 470 and 480 are formed in the bottom portions of the drain and source regions 420 and 430, the ion implantation energy considering the depths of the drain and source regions 420 and 430 is set. Since the implanted impurity type is the same type as the drain and source regions 420 and 430, and impurity ions pass through the drain and source regions 420 and 430, the impurity doping concentrations inherent to the drain and source regions 420 and 430 Since an implanted dose of impurity ions is adjusted to be low enough so as not to affect, a region of the same type as the well 410 and lower than the impurity doping concentration of the well 410 is formed. The impurity doping concentrations of the first and second impurity diffusion regions 470 and 480 may approximate or be substantially lower than the impurity doping concentration of the well 410 according to the dose of impurity ions to be implanted. It is not limited to a specific number because it can.

As described above, the impurity doping concentration of each of the wells 410, the drain and source regions 420 and 430, and the first and second impurity diffusion regions 470 and 480 is difficult to be limited to a specific value according to the surrounding environment. In the case of a specific electrostatic discharge protection device having an NMOS transistor structure as an embodiment, the well 410 is doped with P-type impurities to a P-type region having an impurity doping concentration of about 10 ¹⁷ to 10 ¹⁹ dopants / cm ³ . The drain and source regions 420 and 430 are formed as N-type regions having an impurity doping concentration of about 10 ²⁰ to 10 ²² dopants / cm ³ by doping N-type impurities, and forming first and second impurity diffusion regions. 470 and 480 are doped with N-type impurities, so that a portion of the well 410 is counter-doped to form a P-type region of about 10 ¹⁵ to 5 × 10 ¹⁶ dopants / cm ³ . A process of forming the first and second impurity diffusion regions 470 and 480 will now be described in detail.

The first and second impurity diffusion regions 470 and 480 should be formed in contact with all or part of the bottoms of the drain and source regions 420 and 430, and if they are formed on the side surfaces of the drain and source regions 420 and 430. In operation of the device, the electric properties between the first and second impurity diffusion regions 470 and 480 may be deteriorated, thereby degrading the electric properties and reliability of the device. Accordingly, the first and second impurity diffusion regions 470 and 480 form a photoresist pattern so that only the bottom portions of the drain and source regions 420 and 430 are opened, and the depths of the drain and source regions 420 and 430 are considered. N-type impurities are doped with ion implantation energy, and since the N-type impurities are of the same type as those doped in the drain and source regions 420 and 430, the impurity doping concentrations of the drain and source regions 420 and 430 are affected. The concentration of the N-type impurity is set to be very low, such as 10 ⁻⁴ , compared to the drain and source regions 420 and 430. As a result of this process, the P-type well 410 in contact with the bottom of the drain and source regions 420 and 430 is counter-doped so that the impurity doping concentration of the well 410 in this portion is 10 ¹⁵ to 5 × 10 ¹⁶ dopants / P-type first and second impurity diffusion regions 470 and 480 of about ³ cm are formed.

Since the junction capacitance of the electrostatic discharge protection element is proportional to the square root of the well concentration of the PN junction portion, the impurity doping concentration as in the present invention and the case where only the P type well 410 having an impurity doping concentration of about 10 ¹⁷ dopant / cm ³ exists compared to the 10 ¹⁵ to 5 × 10 ¹⁶ dopant / cm ³ around the P-type impurity diffusion region (470 and 480), if present, the invention is ^{√ (5 × 10 16/10} 17) ~ √ (10 15 / 10 ¹⁷ ), that is, the junction capacitance is greatly reduced by about 2/3 to 1/10.

FIG. 5 is a cross-sectional view of an electrostatic discharge protection device according to a third embodiment of the present invention having a structure in which a pair of transistors share a drain, and the electrostatic discharge protection device according to the third embodiment of the present invention is described above. The transistor described in the second embodiment has a basic structure, and another transistor having the same structure as the transistor of the basic structure is added. The pair of transistors commonly use the drain region 420. A first impurity diffusion region 470 is formed in contact with the entire or a portion of the drain region 420 of the transistors, and is electrically connected to the input / output pad 490. The second impurity diffusion region 480 formed in contact with the entire or a part of the bottom of each of the source regions 430 of the transistors may be omitted.

Similar to the electrostatic discharge protection device according to the second embodiment of the present invention, the electrostatic discharge protection device according to the third embodiment of the present invention also controls the impurity doping concentration of the well 410 in contact with the drain and source regions 420 and 430. By forming and lowering the first and second impurity diffusion regions 470 and 480, the junction capacitance of the electrostatic discharge protection element is reduced by the principle that the junction capacitance is proportional to the square root of the well concentration of the PN junction portion, thereby reducing the electronic capacitance to the electronic system. The pin capacitance of the semiconductor integrated circuit mounted can be reduced.

6 is a cross-sectional view of an electrostatic discharge protection device according to a fourth embodiment of the present invention having a structure in which a plurality of transistors share a drain and a source, and the electrostatic discharge protection device according to the fourth embodiment of the present invention is described above. The transistor described in the second embodiment of the present invention has a basic structure, and a plurality of other transistors having the same structure as the transistor of the basic structure are added. The plurality of transistors commonly use the drain region 420 and the source region 430 formed between the gates 442 of each transistor. Each of the drain regions 420 of the transistors is formed in contact with an entirety or a part of a bottom thereof, and a first impurity diffusion region 470 is formed and electrically connected to the input / output pad 490. The second impurity diffusion region 480 formed in contact with the entire or a part of the bottom of each of the source regions 430 of the transistors may be omitted.

Similar to the electrostatic discharge protection device according to the second embodiment of the present invention, the electrostatic discharge protection device according to the fourth embodiment of the present invention also reduces the impurity doping concentration of the well 410 in contact with the drain and source regions 420 and 430. By forming and lowering the first and second impurity diffusion regions 470 and 480, the junction capacitance of the electrostatic discharge protection element is reduced by the principle that the junction capacitance is proportional to the square root of the well concentration of the PN junction portion, thereby reducing the electronic capacitance to the electronic system. The pin capacitance of the semiconductor integrated circuit mounted can be reduced.

As described above, the present invention lowers the impurity doping concentration of the well portion in contact with the drain region of the transistor or the bottom of the drain / source region by low-doped impurities of the opposite type to the well to form an impurity diffusion region for reducing the junction capacitance. In addition, the junction capacitance of the electrostatic discharge protection element is reduced, thereby reducing the pin capacitance of the semiconductor integrated circuit mounted in the electronic system, thereby improving the speed and reliability of the semiconductor integrated circuit.

1 is a cross-sectional view of an NMOS transistor in a conventional electrostatic discharge protection element;

2 is an enlarged cross-sectional view of a drain region or a source region formed in the well of FIG. 1;

3 is a cross-sectional view of an electrostatic discharge protection device according to a first embodiment of the present invention having a structure in which two impurity diffusion regions are separated by a predetermined distance without a gate structure;

4 is a sectional view of an electrostatic discharge protection element according to a second embodiment of the present invention having a transistor structure;

5 is a cross-sectional view of an electrostatic discharge protection device according to a third embodiment of the present invention having a structure in which a pair of transistors share a drain; And

6 is a cross-sectional view of an electrostatic discharge protection device according to a fourth embodiment of the present invention having a structure in which a plurality of transistors share a drain and a source.

<Explanation of symbols for the main parts of the drawings>

100, 300, 400: semiconductor substrate 110, 310, 410: well

120, 420: drain region 320: impurity diffusion region

130, 430: source region 330: impurity diffusion region

140, 440: gate insulating film 142, 442: gate

150 and 450: interlayer insulating film 160 and 460: drain contact

162, 462: source contact 164, 464: gate contact

370, 380, 470, 480: impurity diffusion region for reducing junction capacitance

190, 390, 490: input / output pads 210: positive charge layer

220: negative charge layer 230: depletion layer

Claims (19)

A well formed in the semiconductor substrate by doping the first type impurities; First and second impurity diffusion regions formed to be spaced apart from each other in the well by doping a second type impurity of a type opposite to the first type impurity; And And a third impurity diffusion region formed in contact with a bottom of the first impurity diffusion region and lower than an impurity doping concentration of the well. The method of claim 1, And a fourth impurity diffusion region formed in contact with a bottom of the second impurity diffusion region and lower than an impurity doping concentration of the well. The method of claim 1, And the first impurity diffusion region is electrically connected to an input / output pad. The method of claim 1, And the third impurity diffusion region is doped with a third type impurity of the same type as the second type impurity, so that the well is counter-doped. The method according to claim 1 or 4, Wherein the first type impurity is P type, and the second and third type impurities are N type. The method according to claim 1 or 4, Wherein the first type impurity is N type, and the second and third type impurities are P type. A well formed in the semiconductor substrate by doping the first type impurities; A drain region and a source region formed to be spaced apart from each other in the well by doping a second type impurity of a type opposite to the first type impurity; A gate structure formed between the drain region and the source region; And And a first impurity diffusion region formed in contact with a bottom of the drain region and lower than an impurity doping concentration of the well. The method of claim 7, wherein And a second impurity diffusion region formed in contact with a bottom of the source region and lower than an impurity doping concentration of the well. The method of claim 7, wherein An interlayer insulating film formed over the entire structure including the drain region, the source region and the gate structure; A drain contact electrically connected to the drain region; A source contact electrically connected to the source region; And And a gate contact electrically connected to the gate. The method of claim 7, wherein An electrostatic discharge including the drain region, the source region, and the gate structure formed in the well, and having a first impurity diffusion region as a basic structure, and having another transistor having the same structure as the transistor of the basic structure; Protection element. The method of claim 10, And the transistors share a drain region in common. The method of claim 10, And a second impurity diffusion region formed in contact with a bottom of each of the source regions of the transistors and lower than an impurity doping concentration of the well. The method of claim 7, wherein A static electricity including the drain region, the source region, and the gate structure formed in the well and having the first impurity diffusion region as a basic structure, and a plurality of other transistors having the same structure as the transistor of the basic structure are added Discharge protection element. The method of claim 13, And the transistors commonly use a drain region and a source region formed between gates of each transistor. The method of claim 13, And a second impurity diffusion region formed in contact with a bottom of each of the source regions of the transistors and lower than an impurity doping concentration of the well. The method according to any one of claims 7, 11 or 14, And the drain region is electrically connected to an input / output pad. The method of claim 7, wherein And the first impurity diffusion region is doped with a third type impurity of the same type as the second type impurity, so that the well is counter-doped. The method according to claim 7 or 17, Wherein the first type impurity is P type, and the second and third type impurities are N type. The method according to claim 7 or 17, Wherein the first type impurity is N type, and the second and third type impurities are P type.