CN107946298B - ESD protection circuit for preventing transient latch-up - Google Patents
ESD protection circuit for preventing transient latch-up Download PDFInfo
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- H01L27/0203—Particular design considerations for integrated circuits
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- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
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Abstract
The invention provides an ESD protection circuit for preventing transient latch-up, which comprises a p-type substrate, a p buried layer on the p-type substrate, a first region and a second region arranged on the p buried layer: the breakdown voltage of the first area is higher than that of the second area, and simultaneously is lower than the damage voltage of a subsequent circuit.
Description
Technical Field
The invention belongs to the field of electronic science and technology, is mainly used for electrostatic discharge (ESD) protection technology, and further relates to an anti-transient latch-up ESD protection circuit.
Background
ESD, i.e., electrostatic discharge, is an ancient natural phenomenon. ESD exists in every corner of people's daily life. Such conventional electrical phenomena are a fatal threat to sophisticated integrated circuits.
With the improvement of the integrated circuit manufacturing process, the minimum line width of the integrated circuit is reduced to the submicron or even nanometer level, so that the performance of the chip is improved, and the anti-ESD striking capability is also greatly reduced, and therefore, the electrostatic damage is more serious. The generation of ESD can cause non-fatal damage to the integrated circuit, thereby reducing the lifetime and reliability of the integrated circuit, and further causing the degradation of system functions, which greatly hinders (and is also an important factor for preventing the continued development of moore's law) the realization of large-scale highly reliable integration.
A thyristor (SCR) structure is one of the most ESD capable devices. The SCR can greatly reduce the area of the ESD module occupying the integrated circuit, reduce the cost and improve the robustness. However, the low trigger voltage thyristor (LVTSCR) structure has a strong snapback phenomenon, which causes a strong latch-up problem, as shown in fig. 1, such that the SCR cannot be safely adopted. The snapback phenomenon refers to: when the ESD device reaches the breakdown voltage Vt, avalanche breakdown occurs in the device, a large number of unbalanced carriers are generated in the device, and the unbalanced carriers have a conductance modulation effect on the device, so that the ESD device which is originally high in resistance (even insulated) becomes a low-resistance path. From the IV graph, as shown in fig. 1, after the voltage reaches Vt, the current rapidly increases while the voltage decreases. However, the voltage does not decrease to 0V, but reaches a certain minimum voltage Vh (i.e., a holding voltage), the ESD device completes conductance modulation, enters an on state, and the device changes from a blocking state to a low-resistance path to discharge charges.
If the ESD device holding voltage Vh is larger than the maximum voltage Vd of the ideal operating region, as shown in fig. 1, the IV curve of the ESD device does not intersect with the ideal operating region, i.e., the power supply voltage or the signal high level is not sufficient to provide a voltage that causes the ESD device to latch-up, then the ESD device will not latch-up. However, if the ESD device holding voltage Vh is smaller than the maximum voltage Vd of the ideal operating region, the intersection of the IV curve of the ESD device and the ideal operating region may cause a strong latch-up problem, so that the ESD device cannot be safely used. The latch-up problem refers to: the parasitic PNP tube and the parasitic NPN tube in the ESD device mutually provide base current to enter a closed loop amplification state, and the ESD device at the moment becomes a low resistance due to the conductance modulation effect and cannot be automatically turned off. Therefore, the high level of the power supply voltage or the signal in the normal circuit is directly short-circuited to the ground by the ESD device, so that the maximum voltage of the ideal working area is determined by the ESD device and is clamped at a lower voltage by the ESD device. Therefore, eliminating the latch-up effect is a difficult problem to solve before the SCR device is reliably applied.
The results of the study show that when the LVTSCR sustain voltage is higher than the supply voltage, its various transient-induced effects are eliminated. However, the power consumption is increased due to the increase of the voltage, so that the original strong ESD robustness of the SCR device is degraded to a certain extent. In order to compromise the contradiction between latch-up and ESD robustness, an ESD protection circuit for preventing transient latch-up is proposed, which can obtain adjustable holding voltage and ESD robustness, and realize functions through an ESD design window shown in fig. 1.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, it is an object of the present invention to provide an ESD protection circuit that is resistant to transient latch-up.
In order to achieve the purpose, the technical scheme of the invention is as follows:
an ESD protection circuit for preventing transient latch-up comprises a p-type substrate, a p-buried layer on the p-type substrate, a first region and a second region arranged on the p-buried layer:
the first region includes: the P buried layer is provided with a right nwell region, a right pwell region, a first right N + contact region and a first right P + region, wherein the right nwell region is arranged on the P buried layer, the right pwell region is tangent to the right edge of the right nwell region, the first right N + contact region is injected into the upper surface of the right nwell region, the first right P + region is tangent to the right edge of the right nwell region, and the surfaces of the first right N + contact region and the first right P + region are short-circuited by; a second right N + contact area injected into the upper surface of the right pwell area and a second right P + area tangent to the right edge of the right pwell area are connected with the adjustable resistor through metal and then are in short circuit with the cathode, and the second right P + area is in short circuit with the cathode through metal; injecting a right N + low trigger area formed on the surface of the junction of the right nwell area and the right pwell area;
the second region includes: the manufacturing method comprises the steps that a left nwell area on a P buried layer is arranged, a left pwell area tangent to the left edge of the left nwell area is arranged, a first left N + contact area injected into the upper surface of the left nwell area and a first left P + area tangent to the left edge of the left nwell area are formed, the surface of the first left N + contact area and the surface of the first left P + area are in short circuit through metal to form an anode of the device, a second left N + contact area injected into the upper surface of the left pwell area and a second left P + area tangent to the left edge of the left pwell area are in short circuit to a cathode through metal, the second left P + area is in short circuit with the cathode through metal, and a left N + low trigger area formed by injection into the surface of the junction of the left nwell area and the left pwell area;
the breakdown voltage of the second region is higher than that of the first region and lower than that of the subsequent circuit. That is, the breakdown voltage of the ESD protection device on the left formed by the second region is higher than the breakdown voltage of the ESD protection device on the right formed by the first region, and is lower than the breakdown voltage of the subsequent circuit.
Preferably, the adjustable resistor is a polysilicon resistor.
Preferably, a first p-sink region is arranged between the upper surface of the wafer and the p buried layer, and a second p-sink region is arranged between the first region and the second region.
Preferably, the first p-sink region is shorted to the cathode by a metal.
Preferably, the distance from the second left N + contact area to the left N + low trigger area of the second area is longer than the distance from the second right N + contact area to the right N + low trigger area of the first area. That is, the gate length of the left device is longer than that of the right device, so that the right ESD protection device is ensured to be broken down and started first.
Preferably, the first p-sink region and the second p-sink region are realized by a medium.
Preferably, the medium is SiO2。
Preferably, the ESD protection circuit for preventing transient latch-up further includes: the right gate oxide layer is positioned on the upper surface of the right pwell region, the left side of the right gate oxide layer is tangent to the right N + low trigger region, and the right side of the right gate oxide layer is tangent to the second right N + contact region; the right polysilicon gate is in short circuit with the cathode through metal; the left gate oxide layer is positioned on the upper surface of the left pwell region, the right side of the left gate oxide layer is tangent to the left N + low trigger region, and the left side of the left gate oxide layer is tangent to the second left N + contact region; the left polysilicon gate is shorted to the cathode by metal.
Preferably, the ESD protection circuit for preventing transient latch-up further includes: the gate oxide layer is positioned on the upper surface of the right nwell area, the right side of the gate oxide layer is tangent to the right N + low trigger area, and the left side of the gate oxide layer is tangent to the first right P + area; the grid is in short circuit with the anode through metal; the left gate oxide layer is positioned on the upper surface of the left nwell area, the left side of the left gate oxide layer is tangent to the left N + low trigger area, and the right side of the left gate oxide layer is tangent to the first left P + area; the left polysilicon gate is shorted to the anode by metal.
The invention has the beneficial effects that: because the ESD protection device provided by the invention adjusts the maintaining voltage of the whole circuit by adjusting the resistance value of the adjustable resistor, and obviously, the adjustment of the resistance value of a single resistor is much easier than the change of the process and the structural parameters of one ESD protection device, the invention greatly increases the flexibility of the design of the ESD protection circuit, realizes the function of discharging ESD signals with lower power consumption on the premise of preventing latch-up, and ensures that the voltage application range of the circuit is wider.
Drawings
FIG. 1 is an ESD design window diagram.
Fig. 2 is a circuit configuration diagram based on junction isolation according to embodiment 1 of the present invention.
Fig. 3 is a circuit configuration diagram based on dielectric isolation according to embodiment 2 of the present invention.
Fig. 4 is a circuit configuration diagram according to embodiment 3 of the present invention.
Fig. 5 is a circuit configuration diagram according to embodiment 4 of the present invention.
Fig. 6 is an equivalent circuit diagram of the circuit configuration diagram of the present invention.
Fig. 7 is an application circuit of the ESD protection circuit according to the present invention.
FIG. 8 is a comparison graph of simulation results of different adjustable resistor timing sequences of the circuit structure of the present invention.
The device comprises a substrate 01, a P-type substrate 07, a P buried layer, a right nwell region 02, a right pwell region 03, a right gate oxide layer 04, a first right N + contact region 11, a first right P + region 21, a device anode 31, a second right N + contact region 12, a second right P + region 22, an adjustable resistor 06, a cathode 08, a right N + low trigger region 13 and a right polysilicon gate 05, wherein the P buried layer 07 is a P-type substrate; and 00 is an insulating layer.
021 is left nwell district, 031 is left pwell district, 111 is first left N + contact region, 211 is first left P + district, 121 is second left N + contact region, 221 is second left P + district, 131 is left N + low trigger zone, 041 is left gate oxide, 051 is left polycrystalline silicon grid, 71 is first P-sink district, 72 is second P-sink district.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1
As shown in fig. 2, an ESD protection circuit for preventing transient latch-up includes a p-type substrate 01, a p-buried layer 07 on the p-type substrate, a first region and a second region disposed on the p-buried layer 07:
the first region includes: the P buried layer 07 is provided with a right nwell region 02, a right pwell region 03, a first right N + contact region 11 and a first right P + region 21, wherein the right nwell region 02 is arranged on the P buried layer 07, the right pwell region 03 is tangent to the right edge of the right nwell region 02, the first right N + contact region 11 is injected into the upper surface of the right nwell region 02, the right edge of the right nwell region 21 is tangent to the right edge of the right nwell region, and the surfaces of the first right N + contact region 11 and the first right P +; a second right N + contact area 12 injected into the upper surface of the right pwell area 03 and a second right P + area 22 tangent to the right edge of the right pwell area, wherein the second right N + contact area 12 is connected with the adjustable resistor 06 through metal and then is in short circuit with the cathode 08, and the second right P + area 22 is in short circuit with the cathode 08 through metal; a right N + low trigger region 13 is formed by surface injection at the junction of the right nwell region 02 and the right pwell region 03;
the second region includes: a left nwell region 021 on the P buried layer 07, a left pwell region 031 tangent to the left edge of the left nwell region 021, a first left N + contact region 111 injected on the upper surface of the left nwell region 021 and a first left P + region 211 tangent to the left edge of the left nwell region 021 are arranged, the surfaces of the first left N + contact region 111 and the first left P + region 211 are shorted by metal to form a device anode 31, a second left N + contact region 121 injected on the upper surface of the left pwell region 031 and a second left P + region 221 tangent to the left edge of the left pwell region 031 are injected, the second left N + contact region 121 is shorted to a cathode 08 by metal, the second left P + region 221 is shorted to the cathode 08 by metal, and a left N + low trigger region 131 formed by injection on the surface at the junction of the left nwell region 021 and the left pwell region 031;
the breakdown voltage of the second region is higher than that of the first region and lower than that of the subsequent circuit.
A first p-sink region 71 is arranged between the upper surface of the wafer and the p buried layer 07, and a second p-sink region 72 is arranged between the first region and the second region. The first p-sink region 71 is shorted to the cathode 08 by metal. Therefore, isolation among different ESD protection circuits and isolation among the ESD protection circuits and other internal circuits can be realized. In a specific implementation manner, the isolation manner between different ESD protection devices and between an ESD protection device and other internal circuits may be PN junction isolation, or may also be dielectric isolation.
Specifically, the adjustable resistor 06 is a polysilicon resistor.
The second left N + contact area 121 of the second region is located at a longer distance from the left N + low trigger area 131 than the second right N + contact area 12 of the first region is located at the right N + low trigger area 13. Namely, the gate length of the left device of the ESD formed in the second region is longer than that of the right device formed in the first region, so that the right ESD protection device is ensured to be broken down and started first.
The trigger voltage of the ESD protection device on the left formed by the second area is higher than that of the ESD protection device on the right formed by the first area, and is lower than the damage voltage of a subsequent circuit, so that the ESD signal is prevented from damaging the subsequent innecrocuit. Meanwhile, before the breakdown of the left ESD protection device, the right ESD protection device has already been broken down, the current of the circuit is very large, the large current is generated by an ESD signal, and the high current cannot be maintained only by a power supply, so the left ESD protection device cannot be latched after the ESD signal is ended.
The working principle is as follows:
when the ESD voltage rises to the breakdown voltage of the right pwell 03/right N + low trigger region 13 junction, electrons in the breakdown current are pulled into the electrode by the anode through the right nwell 02 and the first right N + contact region 11; holes are pulled into the electrode by the cathode through the right pwell region 03, the second P + contact region 22. As the current increases, when the voltage drop generated by the current on the right nwell 02 and the right pwell 03 is enough to turn on the parasitic pnp, npn transistor, the PNPN structure formed by the first right P + region 21, the right nwell 02, the right pwell 03, and the second right N + contact region 12 turns on, i.e., the SCR in the ESD protection device on the right turns on. The current path is 31->21—>02—>03—>12, the device generates snapback phenomenon. Due to the adjustable resistor 06, the current flowing through the adjustable resistor 06 generates a voltage drop, thus raising the voltage drop of the second right N + contact region 12. If the lowest voltage drop achieved by the first right N + contact region 11 to the second right N + contact region 12 is Vh (i.e. the holding voltage of the right ESD protection device) when snapback occurs in the device, and the current flowing through the adjustable resistor Ra is I, the voltage drop between the anode and the cathode is IRa + Vh. Suppose the breakdown voltage of the ESD protection device on the left is Vt2When IRa + Vh1＝Vt2In time, the ESD protection device on the left breaks down, and snapback phenomenon occurs again in the circuit. Because the SCR device has extremely strong ESD discharge capacity, when the ESD protection device on the left breaks down, the ESD signal can be discharged with lower power consumption. And because the current for triggering the breakdown of the left ESD protection device is very high, the high current cannot be maintained only by the power supply, so the left ESD protection device does not latch up after the ESD signal is ended. Therefore, the circuit realizes the function of discharging the ESD signal with lower power consumption on the premise of preventing latch-up.
In order to prevent the ESD device or circuit from latching up when discharging the ESD signal, a common processing method in the industry at present is to increase the holding voltage of the device or circuit so that the holding voltage is greater than the power supply operating voltage Vdd. While a common approach to changing the holding voltage is to change the process or structural parameters of the ESD device. This is clearly a complication of the current practice compared to the circuit arrangement of the invention. The ESD protection circuit of the present invention can adjust the holding voltage of the whole circuit by adjusting the resistance of the adjustable resistor 06. It is obvious that it is much easier to adjust the resistance of a single resistor than to change the process and structure parameters of an ESD protection device. This has the advantage of greatly increasing the design flexibility and making the voltage application range of the circuit wider.
Fig. 6 is an equivalent circuit diagram of the circuit configuration diagram of the present invention. Wherein R isnwIs the N-well resistance of the first region device, i.e. the equivalent resistance of the right nwell region 02; rpwIs the P-well resistance of the first region device, i.e. the equivalent resistance of the right pwell region 03; ra is an adjustable resistor. In the equivalent circuit of fig. 6, the left branch is the equivalent circuit of the first device, and the right branch is the equivalent circuit of the second device, both of which share the anode. When an ESD signal appears at the anode, the left branch in the equivalent circuit is turned on first because the breakdown voltage of the devices in the first region is lower than that in the second region. But due to the adjustable resistance Ra of the first region, the anode voltage will be increased above the breakdown voltage of the first region devices as the first region current increases. When the anode voltage reaches the breakdown voltage of the second-region device, the right branch in the equivalent circuit is opened along with the anode voltage.
Taking the application circuit shown in fig. 7 as an example, it is assumed that the ESD protection circuit for preventing transient latch-up proposed by the patent technology is applied to an inner circuit with a power supply voltage VDD of 5V, and the sustain voltage corresponding to the resistance value of the adjustable resistor 06 just meets the condition that latch-up does not occur, i.e. the sustain voltage of the ESD protection circuit for preventing transient latch-up is slightly larger than 5V. If the subsequent inner circuit of the ESD protection circuit for preventing transient latch-up changes, assuming that the maximum voltage provided by the power voltage VDD becomes 15V, in order to prevent the ESD protection circuit from latch-up, it is only necessary to adjust the resistance of the adjustable resistor 06 to be larger than 15V according to the actual application situation, and it is not necessary to change the process and structure parameters of the ESD protection device.
FIG. 8 is a comparison graph of simulation results of different adjustable resistor timing sequences of the circuit structure of the present invention, wherein the breakdown voltage of the ESD protection device on the left side in the simulation circuit structure is about 30V, and the breakdown voltage of the ESD protection device on the right side is about 30VThe pressure is about 23V. As can be seen from fig. 8, the circuit structure is 1.02 × 10 when t is equal to t-7s is the first snapback, t is 1.1 × 10-7s is the second snapback. With the increase of the resistance value of the adjustable resistor 06, the breakdown voltage and the holding voltage of snapback generated for the first time of the circuit structure also increase. Since the snapback occurs for the second time because the SCR on the left side breaks down, the change of the resistance of the adjustable resistor 06 does not affect the breakdown voltage and the holding voltage of the snapback occurring for the second time in the circuit structure.
Example 2
As shown in fig. 3, the present embodiment is different from embodiment 2 in that: the first p-sink region 71 and the second p-sink region 72 are realized by a medium, and the medium is SiO2. When the p-buried layer 07 and the first and second p- sink regions 71 and 72 are implemented using the same dielectric, they may be regarded as constituting an insulating layer 00 (as shown in fig. 3). In an implementation of this embodiment, the p-type substrate 01 may be a silicon substrate. In other implementations, the first p-sink region 71 and the second p-sink region 72 may also be implemented using other media.
Example 3
As shown in fig. 4, the present embodiment is different from embodiment 1 in that: the right gate oxide layer 04 is positioned on the upper surface of the right pwell area 03, the left side of the right pwell area is tangent to the right N + low trigger area 13, the right side of the right gate oxide layer 04 is tangent to the second right N + contact area 12, and the right polycrystalline silicon gate 05 is positioned on the upper surface of the right gate oxide layer 04; the right polysilicon gate 05 is shorted with the cathode 08 through metal;
a left gate oxide layer 041 which is positioned on the upper surface of the left pwell region 031, the right side of which is tangent to the left N + low trigger region 131, and the left side of which is tangent to the second left N + contact region 121, and a left polysilicon gate 051 which is positioned on the upper surface of the left gate oxide layer 041; the left polysilicon gate 051 is shorted to the cathode 08 by metal.
Example 4
As shown in fig. 5, the present embodiment is different from embodiment 1 in that: the gate oxide 04 is tangent to the right N + low trigger region 13 on the right side and the first right P + region 21 on the left side, and the polysilicon gate 05 is arranged on the upper surface of the gate oxide 04; the gate 05 is shorted to the anode 31 by metal;
a left gate oxide layer 041 which is positioned on the upper surface of the left nwell region 021, the left side of which is tangent to the left N + low trigger region 131 and the right side of which is tangent to the first left P + region 211, and a left polysilicon gate 051 on the upper surface of the left gate oxide layer 041; the left polysilicon gate 051 is shorted to the anode 31 by metal.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
1. An ESD protection circuit for preventing transient latch-up, characterized by comprising a p-type substrate (01), a p-buried layer (07) on the p-type substrate, a first region and a second region provided on the p-buried layer (07):
the first region includes: the device comprises a right N well region (02) arranged on a P buried layer (07), a right P well region (03) tangent to the right edge of the right N well region (02), a first right N + contact region (11) injected into the upper surface of the right N well region (02) and a first right P + region (21) tangent to the right edge of the right N well region, wherein the surfaces of the first right N + contact region (11) and the first right P + region (21) are short-circuited by metal to form a device anode (31); a second right N + contact region (12) injected on the upper surface of the right P well region (03) and a second right P + region (22) tangent to the right edge of the right P well region, wherein the second right N + contact region (12) is connected with the adjustable resistor (06) through metal and then is in short circuit with the cathode (08), and the second right P + region (22) is in short circuit with the cathode (08) through metal; a right N + low trigger region (13) is formed at the interface of the right N well region (02) and the right p well region (03) through surface injection;
the second region includes: a left N well region (021) on a P buried layer (07) is arranged, a left P well region (031) tangent to the left edge of the left N well region (021) is arranged, a first left N + contact region (111) injected on the upper surface of the left N well region (021) and a first left P + region (211) tangent to the left edge of the left N well region are shorted by metal, a device anode (31) is formed, a second left N + well region (121) injected on the upper surface of the left P well region (031) and a second left P + region (221) tangent to the left edge of the left P well region (031) are shorted by metal, and a left N + low trigger region (131) formed by surface injection at the junction of the left N well region (021) and the left P well region (031) is shorted by metal;
the breakdown voltage of the second region is higher than that of the first region and lower than that of the subsequent circuit.
2. The ESD protection circuit against transient latch-up of claim 1, wherein: the adjustable resistor (06) is a polysilicon resistor.
3. The ESD protection circuit against transient latch-up of claim 1, wherein: a first p-deep implantation region (71) is arranged between the upper surface of the wafer and the p buried layer (07), and a second p-deep implantation region (72) is arranged between the first region and the second region.
4. The ESD protection circuit against transient latch-up of claim 3, wherein: the first p-deep implant region (71) is shorted to the cathode (08) by metal.
5. The ESD protection circuit against transient latch-up of claim 1, wherein: the distance from the second left N + contact area (121) of the second area to the left N + low trigger area (131) is longer than the distance from the second right N + contact area (12) of the first area to the right N + low trigger area (13).
6. The ESD protection circuit against transient latch-up of claim 3, wherein the first p-deep implanted region (71) and the second p-deep implanted region (72) are implemented by a dielectric.
7. The ESD protection circuit against transient latch-up of claim 6, wherein: the medium is SiO2。
8. The ESD protection circuit against transient latch-up of claim 3 or 4, further comprising:
the right gate oxide layer (04) is positioned on the upper surface of the right p well region (03), the left side of the right p well region is tangent to the right N + low trigger region (13), the right side of the right gate oxide layer is tangent to the second right N + contact region (12), and a right polysilicon gate (05) is positioned on the upper surface of the right gate oxide layer (04); the right polysilicon gate (05) is in short circuit with the cathode (08) through metal;
the left gate oxide layer (041) is positioned on the upper surface of the left p well region (031), the right side of the left p well region is tangent to the left N + low trigger region (131), and the left side of the left gate oxide layer is tangent to the second left N + contact region (121), and a left polysilicon gate (051) is positioned on the upper surface of the left gate oxide layer (041); the left polysilicon gate (051) is short-circuited with the cathode (08) through metal.
9. The ESD protection circuit against transient latch-up of claim 4, further comprising:
the gate oxide layer (04) is positioned on the upper surface of the right N well region (02), the right side of the gate oxide layer is tangent to the right N + low trigger region (13), and the left side of the gate oxide layer is tangent to the first right P + region (21), and the polysilicon gate (05) is positioned on the upper surface of the gate oxide layer (04); the grid (05) is short-circuited with the anode (31) through metal;
the left gate oxide layer (041) is positioned on the upper surface of the left N well region (021), the left side of the left gate oxide layer is tangent to the left N + low trigger region (131), and the right side of the left gate oxide layer is tangent to the first left P + region (211), and a left polysilicon gate (051) is positioned on the upper surface of the left gate oxide layer (041); the left polysilicon gate (051) is short-circuited with the anode (31) through metal.
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|---|---|---|---|---|
| CN102969312A (en) * | 2012-12-18 | 2013-03-13 | 江南大学 | High-voltage ESD (electro-static discharge) protective device triggered by bidirectional substrate |
| CN104392983A (en) * | 2014-11-06 | 2015-03-04 | 北京大学 | Adjustable maintaining voltage type electronic static discharge protecting circuit |
| CN105428354A (en) * | 2015-12-17 | 2016-03-23 | 江南大学 | Electronic static discharge (ESD) protection device with bidirectional silicon controlled rectifier (SCR) structure embedded with interdigital N-channel metal oxide semiconductor (NMOS) |
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| US7566914B2 (en) * | 2005-07-07 | 2009-07-28 | Intersil Americas Inc. | Devices with adjustable dual-polarity trigger- and holding-voltage/current for high level of electrostatic discharge protection in sub-micron mixed signal CMOS/BiCMOS integrated circuits |
| US8592860B2 (en) * | 2011-02-11 | 2013-11-26 | Analog Devices, Inc. | Apparatus and method for protection of electronic circuits operating under high stress conditions |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102969312A (en) * | 2012-12-18 | 2013-03-13 | 江南大学 | High-voltage ESD (electro-static discharge) protective device triggered by bidirectional substrate |
| CN104392983A (en) * | 2014-11-06 | 2015-03-04 | 北京大学 | Adjustable maintaining voltage type electronic static discharge protecting circuit |
| CN105428354A (en) * | 2015-12-17 | 2016-03-23 | 江南大学 | Electronic static discharge (ESD) protection device with bidirectional silicon controlled rectifier (SCR) structure embedded with interdigital N-channel metal oxide semiconductor (NMOS) |
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