CN107946372B

CN107946372B - Silicon controlled rectifier for ESD protection

Info

Publication number: CN107946372B
Application number: CN201711219518.4A
Authority: CN
Inventors: 乔明; 齐钊; 肖家木; 王正康; 毛焜; 张波
Original assignee: University of Electronic Science and Technology of China; Shanghai Bright Power Semiconductor Co Ltd
Current assignee: University of Electronic Science and Technology of China; Shanghai Bright Power Semiconductor Co Ltd
Priority date: 2017-11-28
Filing date: 2017-11-28
Publication date: 2020-06-30
Anticipated expiration: 2037-11-28
Also published as: CN107946372A

Abstract

The invention provides a silicon controlled rectifier for ESD protection, comprising: the device comprises a P-type substrate, an nwell area, a low trigger area crossing the junction of the nwell area and the pwell area, at least one N + P + area unit arranged on the surface of the nwell area, and at least one P + N + area unit arranged on the surface of the pwell area, wherein the N + area in any one N + P + area unit is tangent to the P + area, and two adjacent N + P + area units are tangent to each other; one side of the low trigger zone is tangent to the right side of the rightmost P + zone in the at least one N + P + zone unit, or tangent to the left side of the leftmost N + zone in the at least one P + N + zone unit, and the low trigger zone is not tangent to the N + P + zone unit and the P + N + zone unit at the same time.

Description

Silicon controlled rectifier for ESD protection

Technical Field

The invention belongs to the field of electronic science and technology, and is mainly used for electrostatic discharge (ESD) protection technology. Further disclosed is a method for optimizing cathode injection of SCR structure, and improving holding voltage by increasing parasitic leakage path and related device structure.

Background

ESD, i.e., electrostatic discharge, is an ancient natural phenomenon. ESD exists in every corner of people's daily life. Such conventional electrical phenomena are a fatal threat to sophisticated integrated circuits.

With the improvement of the integrated circuit manufacturing process, the minimum line width of the integrated circuit is reduced to the submicron or even nanometer level, so that the performance of the chip is improved, the anti-ESD striking capability is greatly reduced, the environment for using the device is not changed, and the damage of static electricity to the IC is more serious. The generation of ESD can cause non-fatal damage to the integrated circuit, thereby reducing the lifetime and reliability of the integrated circuit, and further causing the degradation of system functions, which greatly hinders the realization of large-scale high-reliability integration.

A thyristor (SCR) structure is one of the most ESD capable devices. The SCR can greatly reduce the area of the ESD module occupying the integrated circuit, reduce the cost and improve the robustness. However, the low trigger voltage thyristor (LVTSCR) structure has a strong snapback phenomenon, which causes a strong latch-up problem, as shown in fig. 1, such that the SCR cannot be safely adopted. The snapback phenomenon refers to: when the ESD device reaches the breakdown voltage Vt1, avalanche breakdown occurs in the device, and a large number of unbalanced carriers are generated in the device, and these unbalanced carriers generate a conductance modulation effect on the device, so that the ESD device which is originally high-resistance (even insulation) becomes a low-resistance path. From the IV graph, as shown in fig. 1, after the voltage reaches Vt1, the current rapidly increases while the voltage decreases. However, the voltage does not decrease to 0V, but reaches a certain minimum voltage Vh (i.e., a holding voltage), the ESD device completes conductance modulation, enters an on state, and the device changes from a blocking state to a low-resistance path to discharge charges.

If the ESD device holding voltage Vh is larger than the maximum voltage Vd of the ideal operating region, as shown in fig. 1, the IV curve of the ESD device does not intersect with the ideal operating region, i.e., the power supply voltage or the signal high level is not sufficient to provide a voltage that causes the ESD device to latch-up, then the ESD device will not latch-up. However, if the ESD device holding voltage Vh is smaller than the maximum voltage Vd of the ideal operating region, the intersection of the IV curve of the ESD device and the ideal operating region may cause a strong latch-up problem, so that the ESD device cannot be safely used. The latch-up problem refers to: the parasitic PNP tube and the parasitic NPN tube in the ESD device mutually provide base current to enter a closed loop amplification state, and the ESD device at the moment becomes a low resistance due to the conductance modulation effect and cannot be automatically turned off. Therefore, the high level of the power supply voltage or the signal in the normal circuit is directly short-circuited to the ground by the ESD device, so that the maximum voltage of the ideal working area is determined by the ESD device and is clamped at a lower voltage by the ESD device. Therefore, eliminating the latch-up effect is a difficult problem to solve before the SCR device is reliably applied.

Research results show that when the LVTSCR has a holding voltage higher than the power supply voltage, various transient-induced effects are eliminated, but the advantage of strong SCR ESD robustness is diminished due to the increased power consumption caused by the increased voltage. Therefore, in order to compromise the contradiction between latch-up and ESD robustness, a dual-channel cathode optimized SCR device is provided, which can obtain adjustable maintaining voltage and ESD robustness, and adjust the size of Vh and the size of cathode area through the number of cathode blocks, thereby coordinating the latch-up resistance and current resistance of the device. The function is achieved through the ESD design window shown in fig. 1.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, it is an object of the present invention to provide a silicon controlled rectifier for ESD protection.

In order to achieve the purpose, the technical scheme of the invention is as follows:

a silicon controlled rectifier for ESD protection, the silicon controlled rectifier comprising a P-type substrate, an N-well region disposed on the P-type substrate and a P-well region tangent to a right edge of the N-well region, a low trigger region crossing a junction of the N-well region and the P-well region, at least one N + P + region unit disposed on a surface of the N-well region, and at least one P + N + region unit disposed on a surface of the P-well region, an anode disposed on the at least one N + P + region unit and a cathode disposed on the at least one P + N + region unit;

the left side of the leftmost N + region in at least one N + P + region unit is tangent to the left edge of the N well region, the N + region in any one N + P + region unit is tangent to the P + region, and two adjacent N + P + region units are tangent;

the right side of the rightmost P + region in at least one P + N + region unit is tangent to the right side edge of the P well region, a P + region in any one P + N + region unit is tangent to the N + region, and two adjacent P + N + region units are tangent;

one side of low trigger zone is tangent to the right side of the rightmost P + zone in at least one N + P + zone unit, or one side of low trigger zone is tangent to the left side of the leftmost N + zone in at least one P + N + zone unit, just the low trigger zone is not tangent to simultaneously at least one N + P + zone unit with at least one P + N + zone unit.

Preferably, the low trigger area is one of a low trigger P + area and a low trigger N + area; when the low trigger area is a low trigger P + area, one side of the low trigger area is tangent to the left side of the leftmost N + area in the at least one P + N + area unit; when the low trigger area is a low trigger N + area, one side of the low trigger area is tangent to the right side of the rightmost P + area in the at least one N + P + area unit.

Preferably, the anode is formed by connecting the surface of the leftmost N + region in the at least one N + P + region unit and the surface of each P + region in the at least one N + P + region unit; and connecting the surface of the rightmost P + region in the at least one P + N + region unit with the surface of each N + region in the at least one P + N + region unit to form the cathode.

Preferably, the width of the low trigger area is greater than the width of each P + region and each N + region in the at least one unit of N + P + regions, and the width of the low trigger area is greater than the width of each N + region and each P + region in the at least one unit of P + N + regions.

The invention has the beneficial effects that: the silicon controlled rectifier provided by the invention has obvious advantages for realizing the maximization of current capability and resisting the Latch-up effect.

Drawings

FIG. 1 is an ESD design window.

Fig. 2 is a structural diagram of a device of embodiment 1 of the present invention.

Fig. 3 is a structural view of a device of embodiment 2 of the present invention.

Fig. 4 is a structural view of a device of embodiment 3 of the present invention.

Fig. 5 is a structural view of a device of embodiment 4 of the present invention.

Fig. 6 is a structural view of a device of embodiment 5 of the present invention.

Fig. 7 is an applied circuit diagram of the device structure proposed by the present invention.

FIG. 8 is a comparison graph of simulation results for different numbers of N + P + repeat units of the device structure of the present invention.

FIG. 9 is a comparison graph of time domain simulation results for different numbers of N + P + repeating units of the device structure of the present invention.

Wherein 01 is a p-type substrate; 02 is an n-well region; 03 is a P-well region, 11 is a first N + contact region, 12 is a second N + contact region, 14 is a low-trigger N + region, 21 is a first P + region, 22 is a second P + region, 24 is a low-trigger P + region, 31 is a device anode, and 32 is a device cathode.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Example 1

As shown in fig. 2, a silicon controlled rectifier for ESD protection includes: the P-type substrate 01, an N-well region 02 injected on the P-type substrate, a P-well region 03 tangent to the right edge of the N-well region 02, a first N + contact region 11 injected on the surface of the N-well region 02, and a first P + region 21 tangent to the right edge of the first N + contact region 11; the first N + contact region 11 and the first P + region 21 form an N + P + region unit, and the surfaces of the first N + contact region 11 and the first P + region 21 are shorted by metal to form a device anode 31; the P-well area structure further comprises a second P + area 22 which is injected on the surface of the P-well area 03 and is tangent to the right edge of the P-well area, a second N + contact area 12 which is tangent to the left edge of the second P + area 22, and a P + N + area unit which is formed by the adjacent second P + area 22 and the second N + contact area 12, wherein the second N + contact area 12 and the second P + area 22 are connected to form a device cathode 32, the low-trigger P + area 24 crosses the junction of the N-well area 02 and the P-well area 03, the left edge of the low-trigger P + area 24 is not tangent to the first P + area 21, and the right edge of the low-trigger P + area 24 is tangent to the second N + contact.

The width of the low-trigger P + region 24 is greater than the width of each P + region and each N + region in the N + P + region unit, and the width of the low-trigger P + region 24 is greater than the width of each N + region and each P + region in the P + N + region unit.

The process flow for realizing the device is briefly described as follows:

step 1: n-type impurity injection is carried out on the left side of the upper surface of a P-type substrate 01, P-type impurity injection is carried out on the right side, and then an N-well region 02 and a P-well region 03 tangent to the right edge of the N-well region are formed by junction pushing;

step 2: performing N + impurity implantation on the upper surface to form a first N + contact region 11 and a second N + contact region 12;

and step 3: p + impurity injection is carried out on the upper surface to form a first P + area 21, a second P + area 22 and a low trigger P + area 24;

and 4, step 4: the second N + contact region 12 and the second P + region 22 are shorted together by metal to form a device cathode, and the first N + contact region 11 and the first P + region 21 are shorted together by metal to form a device anode

It is emphasized that step 2 and step 3 can be interchanged, i.e. the P + impurity implantation is performed on the upper surface before the N + impurity implantation. In addition, although the first N + contact region 11 and the second N + contact region 12 have the same concentration, the functions are different from each other. The same is true of the first P + region 21, the second P + region 22, and the low-trigger P + region 24.

The working principle is as follows:

when the ESD voltage rises to the N-well region 02/low trigger P + region 24 junction breakdown voltage, electrons are pulled into the electrode by the anode through the first N + contact region 11, holes are pulled into the electrode by the cathode through the second P + region 22, forming a body diode breakdown current. As the current increases, the SCR turns on when the current creates a voltage drop across the n-well region 02 and the p-well region 03 sufficient to turn on the parasitic pnp, npn transistor. However, since the first and second N +

contact regions

11 and 12 are designed to have lateral widths close to their depths, lateral emission efficiency is high, and the surface pnp + dio path is also open in addition to the bulk SCR. The device is now operating with SCR bleeding in common with pnp + dio. The sustain voltage eventually falls to a voltage between the pnp sustain voltage and the SCR sustain voltage. Thus, the sustain voltage can be adjusted by changing the aspect ratio K of the npn emitter. As K increases, the PNP path current capability dominates and the device holding voltage will rise. When K is lowered, the NPN emission efficiency in the SCR path increases causing the SCR device current capability to dominate and the device holding voltage to drop. I.e., the more repeating units, the lower the sustain voltage. Because the current concentration is caused by the excessively narrow cathode, the ESD robustness of the device is reduced, and therefore the compromise between the area of the cathode and the K value can be adjusted by increasing the number of the repeating units of the N +/P + region. Therefore, the development of the modified structure shown in fig. 5 is also the idea of the present invention. The structure improves the holding voltage of the SCR device under the condition of not changing any process flow and step. In practical application, the device is easy to manufacture and convenient to integrate and adjust. Is a good way to solve the SCR latch-up problem.

As shown in FIG. 7, taking the power driving IC as an example, the anode of the expanded structure of the present invention is connected to the chip VDD, and the cathode is connected to GND. The ESD protection circuit is used for power clamp ESD protection of a chip. Because the VDD that the low-voltage LV power supply can provide is constant, if the device maintains the voltage to be higher than the VDD, the latch-up effect can be immune. As shown, the device can be used for IO port ps mode protection: when an ESD signal comes, the device is triggered and discharges the ESD signal; when the ESD signal current is smaller than the device maintaining current, the device can still be turned off immediately after noise interference, and the signal voltage is raised to avoid causing logic errors or level attenuation. Thus, the device can provide a safer ESD discharge path in the application of an I/O port or a power supply. In the right middle voltage power clamp application, unlike the left LV protection, the middle voltage circuit VDD is higher than the low voltage, and the corresponding sustain voltage is also higher, so the N +/P + repeating unit of the device applied to the middle voltage circuit is replaced with only one repeating unit. According to the principle, the device can maintain a high maintaining voltage, so that the latch-up phenomenon of a medium-voltage end is avoided.

In addition, the device has a limit on the number of N + P + repeat cells when used for protection at a fixed voltage, but when the number of repeat cells is greater than 4 for a 5V supply clamp, the device sustain voltage will drop below the supply voltage, thereby losing latch-up resistance. The higher the supply voltage, the smaller the range the novel device can adjust. The working principle is basically the same as that of embodiment 1.

Fig. 8 shows the I-V characteristics of the new SCR structure versus the conventional LVTSCR structure at ESD voltage. As is apparent from the graph, the sustain voltage gradually decreases as the number of N +/P + repeating units increases. When only one N +/P + unit is repeated, the maintaining voltage value can reach more than 15V.

The time domain response results for each device at a TLP square wave with a rising edge of 10ns are shown in fig. 9. It can be seen that the clamping voltage for each device during operation is above 5V. And as the number of N +/P + is reduced, the device gradually eliminates the strong snapback effect. The device can maintain a high sustain voltage when in a single repeating cell and is therefore suitable for right side medium voltage side ESD protection as shown in fig. 7.

In summary, the present invention provides a latch-up immune SCR device for ESD, which can increase the holding voltage. The invention realizes the controllability, and is particularly suitable for the ESD protection of 5V low-voltage to 15V medium-voltage chip level. The core idea of the device is to increase the sustain voltage by increasing the ratio of the horizontal emission capability of the cathode N + region of the SCR device in the total emission efficiency.

Example 2

As shown in fig. 3, the present embodiment is different from embodiment 1 in that: more than one of the P + N + region cells is included within P-well region 03. An N + region in any one P + N + region unit is tangent to a P + region, and two adjacent P + N + region units are tangent; the second N + contact region 12 of all the N + P + region units and the rightmost second P + region 22 are connected to form the device cathode 32, and the vertical emission capability of the npn tube can be changed by adding the N +/P + repeat unit.

Example 3

As shown in fig. 4, the silicon controlled rectifier for ESD protection in this embodiment includes a P-type substrate 01, an N-well region 02 formed by implantation on the P-type substrate, a P-well region 03 tangent to the right edge of the N-well region 02, a second P + region 22 implanted on the surface of the P-well region 03 and tangent to the right edge thereof, a second N + contact region 12 tangent to the left edge of the second P + region 22, the second P + region 22 and the second N + contact region 12 adjacent to each other form a P + N + region unit, and the second N + contact region 12 and the second P + region 22 are connected to form a device cathode 32;

a first N + contact area 11 which is tangential to the left edge of the N-well area 02 and is injected on the surface of the N-well area 02, and a first P + area 21 which is tangential to the right edge of the first N + contact area 11, wherein the adjacent first N + contact area 11 and the first P + area 21 form an N + P + area unit, and the N-well area 02 internally comprises a plurality of N + P + area units; the low-trigger N + region 14 crosses the boundary between the N-well region 02 and the P-well region 03, and has a left edge tangent to the right side of the rightmost first P + region 21 and a right edge not tangent to the second N + contact region 12 of the low-trigger N + region 14. The first P + regions 21 of all the N + P + region units and the leftmost first N + contact region 11 are connected to constitute a device anode 31.

Example 4

As shown in fig. 5, the silicon controlled rectifier for ESD protection of the present embodiment differs from embodiment 3 in that: a plurality of the P + N + region cells are included inside the P-well region 03. An N + region in any one P + N + region unit is tangent to a P + region, and two adjacent P + N + region units are tangent; the second N + contact regions 12 of all the N + P + region units are connected to the rightmost second P + region 22 to form a device cathode 32.

Example 5

As shown in fig. 6, this embodiment is substantially the same as embodiment 2, with the difference that: the N-well region 02 includes therein a plurality of N + P + region units constituted by the first N + contact region 11 and the first P + region 21; the first P + regions 21 of all the N + P + region units and the leftmost first N + contact region 11 are connected to constitute a device anode 31.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A silicon controlled rectifier for ESD protection, characterized by:

the silicon controlled rectifier comprises a P-type substrate, an N-well region arranged on the P-type substrate, a P-well region tangent to the right edge of the N-well region, a low trigger region crossing the junction of the N-well region and the P-well region, at least one N + P + region unit arranged on the surface of the N-well region, at least one P + N + region unit arranged on the surface of the P-well region, an anode arranged on the at least one N + P + region unit and a cathode arranged on the at least one P + N + region unit;

2. The silicon controlled rectifier for ESD protection of claim 1, wherein: the low trigger area is one of a low trigger P + area and a low trigger N + area;

when the low trigger area is a low trigger P + area, one side of the low trigger area is tangent to the left side of the leftmost N + area in the at least one P + N + area unit;

when the low trigger area is a low trigger N + area, one side of the low trigger area is tangent to the right side of the rightmost P + area in the at least one N + P + area unit.

3. The silicon controlled rectifier for ESD protection of claim 1, wherein: connecting a surface of a leftmost N + region of the at least one N + P + region unit with a surface of each P + region of the at least one N + P + region unit to form the anode;

and connecting the surface of the rightmost P + region in the at least one P + N + region unit with the surface of each N + region in the at least one P + N + region unit to form the cathode.

4. The silicon controlled rectifier for ESD protection of claim 1, wherein: the width of the low trigger area is greater than the width of each P + area and each N + area in the at least one N + P + area unit, and the width of the low trigger area is greater than the width of each N + area and each P + area in the at least one P + N + area unit.