KR20100076779A - Delay locked loop circuit - Google Patents

Abstract

PURPOSE: A delay locked loop circuit is provided to always generate minimum timing pulse by disabling the generation of a plurality of timing pulse. CONSTITUTION: A clock phase comparison unit(300) compares the phase of a source clock and a feedback clock. The clock phase comparison unit generates a phase comparison signal. Clock delay unit(340,350) determine the amount of delay corresponding to the phase comparison signal at a first timing. The amount of the delay determined by a second timing is reflected in a source clock through the clock delay unit. The clock delay unit outputs a delay locked clock. A delay model unit(360) adds real delay conditions in a source clock route at a delay locked clock. The delay model unit outputs a feedback clock. A timing pulse generating unit(320) generates a plurality of timing pulses.

Description

DELAY LOCKED LOOP CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly, to a delay locked loop circuit of a semiconductor device.

Synchronous semiconductor memory devices such as DDR SDRAM (Double Data Rate Synchronous DRAM) transfer data with external devices using an internal clock synchronized with an external clock input from an external device such as a memory controller (CTRL).

This is because, in order to stably transfer data between the memory and the memory controller, the time synchronization between the external clock and the data output from the memory is very important.

At this time, the data output from the memory is output in synchronization with the internal clock. When the internal clock is initially applied to the memory, the internal clock is applied in synchronization with the external clock, but is delayed through each component in the memory and output to the outside of the memory. If it does, it is output out of sync with external clock.

Therefore, for stable transmission of data output from the memory, the delayed internal clock is accurately positioned at the edge or center of the external clock applied by the memory controller while passing through each component in the memory transmitting the data. To do this, the time the data is on the bus must be compensated back to the internal clock so that the internal and external clocks are synchronized.

Clock synchronizing circuits that perform this role include a phase locked loop (PLL) circuit and a delay locked loop (DLL) circuit.

Of these, when the frequency of the external clock and the internal clock are different, the frequency-locking function should be used. Therefore, a phase locked loop (PLL) is used. However, when the frequency of the external clock is the same as the frequency of the internal clock, a delayed fixed loop (DLL) circuit that can be implemented in a relatively small area is mainly used compared to the phase locked loop (PLL).

That is, in the case of the semiconductor memory device, since the frequency used is the same, a delay locked loop (DLL) circuit is mainly used as the clock synchronization circuit.

In particular, the semiconductor memory device includes a register for storing a fixed delay value, and when the power is turned off, the fixed delay value is stored in the register, and when the power is applied again, the internal clock is fixed by loading the fixed delay value stored in the register. In this case, the clock synchronization operation can be performed when the phase difference between the internal clock and the external clock is relatively small during the initial operation of the semiconductor memory device, and the delay value of the register according to the phase difference between the internal clock and the external clock even after the initial operation The most widely used register controlled delayed loop circuit is to adjust the fluctuation width to reduce the time it takes for the internal and external clocks to synchronize.

1 is a block diagram showing a register controlled delay locked loop (DLL) circuit according to the prior art.

Referring to FIG. 1, a register-controlled delay locked loop (DLL) circuit according to the prior art compares phases of a source clock REFCLK and a feedback clock FBCLK to generate a phase comparison signal PD_OUT. A timing pulse generator 120 for generating a plurality of timing pulses TPULSE <0:12> sequentially activated in response to the control clock CONTCLK synchronized with the source clock REFCLK. In order to achieve the delay lock, a delay control in which the value thereof changes in response to the phase comparison signal PD_OUT at the time of toggling the predetermined first timing pulse PHASE DECISION PULSE among the plurality of timing pulses TPULSE <0:12> Toggling time of the delay control unit 140 for generating the signal DLY_CONT and the second timing pulse PHASE UPDATE PULSE among the plurality of timing pulses TPULSE <0:12>-The first timing pulse PHASE DECISION PULSE) later than the time of toggling-at source clock (REFCLK) Reflecting the delay amount corresponding to the soft control signal DLY_CONT, the variable delay line 150 for outputting as the delay locked clock DLLCLK, and the actual delay condition of the source clock REFLCK are reflected in the delay locked clock DLLCLK. And a delay model unit 160 for outputting as a feedback clock FBCLK.

Referring to the basic locking operation based on the configuration of the register-controlled delay locked loop (DLL) circuit according to the related art described above, the reference edge of the source clock REFCLK having a different phase in the pre-locking state is generally a rising edge ( rising edge), and it does not matter if it is the falling edge-delays the phase of the source clock (REFCLK) and outputs it to the delay locked clock (DLLCLK) so that the reference edge of the feedback clock (FBCLK) is synchronized. In this case, since the delay lock clock DLLCLK outputs the feedback clock FBCLK by reflecting the actual delay condition of the source clock path REFCLK, the phase of the source clock REFCLK is increased as the delay amount increases. The phase difference between (REFCLK) and feedback clock (FBCLK) ˜ will decrease.

FIG. 2 is a circuit diagram showing in detail a configuration of a timing pulse generator according to the related art among the components of the register controlled delay locked loop (DLL) circuit according to the related art shown in FIG. 1.

For reference, among the components of the register controlled delay locked loop (DLL) circuit according to the prior art, the last one of the plurality of timing pulses TPULSE <0:12> generated by the timing pulse generator 120 according to the prior art is generated. That is, the twelfth timing pulse TPULSE <12> means that the delay shifting update period of the register controlled delay locked loop (DLL) circuit shown in FIG. 1 is toggled 13 times by the source clock REFCLK. It means that the time (13tCK).

In this case, the number of timing pulses TPULSE <0:12> shown in FIGS. 1 and 2 is merely a number defined for convenience of description, and in reality, the timing pulses generated by the timing pulse generator 120 are 13 times. It may be more or less than the number, i.e., the delay shifting update period of the register-controlled delay locked loop (DLL) circuit according to the prior art may be more than the time (12tCK) that the source clock (REFCLK) toggles 13 times. It may be less.

In addition, the delay shifting update period means that one of the components of the register-controlled delay locked loop (DLL) circuit according to the related art shown in FIG. 1 is based on the clock phase comparator 100. Time means the time to finish the operation. That is, in response to the output signal PD_OUT of the clock phase comparator 100, the delay control unit 140 and the variable delay line 150 operate to output a delay locked clock DLLCLK and delay the delay model unit 160. It means the time until the fixed clock DLLCLK is transferred to the clock phase comparator 100 as the feedback clock FBCLK. When this delay shifting update period is repeated, a locking operation that gradually reduces the phase difference between the source clock REFCLK and the feedback clock FBCLK may be performed.

Referring to FIG. 2, the timing pulse generator 120 according to the related art among the components of the register controlled delay locked loop (DLL) circuit according to the related art illustrated in FIG. 1 may toggle the control clock CONTCLK. Each time, the pulse toggling control unit 122 for toggling the plurality of timing pulses TPULSE <0:12> in a predetermined order, and the operation control unit 124 for repeating the operation of the pulse toggling control unit 122 Equipped.

Here, the pulse toggling control unit 122 may rest the control clock CONTCLK every time after the reference timing pulse TPULSE <0> of the plurality of timing pulses TPULSE <0:12> is toggled. Toggle the timing pulses TPULSE <1:12> sequentially.

That is, the pulse toggling control unit 122 includes a plurality of D flip-flops 122A, 122B, 122C, 122D, 122E, 122F, 122G, 122H, 122I, 122J, 122K, and 122L that are serially connected. To the data output terminal D_OUT in response to the control clock CONTCLK synchronized to the source clock REFCLK applied to CLK_IN and the previously activated timing pulse TPULSE <0:11> applied to the data input terminal D_IN. The timing pulses TPULSE <1:12> that are activated later are outputted.

The operation control unit 124 then generates a reference timing pulse TPULSE <0> in response to the timing pulse TPULSE <12> that toggles relatively late among the plurality of timing pulses TPULSE <0:12>. Toggle.

That is, the operation controller 124 activates the reference timing pulse TPULSE <0> when all of the timing pulses TPULSE <1:12> are deactivated, and activates the reference timing pulse TPULSE1 <0> according to the activation of the reference timing pulse TPULSE1 <0>. The reference timing pulse TPULSE <0> is deactivated in response to the timing pulse TPULSE <1>.

Therefore, the timing pulse generator 120 sequentially toggles the remaining timing pulses TPULSE <1:12> in response to the reference timing pulses TPULSE <0> toggling, and the remaining timing pulses TPULSE. The remaining timing pulses TPULSE <1:12> may be sequentially toggled again by re-toggling the reference timing pulses TPULSE <0> in response to the end of the toggling of <1:12>. Make sure

 That is, when the control clock CONTCLK synchronized to the source clock REFCLK continues to toggle, the plurality of timing pulses TPULSE <0:12> are repeatedly toggled sequentially.

As such, the first timing pulse PHASE DECISION PULSE-TPULSE <1> of the plurality of timing pulses TPULSE <0:12> generated by the timing pulse generator 120 does not mean TPULSE <0:12. > Means any one of pulses-to the delay control unit 140 to adjust the timing at which the value of the delay control signal DLY_CONT is determined in response to the phase comparison signal PD_OUT.

Also, the second timing pulse PHASE UPDATE PULSE-TPULSE <2> of the plurality of timing pulses TPULSE <0:12> does not mean a pulse of any one of TPULSE <0:12>. Toggle at a later time than when the 1 timing pulse (PHASE DECISION PULSE) toggles-to the variable delay line 150 to reflect the delay amount corresponding to the delay control signal DLY_CONT to the source clock REFCLK. The timing, that is, the timing at which the source clock REFCLK is output as the delay locked clock DLLCLK, is adjusted.

That is, it is understood that the plurality of timing pulses TPULSE <0:12> generated by the timing pulse generator 120 are generated to define the operation timing of the register controlled delay locked loop (DLL) circuit shown in FIG. 1. Can be.

As described above, the remaining timing pulses other than the first and second timing pulses among the plurality of timing pulses TPULSE <0:12> generated by the timing pulse generator 120 are not actually used and are simply used as the first timing pulses. A time interval between the timing pulse and the second timing pulse is present to define the frequency unit of the source clock REFCLK.

Accordingly, the second timing pulse PHASE UPDATE PULSE after at least one timing pulse is further toggled after the first timing pulse PHASE DECISION PULSE of the plurality of timing pulses TPULSE <0:12> is toggled. Is toggled.

However, referring to an operation of generating a plurality of timing pulses TPULSE <0:12>, 12 flip-flops 122A, 122B, 122C, 122D, to generate 13 timing pulses TPULSE <0:12>, 122E, 122F, 122G, 122H, 122I, 122J, 122K, 122L) are used.

That is, 12 flip-flops 122A, 122B, to generate the remaining 12 timing pulses TPULSE <1:12> except for the reference timing pulse TPULSE <0> whose activation is controlled by the operation controller 124. 122C, 122D, 122E, 122F, 122G, 122H, 122I, 122J, 122K, 122L) are used.

As such, it is not only very inefficient to substantially increase the number of flip-flops to the number of timing pulses in order to generate a plurality of timing pulses TPULSE <0:12> that are sequentially toggled at regular intervals. There is a problem of increasing the layout of the semiconductor device.

In addition, the above-mentioned problem is that the external clock corresponding to the delay shifting update period of the delay locked loop (DLL) circuit in a semiconductor device that is developed in the future has a toggling period tCK of the external clock CLK applied to the semiconductor device to be small. It may occur more frequently when the number of toggles of the clock CLK increases.

For example, when the number of toggling of the external clock CLK corresponding to the delay shifting update period of the delay locked loop DLL circuit is not longer than 13 times, but 30 times longer than that, that is, delay When the delay shifting update period of the fixed loop (DLL) circuit is increased from the time 13tCK of the external clock CLK toggling 13 times, the time of the external clock CLK 30 toggling 30 times (30tCK), Since two timing pulses are required and 29 flip-flops are required for the delay locked loop (DLL) circuit, the delay locked loop (for a semiconductor device having a relatively small toggling period tCK of the external clock CLK) is required. The problem may arise that the DLL circuit takes up more layout.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems, and an object thereof is to provide a register controlled delay locked loop capable of adjusting a section in which a timing pulse is generated during a delay shifting update period.

According to an aspect of the present invention for achieving the above object, a clock phase comparison unit for generating a phase comparison signal by comparing the phase of the source clock and the feedback clock; In order to achieve delay lock, a delay amount corresponding to the phase comparison signal is determined at a first time point, and a delay amount determined at a second time point, which is later than the first time point, is reflected to the source clock and output as a delay lock clock. Clock delay unit; A delay model unit for outputting the delay clock as the feedback clock by reflecting an actual delay condition of the source clock path; A timing pulse generator configured to generate a plurality of timing pulses sequentially activated in response to toggling of a control clock, wherein the first and second time points are determined in response to a predetermined timing pulse; And a clock toggle control unit configured to control on / off of toggling the control clock according to the toggle of the source clock in response to an update timing pulse among the plurality of timing pulses and the phase comparison signal. Provide a circuit.

The present invention described above disables a register-controlled delay lock by disabling a plurality of timing pulse generation operations at a time point at which a component of the register-controlled delay lock loop does not directly control its operation by a plurality of timing pulses. There is an effect of always generating the minimum number of timing pulses regardless of the operating frequency or power supply voltage level during the delay shifting update period of the loop.

As a result, there is an effect that the area of the circuit for generating a plurality of timing pulses does not increase regardless of the operating frequency or the level of the power supply voltage.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be configured in various different forms, only this embodiment is intended to complete the disclosure of the present invention and to those skilled in the art the scope of the present invention It is provided to inform you completely.

3 is a block diagram illustrating a register controlled delay locked loop (DLL) circuit according to an embodiment of the present invention.

Referring to FIG. 3, in the register-controlled delay locked loop DLL circuit according to an embodiment of the present invention, a phase comparison signal PD_OUT is generated by comparing phases of a source clock REFCLK and a feedback clock FBCLK. And a delay amount corresponding to the phase comparison signal PD_OUT at a first time point to determine the delay phase, and a delay amount determined at a second time point-later than the first time point. The feedback clock FBCLK reflects the clock delay units 340 and 350 that are reflected to the clock REFCLK and output as the delay locked clock DLLCLK, and the actual delay condition of the source clock REFLCK is reflected in the delay locked clock DLLCLK. And a plurality of timing pulses TPULSE <0:12> which are sequentially activated in response to the delay model unit 360 for outputting as a control clock CONTCLK synchronized with the source clock REFCLK. In response to timing pulses (PHASE DECISION PULSE, PHASE UPDATE PULSE) The timing pulse generator 320 for determining the first and second time points, and the update timing pulse UPDATE TIMING PULSE among the plurality of timing pulses TPULSE <0:12> and the phase comparison signal PD_OUT. And a clock toggle control unit 380 for controlling on / off of toggling the control clock CONTCLK according to the toggle of the source clock REFCLK.

Here, the clock delay units 340 and 350 may toggle the predetermined timing timing PHASE DECISION PULSE corresponding to the first time point among the plurality of timing pulses TPULSE <0:12> to achieve delay lock. The delay control unit 340 for generating the delay control signal DLY_CONT whose value varies in response to the phase comparison signal PD_OUT at, and corresponds to the second time point of the plurality of timing pulses TPULSE <0:12>. Delay amount corresponding to the delay control signal DLY_CONT to the source clock REFCLK at the time of toggling the scheduled second timing pulse PHASE UPDATE PULSE-later than the timing of toggling the first timing pulse PHASE DECISION PULSE A variable delay line 350 for outputting as a delay locked clock DLLCLK is provided.

Here, the timing pulse generation unit 320 has the same structure as the timing pulse generation unit 120 among the components of the register-controlled delayed fixed loop (DLL) circuit according to the prior art shown in FIG. The timing pulse generator 120 according to the related art illustrated in FIG. 2 directly receives the source clock REFCLK and generates a control clock CONTCLK synchronized with the source clock REFCLK to generate a plurality of timing pulses TPULSE < 0:12>), the timing pulse generator 320 according to the embodiment of the present invention shown in FIG. 3 controls the control clock (synchronized to the source clock REFCLK directly from the clock toggling controller 380). The only difference is that they are used to generate multiple timing pulses (TPULSE <0:12>). Therefore, the detailed configuration of the timing pulse generator 320 according to the embodiment of the present invention shown in FIG. 3 will not be described.

FIG. 4 is a detailed circuit diagram illustrating a clock toggling control unit among components of a register controlled delay locked loop (DLL) circuit according to an exemplary embodiment of the present invention illustrated in FIG. 3.

Referring to FIG. 4, among the components of a register-controlled delay locked loop (DLL) circuit according to an exemplary embodiment of the present invention, the clock toggling control unit 380 responds to toggling of an update timing pulse (UPDATE TIMING PULSE). Compare the logic phases of the phase comparison signal PD_OUT and the free phase comparison signal PD_OUT_PRE with the prephase comparison signal output 382 for outputting the phase comparison signal PD_OUT as the prephase comparison signal PD_OUT_PRE. A logic level comparison unit 384 for generating a clock toggle control signal CLK_TOG_CONT whose logic level is determined in response to the comparison result PD_CHG and the UPDATE TIMING PULSE, and a clock toggle control signal A toggling control unit 386 is configured to control on / off that the control clock CONTCLK is toggled according to the toggle of the source clock REFCLK in response to the CLK_TOG_CONT.

Here, when the phase comparison signal PD_OUT has a logic level different from that of the prephase comparison signal PD_OUT_PRE, the logic level comparison unit 384 sets the clock toggle control signal CLK_TOG_CONT to logic 'low'. When the phase comparison signal PD_OUT has the same logic level as the prephase comparison signal PD_OUT_PRE, the clock toggle control signal CLK_TOG_CONT is generated in response to the update timing pulse UPDATE TIMING PULSE being toggled. Disable logic 'high'.

In addition, the toggling control unit 386 toggles the control clock CONTCLK according to the toggling of the source clock REFCLK in a section in which the clock toggle control signal CLK_TOG_CONT is activated as logic 'low'. The control clock CONTCLK is deactivated regardless of the toggling of the source clock REFCLK in a section in which the clock toggle control signal CLK_TOG_CONT is deactivated to logic 'high'.

For reference, a pre update timing pulse PRE UPDATE TIMING PULSE used inside the logic level comparator 384 among the components of the clock toggling control unit 380 illustrated in FIG. 4 is more than the update timing pulse PRE UPDATE TIMING. The update timing pulse D (UPDATE TIMING PULSE D) is a pulse delaying the update timing pulse D (UPDATE TIMING PULSE) by a predetermined time, and both pulses are toggled first by one cycle (1 tck) of the control clock CONTCLK. The logic level comparator 380 is only a pulse for guaranteeing an operating margin based on an update timing pulse, and does not have a feature as a pulse itself.

 The update timing pulse UPDATE TIMING PULSE is any one of a plurality of timing pulses TPULSE <0:12> generated by the timing pulse generator 320, and the update timing pulse UPDATE TIMING PULSE is A pulse different from the first timing pulse PHASE DECISION PULSE provided to the delay control unit 340 or the second timing pulse PHASE UPDATE PULSE provided to the variable delay line 350. In the present invention, the update timing pulse UPDATE TIMING PULSE is a timing pulse TPULSE <12> which toggles relatively late among the plurality of timing pulses TPULSE <0:12>.

The operation thereof will be described based on the configuration of the register-controlled delay locked loop (DLL) circuit according to the embodiment of the present invention described above.

First, the basic locking operation will be described. The reference edge of the source clock REFCLK having a different phase in the pre-locking state, which generally refers to a rising edge, may be a falling edge. In order to synchronize the reference edge of the feedback clock FBCLK, the phase of the source clock REFCLK is delayed and output to the delay locked clock DLLCLK. In this case, the delay locked clock DLLCLK is the source clock REFCLK. Since the output is reflected as the feedback clock FBCLK, the phase difference between the source clock REFCLK and the feedback clock FBCLK gradually decreases as the amount of delay increases.

In this case, the timing pulse generator 320 provides the first timing pulse PHASE DECISION PULSE among the plurality of timing pulses TPULSE <0:12> to the delay controller 340, and the second timing pulse PHASE UPDATE. By providing the PULSE to the variable delay line 350, the delay control unit 340 and the variable delay line 350 may delay the phase of the source clock REFCLK and output the delayed clock to the DLLCLK. To make it work. However, a plurality of timing pulses TPULSE <0:12> are not directly provided to the clock phase comparator 300 or the delay model unit 360, which are the remaining components.

Accordingly, the clock toggling control unit 380 controls the toggling of the control clock CONCLK on / off according to the result of the phase comparison signal PD_OUT output from the clock phase comparator 300, thereby generating a timing pulse generator ( In operation 320, an operation of generating a plurality of timing pulses TPULSE <0:12> is controlled on / off.

Specifically, among the components of the clock toggling control unit 380, the prephase comparison signal output unit 382 may update the phase comparison signal PD_OUT output from the clock phase comparison unit 300 to update timing pulses (UPDATE TIMING PULSE). In response to, the signal is output as the pre-phase comparison signal PD_OUT_PRE.

At this time, since the toggling time point of the update timing pulse UPDATE TIMING PULSE is a time point when all of the operations of the variable delay line 350 are finished, that is, the delay amount corresponding to the phase comparison signal PD_OUT is variable delay line 350. Since it is a time point reflected by the delay locked clock (DLLCLK) output from the), if the delay amount of the variable delay line 350 in response to the phase comparison signal (PD_OUT) is updated, the delay locked clock (DLLCLK) is delay model unit The phase comparison signal PD_OUT and the prephase comparison signal PD_OUT_PRE generated by reaching the clock phase comparison unit 300 as the feedback clock FBCLK through 360 may have different values.

On the other hand, when the delay amount of the variable delay line 350 is not updated in response to the phase comparison signal PD_OUT, the delay lock clock DLLCLK passes through the delay model unit 360 and compares the clock phase as the feedback clock FBCLK. The phase comparison signal PD_OUT and the prephase comparison signal PD_OUT_PRE generated after reaching the unit 300 may have the same value.

By using the characteristics of the phase comparison signal PD_OUT and the prephase comparison signal PD_OUT_PRE, the logic level comparison unit 384 and the toggling control unit 386 among the components of the clock toggle control unit 380 use the phase comparison signal. When the PD_OUT and the prephase comparison signal PD_OUT_PRE have different values, the first clock pulse PHASE DECISION PULSE and the control clock CONTCLK are controlled to be toggled according to the toggle of the source clock REFCLK. By generating a plurality of timing pulses TPULSE <0:12> including the second timing pulse PHASE UPDATE PULSE, the delay controller 340 and the variable delay line 350 delay the phase of the source clock REFCLK. Allows you to perform a delayed clock (DLLCLK) output.

On the contrary, when the phase comparison signal PD_OUT and the prephase comparison signal PD_OUT_PRE have the same value, the control clock CONTCLK is controlled to remain inactive regardless of toggling of the source clock REFCLK. Prevents generation of timing pulses TPULSE <0:12>.

In this case, when the phase comparison signal PD_OUT and the prephase comparison signal PD_OUT_PRE have the same value, the delay amount of the variable delay line 350 is not updated in response to the phase comparison signal PD_OUT as described above. Therefore, in some cases, the phase comparison signal PD_OUT and the prephase comparison signal PD_OUT_PRE generated by the clock phase comparison unit 300 may have the same value, but the variable delay line 350 may correspond to the phase comparison signal PD_OUT. Whether or not the amount of delay is updated or not, after the toggling time of the UPDATE TIMING PULSE, that is, all of the operations of the variable delay line 350 are terminated, the delay lock clock DLLCLK is delayed model unit 360. From the point in time at which the signal is transmitted to the prephase comparison signal output unit 382, the phase comparison signal PD_OUT and the prephase comparison signal PD_OUT_PRE may sometimes have the same value.

That is, the delay locked clock DLLCLK output from the variable delay line 350 reaches the clock phase comparator 300 as the feedback clock FBCLK via the delay model unit 360 to generate a new phase comparison signal PD_OUT. Until it is generated, the phase comparison signal PD_OUT and the prephase comparison signal PD_OUT_PRE always have the same value.

Accordingly, in the logic level comparator 384 and the toggling controller 386 among the components of the clock toggling controller 380, the delay locked clock DLLCLK output from the variable delay line 350 is delayed model unit 360. The control clock CONTCLK is inactive regardless of toggling of the source clock REFCLK until it reaches the clock phase comparator 300 as a feedback clock FBCLK and generates a new phase comparison signal PD_OUT. It is controlled to maintain a state so that a plurality of timing pulses TPULSE <0:12> cannot be generated.

For reference, when the delay amount of the variable delay line 350 is not updated corresponding to the phase comparison signal PD_OUT once, the timing pulse generator 320 may enter the plurality of timing pulses TPULSE <0:12>. ), The delay control unit 340 and the variable delay line 350 may completely stop operation because the lock is completed. If this state is a phenomenon in which locking is completed and no longer needs to be updated, it may be stopped. If the delay amount of the variable delay line 350 is not updated in response to the phase comparison signal PD_OUT, it should not be stopped if it is caused by the instability of the power supply voltage. Accordingly, when the delay amount of the variable delay line 350 is not updated in response to the phase comparison signal PD_OUT, the timing pulse generator 320 generates a plurality of timing pulses TPULSE <0:12>. If not, the timing pulse generator 320 may forcibly generate a plurality of timing pulses TPULSE <0:12> after a predetermined time.

As described above, according to the embodiment of the present invention, the clock phase comparison unit 300 and the delay model unit 360 whose operation is not directly controlled by a plurality of timing pulses among the components of the register-controlled delay locked loop may be applied. ) Disables the operation of generating a number of timing pulses (TPULSE <0:12>) at the point of operation, so that during the delay-shifting update period of the register-controlled delay locked loop, the minimum Only a number of timing pulses can be generated.

That is, the timing pulse generator 320 generates a plurality of timing pulses during the operation of the clock phase comparator 300 and the delay model unit 360 whose operations are not directly controlled by the plurality of timing pulses. Since only a number of timing pulses capable of operating the delay control unit 340 and the variable delay line 350 may be required.

As a result, even if the operating frequency or the level of the power supply voltage is changed to increase the operating time of the clock phase comparison unit 300 and the delay model unit 360, the area of the circuit for generating a plurality of timing pulses needs to be increased. none.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill.

For example, the logic gate and the transistor illustrated in the above-described embodiment should be implemented differently in position and type depending on the polarity of the input signal.

1 is a block diagram showing a register controlled delay locked loop (DLL) circuit according to the prior art;

FIG. 2 is a circuit diagram showing in detail a configuration of a timing pulse generation unit according to the prior art among the components of the register controlled delay locked loop (DLL) circuit according to the prior art shown in FIG.

3 is a block diagram illustrating a register controlled delay locked loop (DLL) circuit in accordance with an embodiment of the present invention.

4 is a circuit diagram illustrating in detail a clock toggling control unit among components of a register controlled delay locked loop (DLL) circuit according to the embodiment of the present invention shown in FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

100, 300: clock phase comparison unit 120, 320: timing pulse generator

140, 340: delay control unit 150, 350: variable delay line

160, 360: delay model unit 380: clock toggle control

382: pre-phase comparison signal output unit 384: logic level comparison unit

386: toggle control

Claims (9)

A clock phase comparison unit for comparing a phase of a source clock and a feedback clock to generate a phase comparison signal; In order to achieve delay lock, a delay amount corresponding to the phase comparison signal is determined at a first time point, and a delay amount determined at a second time point, which is later than the first time point, is reflected to the source clock and output as a delay lock clock. Clock delay unit; A delay model unit for outputting the delay clock as the feedback clock by reflecting an actual delay condition of the source clock path; A timing pulse generator configured to generate a plurality of timing pulses sequentially activated in response to toggling of a control clock, wherein the first and second time points are determined in response to a predetermined timing pulse; And A clock toggle control unit for controlling on / off of toggling the control clock according to the toggle of the source clock in response to an update timing pulse and the phase comparison signal among the plurality of timing pulses Delay fixed loop circuit having a. The method of claim 1, The clock delay unit, A delay control unit for generating a delay control signal whose value varies in response to the phase comparison signal at a time of toggling a predetermined first timing pulse among the plurality of timing pulses; And The delay lock clock by reflecting a delay amount corresponding to the delay control signal to the source clock at a toggling time point of a predetermined second timing pulse among the plurality of timing pulses, which is later than a toggling time point of the first timing pulse A delay locked loop circuit having a variable delay line for outputting the signal. The method of claim 2, The timing pulse generator, And activating at least one timing pulse after the first timing pulse of the plurality of timing pulses is activated, and then activating the second timing pulse. The method of claim 1, The timing pulse generator, A pulse toggle control unit for toggling a plurality of timing pulses in a predetermined order each time the control clock is toggled; And And a delay control loop circuit including an operation control unit for repeating the operation of the pulse toggling control unit. The method of claim 4, wherein The pulse toggling control unit, And a remaining timing pulse is sequentially toggled each time the control clock toggles after the reference timing pulse among the plurality of timing pulses is toggled. The method of claim 5, The operation control unit, And delaying the reference timing pulse in response to a timing pulse that toggles relatively late among the plurality of timing pulses. The method of claim 1, The clock toggle control unit, A prephase comparison signal output unit for outputting the phase comparison signal as a prephase comparison signal in response to the toggling of the update timing pulse; A logic level comparison unit for comparing a logic level of the phase comparison signal and the prephase comparison signal and generating a clock toggling control signal whose logic level is determined in response to a comparison result and the update timing pulse; And a toggling control unit for controlling on / off that the control clock is toggled in response to toggling of the source clock in response to the clock toggling control signal. The method of claim 7, wherein The logic level comparison unit, When the phase comparison signal has a different logic level than the prephase comparison signal, the clock toggling control signal is activated. And the clock toggle control signal is deactivated in response to the update timing pulse being toggled when the phase comparison signal has the same logic level as the prephase comparison signal. The method of claim 8, The toggling control unit, Toggle the control clock according to the toggle of the source clock in the activation period of the clock toggle control signal, And deactivating the control clock regardless of toggling of the source clock in an inactivation section of the clock toggling control signal.

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