KR20110060741A - Delay locked loop circuit - Google Patents

Abstract

PURPOSE: A delay locked loop circuit is provided to perform delay locked without increasing the number of delay line by comparing a reference clock with a negative reference clock to perform delay locked. CONSTITUTION: A buffering part(40) buffers an external clock. A divider(41) divides the output clock of the buffering part into two. The divider generates a positive reference clock. A first phase comparison unit(42) compares a positive clock with the phase of a feedback clock. The first phase comparison unit outputs a first phase comparison signal. A second phase comparator(43) compares a negative reference clock with the phase of a feedback clock. A phase information selecting unit(45) generates a phase information signal. A variable delayer varies the amount of delay of the positive reference clock. A delay model unit(44) delays the output clock of the variable delayer.

Description

DELAY LOCKED LOOP CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly to a delay locked loop (DLL) of a semiconductor memory device.

In general, a clock is used as a reference for timing operation in a system or a circuit, and may be used to ensure faster operation without an error. When a clock input from the outside is used internally, a time delay (clock skew) caused by an internal circuit occurs, and a DLL is used to compensate for this time delay so that the internal clock has the same phase as the external clock. have.

On the other hand, DLL has the advantage of being less affected by noise than the conventional phase locked loop (PLL), which is widely used in synchronous semiconductor memory including DDR Double Data Rate Synchronous DRAM (SDRAM). .

1 is a block diagram illustrating a configuration of a two-division DLL according to the prior art.

Referring to FIG. 1, the DLL includes a buffering unit 10, a divider 11, a phase comparing unit 12, a delay control unit 14, a variable delay unit 15, and a delay model unit 13.

The buffering unit 10 receives the external clock EXTCLK, buffers it, and delivers it to the inside of the DLL, and the divider 11 divides the signal received from the buffering unit 10 into two parts, the first internal being the reference clock REFCLK. A second internal clock ICLK2 having a 90 degree phase difference from the clock ICLK1 and the reference clock REFCLK is generated. 2 is a timing diagram of the DLL input clock passing through the divider 11. When the external clock EXTCLK is divided into two, the period of the first internal clock ICLK1 and the second internal clock ICLK2 is twice the external clock period tCK. The second internal clock is 90 degrees behind the first internal clock. The phase comparator 12 compares the phases of the reference clock REFCLK and the feedback clock FBCLK, and the delay controller 14 generates a delay control signal CTR in response to the output signal of the phase comparator 12. do. The variable delay unit 15 delays the reference clock REFCLK in response to the delay control signal CTR. The delay model unit 13 outputs a feedback clock FBCLK by reflecting the delay of the actual clock / data path to the output signal of the variable delay unit 15.

Here, the feedback clock FBCLK becomes a clock obtained by adding the delay time of the variable delay unit 15 and the delay time of the delay model unit 13 to the reference clock REFCLK. The DLL compares the reference clock (REFCLK) and the feedback clock (FBCLK), and when the two clocks have the minimum jitter, the locking is performed to output the desired DLL clock (DLLCLK1, DLLCLK2).

In general, the amount of delay required for the phase locked loop to lock is equivalent to at least 0 to 1 tCK (cycle of EXTCLK). Therefore, the DLL should have as many delay lines as tCK to use. When two divisions are performed, the period of the clock used in the DLL is twice the external clock period (tCK), and the amount of delay required to lock the delay corresponds to twice the external clock period (tCK). To illustrate this, FIG. 3 is a timing diagram of the amount of delay required for DLL locking. In FIG. 3 (a), when the clock division is not used, the amount of delay required to match the phase of the feedback clock FBCLK and the reference clock REFCLK is D1. Although FIG. 3 (b) divides the clock, the rising edge of the feedback clock FBCLK does not differ much from the rising edge of the reference clock REFCLK. It is the case that delay lock is possible with as much delay. On the other hand, in FIG. 3 (c), the rising edge of the feedback clock FBCLK is located far from the reference clock REFCLK, and the amount of delay required for locking is external clock cycle tCK. More D2. Therefore, if two divisions are made, there is a problem of increasing the area of the variable delay unit 15, and if a large number of delays are used to lock the delay, an increase in the use current may occur.

It is an object of the present invention to provide a DLL that operates in a two-division DLL circuit to enable delaying using a small amount of delay.

According to an aspect of the present invention, a buffering unit for buffering an external clock, a divider unit for generating a positive reference clock by dividing an output clock of the buffering unit by two, and comparing a phase of a positive reference clock and a feedback clock to compare a first phase. A first phase comparator for outputting a signal, a second phase comparator for outputting a second phase comparison signal by comparing a phase of the feedback clock with a negative reference clock that is opposite to the positive reference clock and the first and second clocks A phase information selector for generating a phase information signal by selecting one of the positive reference clock and the sub reference clock for delay lock according to the initial comparison value of the phase comparator, and delay lock is performed in response to the phase information signal. By modeling the delay components of the variable delay unit and the actual clock path to vary the delay amount of the positive reference clock until only the delay amount modeled for the output clock of the variable delay unit A delay locked loop circuit including a delay model unit for outputting a large delay and outputting a feedback clock is provided.

An initial comparison value that is a phase information signal at a specific time point using the output of the first phase comparator comparing the phases of the positive reference clock and the feedback clock and the output of the second phase comparator comparing the phases of the negative reference clock and the feedback clock. By selecting a reference clock with a small delay delay delay to generate a delay increase and decrease signal, the delay can be fixed without increasing the delay line, thereby reducing the area of the two-division DLL circuit.

According to the present invention, when the external clock is divided into two parts, the fixed reference clock and the negative reference clock are locked compared to the feedback clock, so that the delay can be fixed without increasing the delay line, thereby reducing the layout area of the DLL. Reduced current has the effect of reducing power consumption.

DETAILED DESCRIPTION Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

4 is a block diagram illustrating a DLL circuit according to an embodiment of the present invention.

Referring to FIG. 4, the DLL receives the output of the buffering unit 40, the buffering unit 40, which buffers the external clock EXTCLK and delivers the inside of the DLL, and receives the first internal clock ICLK1 and the second internal clock ICLK2. The first phase comparator 42 comparing the phases of the positive reference clock REFCLK and the feedback clock FBCLK with the frequency divider 41 divided by the first clock and the first internal clock ICLK1 as the positive reference clock REFCLK. ), The second phase comparator 43 comparing the phases of the sub reference clock REFCLKB and the feedback clock FBCLK, and modeling the delay component of the actual clock path to model the output clock of the variable delay unit 46. According to the initial comparison value of the delay model unit 44 and the first and second phase comparators for delaying the output amount by a delay amount, delay fixing of one of the positive reference clock REFCLK and the negative reference clock REFCLKB is performed. A phase information selector 45 and a phase information selector 4 for generating a phase information signal by selecting the reference clock A variable delay unit 46 for delaying the reference clock REFCLK in response to the output of 5) is provided.

First, since the rising edge of the positive reference clock REFCLK and the rising edge of the sub-reference clock REFCLKB both have the rising edge information of the external clock EXTCLK, the feedback clock It does not matter if the FBCLK is locked with the phase of either the positive reference clock REFCLK or the negative reference clock REFCLKB. The phase comparator outputs logic 'HIGH' when the phase of the feedback clock FBCLK is HIGH at the rising edge of the reference clock and logic when the abnormality of the feedback clock FBCLK is LOW. Output LOW.

FIG. 5 is a timing diagram for describing an operation of the DLL circuit of FIG. 4.

FIG. 5A illustrates a case where the output of the first phase comparator 42 is logic 'high', and the amount of delay required to match the phase of the positive reference clock REFCLK and the feedback clock FBCLK is D3, and the amount of delay required to match the phase of the negative reference clock REFCLKB and the feedback clock FBCLK is D4. Therefore, the phase of the feedback clock FBCLK is matched to the positive reference clock REFCLK, which requires a smaller amount of delay for locking.

FIG. 5B shows a case where the output of the second phase comparator is logic 'HIGH', and the amount of delay required to match the phase of the positive reference clock REFCLK and the feedback clock FBCLK is D5. The amount of delay required to match the phase of the sub reference clock REFCLKB and the feedback clock FBCLK is D6. Therefore, the phase of the feedback clock FBCLK is matched to the negative reference clock REFCLKB, which requires a smaller amount of delay for locking.

FIG. 6 is an exemplary embodiment of the phase information selector 45 of FIG. 4, and an initial comparison value latch for latching phase information which is an output of the first and second phase comparators at the time when the driving start signal START is applied. And a multiplexer 61 for selecting the first or second phase comparison signal and outputting the first or second phase comparison signal as a phase information signal in response to the output values CASE1 and CASE2 of the initial comparison value latch unit. The initial comparison value latch section 60 includes a switch section 601 that is turned on in response to the drive start signal START and a latch section 602 for latching a signal passing through the switch section 601. The driving start signal START is a signal applied by the user after the DLL is activated and before delay locking is performed. The multiplexer 61 compares the output of the phase information selector 60 with the outputs of the first and second phase comparators to compare the phase and feedback clock of any reference clock among the positive reference clock REFCLK and the secondary reference clock REFCLKB. It is selected whether or not to match the phase of (FBCLK) uses less delay and outputs it as the phase information signals DEL_INC and DEL_DEC.

The operation of the present invention will be described with reference to FIG.

When the driving start signal START is applied to the input terminal of the NOR gate NOR, the output PD1 of the first phase comparator at the time when the driving start signal START is applied passes through the switch unit 601 and the latch unit 602. ) The output PD1 of the stored first phase comparator and the initial comparison values CASE1 and CASE2 which are inverted outputs are output. The initial comparison value CASE1 and the output PD1 of the first phase comparator are applied to the first NAND gate NAND1, and the output PD2 of the second phase comparator of the second comparison comparator is the second NAND gate. It is applied as an input to (NAND2). When the output of the first NAND gate NAND1 and the output of the second NAND gate NAND2 are applied to the third NAND gate NAND3, the third NAND gate NAND3 outputs phase information signals DEL_INC and DEL_DEC. do.

Since the initial comparison value CASE1 and the initial comparison value CASE2 are opposite signals and have the same operation characteristics, only the case where the initial comparison value CASE1 is logical 'high' will be described as an example. When the initial comparison value CASE1 is logic 'high', the initial comparison value CASE2 is logic 'low'. Therefore, the output of the second NAND gate NAND2 always has an output value of logic 'HIGH' regardless of the output PD2 of the second phase comparator. However, the output of the first NAND gate NAND1 is changed according to the value of the output PD1 of the first phase comparator. When the output PD1 of the first phase comparator is logic 'high', the first NAND gate NAND1 outputs logic 'low' and the third NAND gate NAND3 is logic 'high' ( HIGH) to generate the phase information signal DEL_INC. The variable delay unit 46 increases the delay by the phase information signal DEL_INC. When the output PD1 of the first phase comparator becomes logic 'low' due to an increase in delay, the first NAND gate NAND1 outputs a logic 'high' and the third NAND gate NAND3. Outputs a logic 'LOW' to generate a delay reduction signal DEL_DEC. Accordingly, the variable delay unit 46 reduces the delay, and when the phases of the positive reference clock REFCLK and the feedback clock FBCLK coincide with each other, delay locking is performed to output the DLL clocks DLLCLK1 and DLLCLK2.

When the DLL is in continuous operation by adjusting the delay amount for locking, there may be a case where the locking cannot be achieved due to sudden power supply voltage and other operating environment changes. In this case, the problem may be solved by applying the stuck fail signal STUCK to the NOR gate NOR of the initial comparison value latch unit 60. The operation will be described below.

The case where the first phase information signal PI1 is logic 'high' will be described by way of example. As soon as the DLL is in continuous operation by adjusting the delay amount for locking, the output PD1 of the first phase comparator is momentarily logic at high. If changed to 'LOW', the multiplexer 61 will generate the phase information signal DEL_DEC. In this case, the delay must be reduced to lock the delay, but there may be a case where the amount of delay to be reduced for the delay lock is insufficient. As a result, delay locks cannot be achieved due to lack of delay. In this case, the threshold fail signal STUCK is applied to the NOR gate NOR of the initial comparison value latch unit 60 to newly update the initial comparison values CASE1 and CASE2 that are outputs of the initial comparison value latch unit 60 to multiplex the multiplexer. By passing to 61, delay locking is possible.

Although the technical spirit of the present invention has been described in detail according to the above embodiments, it should be noted that the above embodiments are for the purpose of explanation and not for the limitation. In addition, one of ordinary skill in the art will appreciate that various implementations within the scope of the technical idea of the present invention are possible.

1 is a block diagram of a conventional two-division DLL.

2 is a view showing a relationship between the external clock and the first and second internal clocks dispensed.

Figure 3 shows the delay amount required for delay fixing, (a) shows the delay amount required for delay fixing when not divided, and (b) and (c) shows the delay amount necessary for delay fixing when divided by two City road.

4 is a block diagram of one embodiment of the present invention.

5 is a timing diagram for explaining the operation of the present invention of FIG.

6 is an embodiment of a phase information selector of FIG. 4; FIG.

Claims (4)

A buffering unit for buffering an external clock; A divider for dividing the output clock of the buffering unit into two to generate a positive reference clock; A first phase comparator for comparing a phase of the positive reference clock and a feedback clock to output a first phase comparison signal; A second phase comparator for outputting a second phase comparison signal by comparing a phase of the feedback clock with a negative reference clock having an opposite phase to the positive reference clock; A phase information selector for generating a phase information signal by selecting any one of the positive reference clock and the sub reference clock as a reference clock for delay lock according to an initial comparison value of the first and second phase comparators; A variable delay unit for varying a delay amount of the fixed reference clock until delay lock is performed in response to the phase information signal; And Delay model unit for modeling the delay component of the actual clock path to delay the output clock of the variable delay unit by the modeled delay amount to output to the feedback clock Delay fixed loop circuit having a. The method of claim 1, The phase information selection unit, An initial comparison value latch unit for latching the initial comparison value in response to a delay locked loop driving start signal; And And a multiplexing section for selecting the first or second phase comparison signal and outputting the first or second phase comparison signal as the phase information signal in response to an output value of the initial comparison value latch section. The method of claim 2, The initial comparison value latch unit, A switch unit for transferring the initial comparison value in response to the delay locked loop driving start signal; And And a latch unit for latching an output signal of the switching unit. The method according to claim 2 or 3, And the initial comparison value latch unit latches the initial comparison value in response to a stuckfail signal together with the delay locked loop driving start signal.

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