KR20100075066A - Method of fabricating thin film transistor substrate and thin film transistor substrate fabricated thereby - Google Patents

Abstract

PURPOSE: A method for manufacturing a thin film transistor substrate and the thin film transistor substrate manufactured by the same are provided to stably maintain a cell gap between the thin film transistor substrate and an upper substrate. CONSTITUTION: Partition walls(80a,80b) defining a pixel area are formed on a substrate. Color filters(90R,90G) are applied on the pixel area. An overcoat layer is formed on the substrate. The overcoat layer includes protrusions. A plurality of double column spacers is formed. The second light shielding pattern is formed on part of a signal line.

Description

Method of fabricating a thin film transistor substrate and a thin film transistor substrate produced by the same {Method of fabricating thin film transistor substrate and thin film transistor substrate fabricated

The present invention relates to a method for manufacturing a thin film transistor substrate and a thin film transistor substrate manufactured thereby, and more particularly, to a thin film transistor substrate having improved reliability and a method for manufacturing the same.

Liquid crystal display (LCD), the most widely used flat panel display (FPD) in recent years, consists of two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween. A display device adjusts the amount of light transmitted by rearranging liquid crystal molecules of a liquid crystal layer by applying a voltage.

Among the two substrates constituting the liquid crystal display, the thin film transistor substrate includes a plurality of thin film transistors and pixel electrodes. Recently, a color on array (COA) structure in which a color filter is formed on a thin film transistor substrate has been studied to improve flattening characteristics, optical characteristics, and alignment problems of a liquid crystal display.

In general, in the COA structure, the light shielding pattern and the column spacer process are performed together. However, the level of the column spacer is reduced by the heat generated during the process, so that it is difficult to maintain the liquid crystal margin, thereby reducing the reliability of the display device.

The technical problem to be solved by the present invention is to provide a method for manufacturing a thin film transistor substrate with improved reliability.

Another technical problem to be solved by the present invention is to provide a thin film transistor substrate with improved reliability.

Problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a method of manufacturing a thin film transistor substrate, including a substrate including signal wiring, forming a partition defining a pixel region on the substrate, Applying a color filter to the pixel region partitioned by the substrate; forming a planarization film on the partition including the partition and the color filter; forming a planarization film including a plurality of protrusions disposed on the signal line; Forming a plurality of double column spacers by conformally forming a first light blocking pattern on each protrusion, and forming a second light blocking pattern on a portion of the signal line.

According to an aspect of the present invention, a thin film transistor substrate includes a substrate including signal wiring, a partition wall formed on the substrate to define a pixel area, and the pixel area partitioned by the partition wall. A planarization film formed on the substrate including the color filter, the partition wall, and the color filter, the planarization film including a plurality of protrusions formed on the signal wire, and a plurality of planarization conformally formed on each of the protrusions. A first light shielding pattern forming a double column spacer of a second light shielding pattern, and a second light shielding pattern formed on a portion of the signal line.

Other specific details of the invention are included in the detailed description and drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Thus, in some embodiments, well known process steps, well known device structures and well known techniques are not described in detail in order to avoid obscuring the present invention. Like reference numerals refer to like elements throughout.

The spatially relative terms " below ", " beneath ", " lower ", " above ", " upper " It can be used to easily describe the correlation of an element or components of the element with other elements or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when flipping a device shown in the figure, a device described as "below" or "beneath" of another device may be placed "above" of another device. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in other directions, so that spatially relative terms can be interpreted according to orientation.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, “comprises” and / or “comprising” refers to the presence of one or more other components, steps, operations and / or elements. Or does not exclude additions.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used in a sense that can be commonly understood by those skilled in the art. In addition, the terms defined in the commonly used dictionaries are not ideally or excessively interpreted unless they are specifically defined clearly.

In the present specification, for convenience of description, a thin film transistor substrate including a pixel electrode patterned as a fine electrode and each pixel electrode divided into two sub pixel electrodes will be described as an example. However, the thin film transistor substrate to which the technical idea of the present invention can be applied is not limited thereto, and a thin film having a patterned vertical alignment (PVA) structure having several domain division means in one pixel region or a structure in which the pixel electrode is not patterned. It can also be applied to a transistor substrate and a thin film transistor substrate having a pixel electrode not divided into sub pixel electrodes.

Hereinafter, a thin film transistor substrate according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2. 1 is a layout view of a thin film transistor substrate according to an exemplary embodiment of the present invention. FIG. 2 is a cross-sectional view of the thin film transistor substrate according to the exemplary embodiment, taken along line AA ′ of FIG. 1.

The thin film transistor substrate 1 includes various elements such as a thin film transistor formed on a substrate 10 made of glass or plastic, such as soda lime glass or borosilicate glass.

Signal wirings are formed on the substrate 10. The signal wires may include gate wires 22 and 26 that transmit gate signals, and data wires 62a, 62b, 65a, 65b, 66a, 66b, 67a, and 67b that transmit data signals.

The gate lines 22 and 26 include a gate line 22 extending in one direction, for example, a horizontal direction, and a gate electrode 26 of the thin film transistor protruding from the gate line 22 to form a protrusion. In the present exemplary embodiment, one gate line 22 is formed in one unit pixel region as an example, but two gate lines 22 are disposed in one unit pixel region to provide gate signals to different sub-pixels. May be authorized. In this case, two gate electrodes 26 may be formed in each pixel area to be adjacent to the data lines 62 on both sides of the pixel.

In the present exemplary embodiment, the pixel area may mean a closed area formed by crossing the gate line 22 and the data line 62.

In addition, a storage line (not shown) may be formed on the substrate 10 to transmit a common voltage. The storage line may be formed in a horizontal direction substantially parallel to the gate line 22.

The gate wirings 22 and 26 and the storage wires include aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, copper-based metals such as copper (Cu) and copper alloys, It may be made of molybdenum-based metals such as molybdenum (Mo) and molybdenum alloys, chromium (Cr), titanium (Ti), tantalum (Ta) and the like. In addition, the gate lines 22 and 26 and the storage line may have a multilayer structure including two conductive layers (not shown) having different physical properties. One of the conductive films is made of a low resistivity metal, such as an aluminum-based metal, a silver-based metal, a copper-based metal, or the like, so as to reduce the signal delay or voltage drop of the gate wirings 22 and 26 and the storage line. In contrast, the other conductive layer is made of a material having excellent contact properties with other materials, in particular zinc oxide (ZnO), indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, titanium, tantalum and the like. A good example of such a combination is a chromium bottom film and an aluminum top film, and an aluminum bottom film and a molybdenum top film. However, the present invention is not limited thereto, and the gate lines 22 and 26 and the storage line may be made of various metals and conductors.

A gate insulating film 30 made of silicon oxide (SiOx), silicon nitride (SiNx), or the like is formed on the substrate 10, the gate wirings 22 and 26, and the storage line.

A pair of active layer patterns 40a and 40b made of hydrogenated amorphous silicon, polycrystalline silicon, and the like are formed on the gate insulating film 30. The active layer patterns 40a and 40b may have various shapes, such as island shapes and linear shapes. For example, the active layer patterns 40a and 40b may be linearly formed as in the present embodiment.

On top of each of the active layer patterns 40a and 40b, an ohmic contact layer (not shown) made of a material such as n + hydrogenated amorphous silicon doped with a high concentration of silicide or n-type impurities is formed. Can be. The ohmic contacts are paired and positioned on the active layer patterns 40a and 40b.

Data lines 62a, 62b, 65a, 65b, 66a, 66b, 67a, and 67b may be formed on the ohmic contact layer and the gate insulating layer 30.

The data wires 62a, 62b, 65a, 65b, 66a, 66b, 67a, and 67b include a pair of first and second data lines 62a and 62b and first and second data lines 62a. First and second source electrodes 65a and 65b respectively connected to the second and second source electrodes 65a and 65b, and a pair of first and second drain electrodes 66a and 66b spaced apart from each other, respectively; First and second drain electrode extensions 67a and 67b.

The first and second data lines 62a and 62b mainly extend in the vertical direction, intersect the gate line 22 and the storage line, and transmit a data voltage. The gate line 22 and the first and second data lines 62a and 62b cross each other to define a pixel area.

First and second source electrodes 65a and 65b are formed in the first and second data lines 62a and 62b to extend toward the first and second drain electrodes 66a and 66b, respectively. At the ends of the first and second data lines 62a and 62b, the data line ends (not shown) which receive data signals from another layer or the outside and transmit them to the first and second data lines 62a and 62b, respectively, are provided. Can be formed. The first data line 62a may transmit a data signal to the first pixel electrode 112a, and the second data line 62b may transmit a separate data signal to the second pixel electrode 112b.

The data wires 62a, 62b, 65a, 65b, 66a, 66b, 67a, and 67b are preferably made of refractory metals such as chromium, molybdenum-based metals, tantalum, and titanium, and include an underlayer (not shown) such as a refractory metal. It may have a multi-layer structure consisting of a low resistance material upper layer (not shown) disposed thereon. Examples of the multilayer film structure include a triple film of molybdenum film, aluminum film, and molybdenum film in addition to the above-described double film of chromium lower film and aluminum upper film or aluminum lower film and molybdenum upper film.

The first and second source electrodes 65a and 65b overlap at least a portion of the active layer patterns 40a and 40b, respectively, and the first and second drain electrodes 66a and 66b are gate electrodes 26a and 26b, respectively. The first and second source electrodes 65a and 65b face each other and at least partially overlap the active layer patterns 40a and 40b. Here, the aforementioned ohmic contact layer may include the active layer patterns 40a and 40b thereunder, the first and second source electrodes 65a and 65b and the first and second data lines 62a and 62b thereon. It exists between and lowers contact resistance.

A passivation layer 70 is formed on the first and second data lines 62a and 62b and the drain electrodes 66a and 66b and the exposed active layer patterns 40a and 40b. The protective film may be made of, for example, an inorganic material made of silicon nitride or silicon oxide. The passivation layer 70 protects the exposed portions of the active layer patterns 40a and 40b.

As described above, a pair of data lines 62a and 62b are formed in one pixel area, but the technical concept of the present invention is not limited thereto, and one data line per pixel area ( It may also be applied to the thin film transistor substrate formed.

On the gate lines 22 and 26 and the first and second data lines 62a and 62b, barrier ribs 80a and 80b are formed along the edge of the pixel area to distinguish the color filters 90R, 90B and 90G. The partitions 80a and 80b may be formed on the substrate 10 to define the pixel area. In this case, the partitions 80a and 80b may be formed using an organic film or an inorganic film.

The barrier ribs 80a and 80b are formed along the gate lines 22 and 26 and formed in parallel with the horizontal portions 80a and the first and second data lines 62a and 62b. The vertical portion 80b may include contact holes 106a and 106b formed at positions where the pixel electrodes 112a and 112b and the drain electrodes 66a and 66b are connected to each other. Since the red, green, and blue color filters 90R, 90B, and 90G are disposed in the pixel areas divided by the partitions 80a and 80b, the partitions 80a and 80b are used to separate the color filters 90R, 90B, and 90G. It is desirable to form the material so that the material does not overflow to the adjacent pixel region. At this time, the color filters 90R, 90B, and 90G may be formed by an inkjet method. Further, the color filters 90R, 90B, and 90G may be disposed on the same substrate as the signal wirings.

The color filters 90R, 90B, and 90G serve to pass only light of a specific wavelength band. Each color filter 90R, 90B, and 90G may be arranged in a stripe, mosaic, and delta shape.

The color filters 90R, 90B, 90G may be made of a photosensitive organic material, for example photoresist. These color filters 90R, 90B, and 90G may be formed to have the same thickness as each other or may have a constant step. Each of the color filters 90R, 90B, and 90G may be formed of a red color organic material through which light of a red wavelength passes, a blue color organic material through which light of a blue wavelength passes, and a green color organic material through which light of a green wavelength passes.

Since the color filters 90R, 90B, and 90G do not have great spreadability, they may be formed thick at the center of each pixel area, and may be formed thin at the edge of the pixel area.

The planarization film 100 is formed on the partitions 80a and 80b and the color filters 90R, 90B and 90G. The planarization layer 100 may be an organic layer formed of an organic material having photosensitivity. The planarization film 100 flattens the curvature formed by the barrier ribs 80a and 80b and the color filters 90R, 90B, and 90G, and liquid crystals by organic substances that may flow in the color filters 90R, 90B, and 90G. The pollution of the city can be prevented. In addition, the planarization film 100 may prevent the color filters 90R, 90B, and 90G from lifting.

Contacts 107a and 107b formed through the planarization film 100 and the color filters 90R, 90B, and 90G are formed at positions adjacent to the corners of the pixel region. The contacts 107a and 107b may be formed at one side of lower edges of the pixel area, for example. When two data lines 62a and 62b are formed in one pixel area, two contacts 107a and 107b may be formed on both sides of the lower edge of the pixel area. In this case, the first contact 107a contacts the first drain electrode extension 67a and the first sub pixel electrode 112a, and the second contact 107b contacts the second drain electrode extension 67b and the second. The sub pixel electrode 112b is contacted.

The pixel electrodes 112a and 112b are formed on the planarization film 100. The pixel electrodes 112a and 112b may be made of a transparent conductor such as indium tin oxide (ITO) or indium zinc oxide (IZO) or a reflective conductor such as aluminum.

The pixel electrodes 112a and 112b of the present exemplary embodiment may be divided into first and second sub-pixel electrodes 112a and 112b, and the first and second drain electrode extensions 67a are provided through the contacts 107a and 107b, respectively. And 67b) may be physically and electrically connected to the first and second drain electrodes 66a and 66b to receive different data signals, that is, the first and second data signals, respectively.

The first and second sub pixel electrodes 112a and 112b to which the data voltage is applied are generated between the sub pixel electrodes 112a and 112b and the common electrode by generating an electric field together with a common electrode (not shown) of the upper substrate (not shown). The arrangement of the liquid crystal molecules of the liquid crystal layer of. The first and second sub pixel electrodes 112a and 112b may be driven separately by receiving different data signals, respectively, so that side visibility may be improved.

The first and second sub pixel electrodes 112a and 112b of the present exemplary embodiment may be formed of a plurality of domain groups, respectively. For example, one domain group may be formed on each of the two quadrants that divide the first and second sub pixel electrodes 112a and 112b into two equal parts. In addition, each domain group may be composed of a plurality of domains, for example, one may be formed on each quadrant that divides each domain group into quarters. That is, each of the first and second sub pixel electrodes 112a and 112b may be divided into eight domains, for example. Each domain consists of a plurality of fine electrodes arranged substantially side by side in a constant direction, and the fine slits are disposed between the plurality of fine electrodes. Domains and domain groups adjacent to each other are connected to each other to form one domain group.

The fine electrodes may have a bar shape arranged side by side in a predetermined direction in each domain. The fine electrodes and the fine slits are arranged side by side in a constant direction in one domain, and the arrangement directions of the fine electrodes formed in different domains are different from each other. That is, the arrangement direction of each fine electrode may be substantially 45 °, 135 °, 225 °, 315 ° with respect to the polarization axis of the polarizing plate (not shown) formed on the substrate 10. Such a plurality of fine electrodes may provide a liquid crystal display device having a fast response speed without applying a tilt driving force to the liquid crystal molecules without patterning the common electrode of the upper substrate.

Although not illustrated in the drawings, the liquid crystal display device including the thin film transistor substrate according to the exemplary embodiment of the present invention includes an upper substrate facing the thin film transistor substrate (not shown), and a liquid crystal layer interposed between the thin film transistor substrate and the upper substrate. (Not shown). The upper substrate may include a common electrode (not shown) formed on the insulating layer and an alignment layer (not shown) formed thereon. In addition, polarizers (not shown) may be disposed on outer surfaces of the thin film transistor substrate and the upper substrate.

In addition, the planarization layer 100 may include a plurality of protrusions 101 and 102 formed on the signal wire including the gate wires 22 and 26 and the first and second data lines 62a and 62b. . For example, the planarization film 100 may include first and second protrusions 101 and 102. As shown in the figure, the first protrusion 101 may be larger than the second protrusion 102. Here, the fact that the first protrusion 101 is larger than the second protrusion 102 means that when the lower width of the first protrusion 101 is greater than the lower width of the second protrusion 102, the height of the first protrusion 101 is increased. May be higher than the height of the second protrusion 102 or both of the lower width and the height of the first protrusion 101 are greater than the lower width and the height of the second protrusion 102. The planarization film 100 may include only the first protrusion 101 according to the use of the thin film transistor substrate.

In addition, although the first and second protrusions 101 and 102 are formed on the gate line 22 in the drawing, the number and shape of the protrusions may be variously modified if disposed above the signal line. That is, although one of the first protrusion 101 and the second protrusion 102 is included in one pixel area in the drawing, the first and second protrusions 101 may be formed in each pixel area according to the purpose of the thin film transistor substrate. , 102, or a first protrusion 101 and a second protrusion 102 for a plurality of pixel areas.

The first and second protrusions 101 and 102 may be controlled by the irradiation amount of light during the exposure process for forming the contact holes 106a and 106b in the planarization film 100. More specifically, when the planarization film 100 has, for example, negative photosensitivity, the exposure mask used in the exposure process has a light transmittance of the first region corresponding to the first protrusion 101 and the second protrusion 102. It may be greater than the light transmittance of the first region corresponding to.

The first light blocking patterns 116 and 117 and the second light blocking pattern 115 may be formed on the planarization film 100.

The first light blocking patterns 116 and 117 are formed on the protrusions 101 and 102 of the planarization film 100. More specifically, the first light blocking patterns 116 and 117 may be conformally formed on the first and second protrusions 101 and 102 of the planarization layer 100. In this case, the first and second protrusions 101 and 102 and the first light blocking patterns 116 and 117 formed on the first and second protrusions 101 and 102 may include a plurality of double column spacers 121 and 122. To form. As shown in the figure, the first and second dual column spacers 121 and 122 may have first and second heights h1 and h2 from an upper surface of the thin film transistor substrate. Each of the double column spacers 121 and 122 serves to maintain a cell gap between the upper substrate and the thin film transistor substrate.

As such, the first light blocking pattern is formed by forming the double column spacers 121 and 122 including the first and second protrusions 101 and 102 of the planarization film 100 and the first light blocking patterns 116 and 117. Since the height is higher than that of forming the column spacer with only 116 and 117, the cell gap can be maintained more stably. In addition, a buffering effect may occur because the organic film of the relatively soft planarization film 100 supports the relatively hard first light blocking patterns 116 and 117. Therefore, the compression characteristics of the double column spacers 121 and 122 may be improved.

As described above, the first and second protrusions 101 and 102 may have different sizes, and corresponding first and second double column spacers 121 and 122 may be formed. That is, the first double column spacer 121 may be larger in size than the second double column spacer 122. Accordingly, the first double column spacer 121 serving as the main column spacer mainly maintains the cell gap between the upper substrate and the thin film transistor substrate, and the second double column spacer 122 serves as a sub column spacer. Can be.

Hereinafter, a thin film transistor substrate according to another exemplary embodiment of the present invention will be described with reference to FIG. 3. 3 is a layout view of a thin film transistor substrate according to another exemplary embodiment of the present invention. The thin film transistor substrate 2 according to the exemplary embodiment of the present invention is formed by extending the first light blocking patterns 116 and 117 and the second light blocking pattern 115, according to an exemplary embodiment. It is distinguished from (1). Hereinafter, description will be given based on such distinction points, and for convenience of description, components substantially the same as the above-described embodiments are denoted by the same reference numerals, and description thereof is omitted or simplified.

In the thin film transistor substrate 2 according to another exemplary embodiment of the present invention, the first light blocking patterns 116 and 117 and the second light blocking pattern 115 of the above-described embodiment are integrally formed. That is, the first light blocking patterns 116 and 117 and the second light blocking pattern 115 of the above-described embodiment are formed as one light shielding pattern, and the first and second double column spacers 131 and 132 are one light shielding pattern. The first and second light blocking patterns 115 extend to each other. In other words, the first light blocking patterns 116 and 117 formed on the plurality of protrusions 101 and 102 of the planarization film 100 may be formed by extending the second light blocking pattern 115.

According to the thin film transistor substrate according to another embodiment of the present invention, it is possible to ensure a step between the double column spacer and the top surface of the thin film transistor substrate to form a cell gap than when forming a column spacer using only one film, for example, a light shielding pattern. It has the advantage of being more stable.

Hereinafter, a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 4 to 7. 4 to 7 are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to an embodiment of the present invention. For convenience of explanation, hereinafter, members having the same functions as the members shown in the drawings of the above-described embodiments are denoted by the same reference numerals, and therefore description thereof is omitted or simplified.

First, referring to FIG. 4, gate wirings 22 and 26 and a storage line are formed on a substrate 10, and barrier ribs 80a and 80b defining pixel regions are formed on the substrate 10. For example, a sputtering method may be used to form the gate lines 22 and 26 and the storage line. When etching the gate wirings 22 and 26 and the storage line, wet etching or dry etching may be used. In the case of wet etching, an etchant such as phosphoric acid, nitric acid or acetic acid may be used. In addition, in the case of dry etching, chlorine-based etching gas, for example, Cl ₂ , BCl ₃ and the like can be used.

Subsequently, a gate insulating film 30 is formed on the substrate 10, the gate wirings 22 and 26, and the storage line. The gate insulating layer 30 may be formed using plasma enhanced chemical vapor deposition (PECVD), reactive sputtering, or the like.

Subsequently, a hydrogenated amorphous silicon layer, an n + hydrogenated amorphous silicon layer heavily doped with n-type impurities, and a conductive material for data wiring are sequentially formed and patterned on the gate insulating film 30 to form the data wirings 62a, 62b, 65a, 65b, 66a, 66b, 67a, 67b, resistive contact layer, and active layer patterns 40a, 40b. The data lines 62a and 62b together with the gate line 22 define a pixel region.

Subsequently, a protective film (e.g., plasma enhanced chemical vapor deposition (PECVD)) is formed on the data lines 62a, 62b, 65a, 65b, 66a, 66b, 67a, and 67b and the gate insulating film 30, for example. 70).

Subsequently, barrier ribs 80a and 80b are formed along the edge of the pixel. In this case, the barrier ribs 80a and 80b are deposited on the substrate 10 using an organic material or an inorganic material, and are formed by patterning an organic or inorganic material layer.

The partition walls 80a and 80b are formed on the gate partition walls 80a on the gate wirings 22 and 26 and on the data lines and the first data lines 62a and the second intersecting the gate partition walls 80a. The method may include forming the data partition wall 80b on the data line 62b.

Subsequently, referring to FIG. 5, color organic materials are sprayed by an inkjet method to form color filters 90R, 90B, and 90G. In this case, the color organic material may be disposed in each pixel area surrounded by the barrier ribs 80a and 80b to cover the entire pixel area.

In more detail, a method of forming a color organic material using an inkjet method, for example, a red color is formed in a pixel area surrounded by barrier ribs 80a and 80b while moving an inkjet printing apparatus (not shown) in a predetermined direction from an upper portion of the pixel area. The color organic material is sprayed and filled, and adjusted to be sprayed on one pixel area per three pixel areas in a moving direction. Then, green and blue color organic materials are sprayed on the remaining pixel areas in the same manner. If the inkjet printing apparatus is able to spray all three color organic materials, the inkjet printing apparatus may move over the pixel region while alternately spraying.

The sprayed color organic material is made of a viscous liquid material and arranged to have a step in each pixel area. That is, the thickness of the color organic material may be thinner at the edge of each pixel area than at the center portion thereof. The inkjet method can eliminate the patterning process when forming the color filters 90R, 90B, and 90G, thereby shortening the process time.

Subsequently, the liquid color organic material filled in the entire pixel region may be dried and cured. As a method of drying and hardening, heat processing or ultraviolet irradiation can be performed.

Next, referring to FIG. 6, the planarizing film organic film 100a covering the partition walls 80a and 80b and the color filters 90R, 90B and 90G is formed. The planarization film 100 of the present embodiment may be formed of a photosensitive organic material. More specifically, it may be a negative photosensitive organic material.

Next, referring to FIG. 7, a portion of the planarization organic film 100a is removed to form a planarization film 100 including a plurality of protrusions 101 and 102. More specifically, the planarization film 100 including the plurality of protrusions 101 and 102 is formed using the exposure mask 300 including the first region 311 corresponding to the plurality of protrusions 101 and 102. can do. In this case, the planarization film 100 may further include a plurality of contact holes 106a and 106b disposed on the signal wires, and the exposure mask 300 may include second contacts corresponding to the respective contact holes 106a and 106b. Region 320 may include.

In other words, the exposure mask 300 may include the first regions 311 and 312 corresponding to the first and second protrusions, the second regions 320 corresponding to the plurality of contact holes 106a and 106b, and The third region 330 may be included. For example, when the planarization organic film 100a is a negative photosensitive organic film, the light transmittance of the first regions 311 and 312 of the exposure mask 300 is greater than that of the third region 320, and the second region 320 is formed. ) May have a light transmittance smaller than that of the third region 330. More specifically, the first regions 311 and 312 of the exposure mask 300 may be a battle and region, the second region 320 may be a light shielding region, and the third region 330 may be a transflective region.

When the planarization organic film 100a, which is a negative photosensitive organic film, is exposed using the exposure mask 300, and the planarization organic film 100a is developed, a plurality of contact holes 106a and 106b and a plurality of contact holes are formed according to the exposure degree. The planarization film 100 including the protrusions 101 and 102 of is formed.

Referring to FIG. 1 again, a transparent electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO) or a reflective conductor such as aluminum is deposited and patterned on the color filters 90R, 90B, and 90G. And form 112a and 112b. The pixel electrodes 112a and 112b may be divided into first and second sub pixel electrodes 112a and 112b, and the first and second drain electrode extensions 67a and 67b are provided through the contacts 107a and 107b, respectively. Can be connected physically and electrically.

Subsequently, the first light blocking patterns 116 and 117 are conformally formed on the plurality of protrusions 101 and 102, and the second light blocking pattern 115 is formed on a portion of the signal wiring.

Although not shown in the drawings, a light blocking material layer is formed on the planarization film 100 including the plurality of contact holes 106a and 106b and the plurality of protrusions 101 and 102, and the plurality of contact holes 106a and 106b. And a portion of the light blocking material layer may be removed by using an exposure mask including a first region corresponding to the plurality of protrusions 101 and 102 and other second regions. Therefore, the first and second light blocking patterns 115 may be formed at the same time. Furthermore, by forming the first light blocking patterns 116 and 117, the double column spacers 121 and 122 including the plurality of protrusions 101 and 102 and the first light blocking patterns 116 and 117 may be formed. . That is, the double column spacers 121 and 122 may include a plurality of protrusions 101 and 102, which are part of the planarization film 100 made of an organic material, and first light blocking patterns 116 and 117 made of an organic material including carbon. It may be formed to include.

According to the method of manufacturing the thin film transistor substrate according to the exemplary embodiment of the present invention, the column spacer may be formed as a double layer to maintain the sal gap between the thin film transistor substrate and the upper substrate more stably.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

1 is a layout view of a thin film transistor substrate according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor substrate according to the exemplary embodiment, taken along line AA ′ of FIG. 1.

3 is a layout view of a thin film transistor substrate according to another exemplary embodiment of the present invention.

4 to 7 are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to an embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

10: substrate 22: gate line

26 gate electrode 30 gate insulating film

40a, 40b: active layer pattern 62a, 62b: data line

65a, 65b: source electrode 66a, 66b: drain electrode

67a and 67b: drain electrode extension 70: protective film

80a, 80b: bulkhead 90R, 90G, 90B: color filter

100: planarization film 106a, 106b: contact hole

107a and 107b: contacts 112a and 112b: pixel electrodes

115, 116, 117: shading pattern

121, 122, 131, 132: double column spacer

Claims (12)

Providing a substrate including signal wiring, Forming a partition wall defining a pixel region on the substrate, Applying a color filter to the pixel region partitioned by the partition wall, Forming a planarization film on the substrate including the barrier rib and the color filter, and forming a planarization film including a plurality of protrusions disposed on the signal line, Forming a plurality of double column spacers by conformally forming a first light shielding pattern on each of the protrusions, And forming a second light blocking pattern on a portion of the signal wiring. The method of claim 1, wherein the planarization film including a plurality of protrusions is formed on the signal wire. Forming an organic film for a planarization film on the substrate including the barrier rib and the color filter; And forming a planarization film including each of the protrusions by removing a portion of the organic film for the planarization film using an exposure mask including a first region corresponding to each of the protrusions. The method of claim 2, The exposure mask includes a second region corresponding to a plurality of contacts disposed on the signal line, and a third region except for the first and second regions, The first region has a light transmittance greater than the third region, and the second region has a light transmittance smaller than the third region. The method of claim 3, And the first region is a battle region, the second region is a light shielding region, and the third region is a transflective region. The method of claim 1, wherein applying the color filter, A method of manufacturing a thin film transistor substrate comprising using an inkjet method. The method of claim 5, wherein applying the color filter, The thin film transistor substrate manufacturing method including forming on the same board | substrate as the said signal wiring. According to claim 1, Forming the first light blocking pattern and the second light blocking pattern, Forming a light blocking material layer on the planarization layer, And removing a portion of the light blocking material layer by using an exposure mask including a first region corresponding to each of the protrusions and a part of the signal wiring, and another second region. The method of claim 7, wherein the first light shielding pattern, The second light blocking pattern is formed to extend the manufacturing method of the thin film transistor substrate. A substrate including signal wiring; Barrier ribs formed on the substrate to define pixel regions; A color filter formed in the pixel region partitioned by the partition wall; A planarization film formed on the substrate including the barrier rib and the color filter, the planarization film including a plurality of protrusions formed on the signal wire; A first light blocking pattern conformally formed on each of the protrusions to form a plurality of double column spacers; And And a second light blocking pattern formed on a portion of the signal line. The method of claim 9, And the planarization film is an organic film. The method of claim 9, And the signal line and the color filter are disposed on the same substrate. The method of claim 9, wherein the first light shielding pattern, The thin film transistor substrate formed by extending the second light blocking pattern.

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