KR20100060502A - Method of fabricating oxide thin film transistor - Google Patents

Abstract

PURPOSE: A manufacturing method of an oxide thin film transistor which is applied to the excellent uniformity to a large-scaled display is provided to improve the uniformity by using an amorphous ZnO based TFT as an active layer. CONSTITUTION: An active layer(224) is formed on a substrate(210). A gate electrode is formed on the channel region of the active layer. A second insulating layer is formed on the gate electrode. Source/drain electrodes are electrically connected through the first and the second contact hole in source/drain region of the active layer. The third dielectric polish layer is formed on the source/drain electrode. A pixel electrode is electrically connected through the third contact hole.

Description

Manufacturing Method of Oxide Thin Film Transistor {METHOD OF FABRICATING OXIDE THIN FILM TRANSISTOR}

The present invention relates to a method for manufacturing an oxide thin film transistor, and more particularly, to a method for manufacturing an oxide thin film transistor using an amorphous zinc oxide semiconductor as an active layer.

In particular, the present invention relates to a method of manufacturing an oxide thin film transistor in which an oxide thin film transistor having a coplanar structure is reduced in number of masks to simplify the manufacturing process and reduce manufacturing costs.

Recently, with increasing interest in information display and increasing demand for using a portable information carrier, a lightweight flat panel display (FPD), which replaces a conventional display device, a cathode ray tube (CRT), is used. The research and commercialization of Korea is focused on. In particular, the liquid crystal display (LCD) of the flat panel display device is an image representing the image using the optical anisotropy of the liquid crystal, is excellent in resolution, color display and image quality, and is actively applied to notebooks or desktop monitors have.

The liquid crystal display is largely composed of a color filter substrate and an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

The active matrix (AM) method, which is a driving method mainly used in the liquid crystal display device, uses an amorphous silicon thin film transistor (a-Si TFT) as a switching device to drive the liquid crystal in the pixel portion. to be.

Hereinafter, a structure of a general liquid crystal display device will be described in detail with reference to FIG. 1.

1 is an exploded perspective view schematically illustrating a general liquid crystal display.

As shown in the figure, the liquid crystal display device is largely a liquid crystal layer (liquid crystal layer) formed between the color filter substrate 5 and the array substrate 10 and the color filter substrate 5 and the array substrate 10 ( 30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 for implementing colors of red (R), green (G), and blue (B); A black matrix 6 that separates the sub-color filters 7 and blocks light passing through the liquid crystal layer 30, and a transparent common electrode that applies a voltage to the liquid crystal layer 30. 8)

In addition, the array substrate 10 may be arranged in a vertical direction to form a plurality of gate lines 16 and data lines 17 defining a plurality of pixel regions P, and the gate lines 16 and data lines 17. And a pixel electrode 18 formed on the pixel region P.

The color filter substrate 5 and the array substrate 10 are joined to face each other by a sealant (not shown) formed on the outer side of the image display area to form a liquid crystal display panel, and the color filter substrate 5 And the bonding of the array substrate 10 is made through a bonding key (not shown) formed in the color filter substrate 5 or the array substrate 10.

On the other hand, the above-mentioned liquid crystal display device has been the most attracting display device until now because of the light weight and low power consumption, but the liquid crystal display device is not a light emitting device but a light receiving device and because of the technical limitations such as brightness, contrast ratio and viewing angle, Development of new display devices that can overcome the disadvantages is actively being developed.

Organic Light Emitting Diode (OLED), one of the new flat panel displays, is self-luminous, so it has better viewing angle and contrast ratio than liquid crystal displays, and it is lightweight because it does not require backlight. It is also advantageous in terms of power consumption. In addition, there is an advantage that the DC low-voltage drive is possible and the response speed is fast, in particular, it has an advantage in terms of manufacturing cost.

Recently, studies on the large area of the organic light emitting display have been actively conducted, and in order to achieve this, there is a demand for developing a transistor having stable operation and durability by securing a constant current characteristic as a driving transistor of the organic light emitting display.

Amorphous silicon thin film transistors used in the liquid crystal display described above can be fabricated in low temperature processes, but have very low mobility and do not satisfy the constant current bias conditions. Polycrystalline silicon thin film transistors, on the other hand, have high mobility and satisfactory constant current test conditions, and are difficult to obtain uniform characteristics, making it difficult to large area and require high temperature processes.

The present invention has been made to solve the above problems, and an object thereof is to provide a method of manufacturing an oxide thin film transistor using an amorphous zinc oxide semiconductor as an active layer.

Another object of the present invention is to provide a method of manufacturing an oxide thin film transistor to prevent denaturation of the amorphous zinc oxide semiconductor generated during source / drain electrode etching by applying a coplanar structure.

It is still another object of the present invention to provide a method of manufacturing an oxide thin film transistor in which the oxide thin film transistor having the coplanar structure is manufactured by four mask processes.

Other objects and features of the present invention will be described in the configuration and claims of the invention described below.

In order to achieve the above object, the method of manufacturing an oxide thin film transistor of the present invention forms an active layer made of an amorphous zinc oxide-based semiconductor on a substrate using a diffraction mask having a diffraction pattern applied to a source / drain region of the active layer. Forming a gate electrode on the channel region of the active layer with a first insulating film interposed therebetween; Forming a second insulating film on the substrate on which the gate electrode is formed; Removing portions of the second insulating layer to form first and second contact holes exposing portions of the source / drain regions of the active layer; Forming a source / drain electrode electrically connected to the source / drain regions of the active layer through the first and second contact holes; Forming a third insulating film on the substrate on which the source / drain electrodes are formed; Removing a portion of the third insulating layer to form a third contact hole exposing a portion of the drain electrode; And forming a pixel electrode electrically connected to the drain electrode through the third contact hole.

Another method of manufacturing an oxide thin film transistor of the present invention forms an active layer of amorphous zinc oxide semiconductor on a substrate by using a diffraction mask having a diffraction pattern applied to a channel region of an active layer, and simultaneously forms a source / drain region of the active layer. Forming a source / drain electrode to be electrically connected; Forming a first insulating film on the substrate on which the source / drain electrodes are formed; Forming a gate electrode on the substrate on which the first insulating film is formed; Forming a second insulating film on the substrate on which the gate electrode is formed; Removing a portion of the first insulating layer and the second insulating layer to form a contact hole exposing a portion of the drain electrode; And forming a pixel electrode electrically connected to the drain electrode through the contact hole.

As described above, the method of manufacturing the oxide thin film transistor according to the present invention is excellent in uniformity by using an amorphous zinc oxide-based semiconductor as an active layer provides an effect applicable to large area display.

In addition, the method of manufacturing the oxide thin film transistor according to the present invention does not damage the oxide semiconductor during the source / drain electrode etching by applying the coplanar structure provides an effect that can secure excellent device characteristics.

In addition, the manufacturing method of the oxide thin film transistor according to the present invention provides the effect of reducing the manufacturing process and cost by forming a high-performance thin film transistor through a minimum mask process without the doping process while applying the coplanar structure.

In addition, the oxide thin film transistor according to the present invention has the advantage of being able to prevent the leakage current of the thin film transistor due to external light in the application of the reflective electrophoretic display device having a top gate form.

Hereinafter, exemplary embodiments of a method of manufacturing an oxide thin film transistor according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view schematically illustrating a structure of an oxide thin film transistor according to a first embodiment of the present invention, and schematically illustrates a structure of an oxide thin film transistor using an amorphous zinc oxide based semiconductor as an active layer.

In this case, the oxide thin film transistor according to the first embodiment has a coplanar structure in which a gate electrode and a source / drain electrode are positioned on an active layer.

As shown in the figure, the oxide thin film transistor according to the first embodiment of the present invention is a buffer layer 111 formed on a predetermined substrate 110, an active layer formed of an amorphous zinc oxide-based semiconductor on the buffer layer 111 layer 124, a gate electrode 121 formed on the active layer 124 with the first insulating layer 115a therebetween, and a source / drain region of the active layer 124 formed on the gate electrode 121. A second insulating film 115b to be exposed, source / drain electrodes 122 and 123 electrically connected to the source / drain regions of the exposed active layer 124, and source / drain electrodes 122 and 123. And a third insulating film 115c exposing a part of the drain electrode 123 and a pixel electrode 118 electrically connected to the exposed drain electrode 123.

In this case, the oxide thin film transistor according to the first embodiment of the present invention satisfies high mobility and constant current test conditions while ensuring uniform characteristics as the active layer 124 is formed using an amorphous zinc oxide semiconductor. It has the advantage of being applicable to area display.

The zinc oxide (ZnO) is a material capable of realizing all three properties of conductivity, semiconductivity, and resistance according to oxygen content. An oxide thin film transistor using an amorphous zinc oxide semiconductor material as an active layer is a liquid crystal display and an organic field. It can be applied to large area displays including light emitting displays.

In addition, a tremendous interest and activity has recently been focused on transparent electronic circuits, and oxide thin film transistors using the amorphous zinc oxide-based semiconductor materials as active layers have high mobility and can be manufactured at low temperatures, thereby making it possible to manufacture the transparent electronic circuits. There is an advantage that can be used.

In particular, the oxide thin film transistor according to the first embodiment of the present invention is characterized in that the active layer is formed of an a-IGZO semiconductor containing heavy metals such as indium (In) and gallium (Ga) in the ZnO. do.

The a-IGZO semiconductor is transparent because it can pass visible light, and the oxide thin film transistor made of the a-IGZO semiconductor has a mobility of 1 to 100 cm ² / Vs, which is higher than that of an amorphous silicon thin film transistor. Indicates.

In addition, the a-IGZO semiconductor has a wide band gap and can manufacture UV light emitting diodes (LEDs), white LEDs and other components having high color purity, and can be processed at low temperatures to provide a light and flexible product. It has the features to produce.

Furthermore, since the oxide thin film transistor made of the a-IGZO semiconductor exhibits uniform characteristics similar to that of the amorphous silicon thin film transistor, the component structure is as simple as that of the amorphous silicon thin film transistor and has an advantage that it can be applied to a large area display.

In the oxide thin film transistor according to the first exemplary embodiment of the present invention having the above characteristics, a channel of the oxide semiconductor when the source / drain electrodes are etched by applying a coplanar structure in which the gate electrode and the source / drain electrodes are positioned on the active layer. It does not damage the layer and has the characteristics of ensuring excellent device characteristics.

In addition, the oxide thin film transistor according to the first embodiment of the present invention after depositing the oxide semiconductor, the insulating film and the first conductive film in succession, and includes a diffraction mask (hereinafter referred to as a diffraction mask) includes a half-tone mask By simultaneously patterning the active layer and the gate electrode, the number of masks can be reduced to reduce the manufacturing process and cost, which will be described in detail through the following method of manufacturing the oxide thin film transistor.

Furthermore, the oxide thin film transistor according to the first embodiment of the present invention performs the same process as the existing coplanar structure, while the oxide semiconductor does not need a buffer layer and an n + layer, and thus does not require a doping process and an activation process. It offers the advantage of simplifying the process.

3A to 3E are cross-sectional views sequentially illustrating a manufacturing process of an oxide thin film transistor according to a first embodiment of the present invention shown in FIG.

As shown in FIG. 3A, a buffer layer 111 is formed on a substrate 110 made of a transparent insulating material.

In this case, the buffer layer 111 serves to block impurities such as sodium (natrium) in the substrate 110 from penetrating into the upper layer during the process. As the layer is formed, the buffer layer 111 may be removed.

Next, an oxide semiconductor, an insulating film, and a first conductive film are deposited on the substrate 110 on which the buffer layer 111 is formed, and then selectively patterned through a photolithography process (first mask process) to form an active layer made of the oxide semiconductor. A gate electrode 121 made of 124 and the first conductive film is formed at the same time.

In this case, the gate electrode 121 is formed on the active layer 124 with the first insulating film 115a formed between the insulating layers therebetween, and the active layer 124 and the gate electrode 121 are formed in the present invention. By using the diffraction mask according to the first embodiment of the can be formed through a single mask process, which will be described in detail with reference to the drawings.

4A to 4F are cross-sectional views illustrating in detail the first mask process illustrated in FIG. 3A.

As shown in FIG. 4A, an amorphous zinc oxide semiconductor layer 120 is deposited on the entire surface of the substrate 110 on which the buffer layer 111 is formed to form a predetermined amorphous zinc oxide semiconductor layer 120, and the insulating layer 115 is formed thereon. ) And the first conductive film 130 are formed.

At this time, the amorphous zinc oxide-based composite semiconductor, in particular a-IGZO semiconductor sputtering method using a composite target of gallium oxide (Ga ₂ O ₃ ), indium oxide (In ₂ O ₃ ) and zinc oxide (ZnO) It may be formed by, and in addition to this, it is also possible to use a chemical vapor deposition method such as chemical vapor deposition or atomic layer deposition (ALD).

Here, in the case of the first embodiment of the present invention using a composite oxide target having an atomic ratio of gallium, indium and zinc of 1: 1: 1, 2: 2: 1, 3: 2: 1 and 4: 2: 1, respectively An amorphous zinc oxide-based semiconductor layer 120 may be formed, and in the case of using a composite oxide target having an atomic ratio of 2: 2: 1 of gallium, indium, and zinc, an equivalent weight of gallium, indium, and zinc (equivalent weight) Ratio is approximately 2.8: 2.8: 1.

In addition, the amorphous zinc oxide-based composite semiconductor applied to the oxide thin film transistor according to the first embodiment of the present invention can be deposited at a low temperature, so that a substrate 110 applicable to a low temperature process such as a plastic substrate or soda lime glass may be used. Can be. In addition, because of the amorphous properties, it is possible to use the large-area display substrate 110.

In addition, the insulating layer 115 may be formed of an inorganic insulating film such as silicon nitride film (SiNx) or silicon oxide film (SiO ₂ ), or a highly dielectric oxide film such as hafnium (Hf) oxide or aluminum oxide. In this case, for example, when the silicon oxide film is applied to the insulating layer 115, the silicon oxide film may be formed to have a thickness of about 300 to 1000 μs, and dry etching may be used for the etching.

In this case, the insulating layer 115 may be formed by Chemical Vapor Deposition (CVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD).

The first conductive layer 130 may include aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), nickel (Ni), and chromium (chromium). Low resistance opaque conductive materials such as Cr), molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta), and the like may be used. In addition, the first conductive layer 130 may use an opaque conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). It is also possible to form a multilayered structure in which two or more of these are stacked.

And, as shown in Figure 4b, after forming a photosensitive film 170 made of a photosensitive material such as photoresist on the entire surface of the substrate 110, the photosensitive film through the diffraction mask 160 of the first embodiment of the present invention Light is selectively irradiated to 170.

In this case, the diffraction mask 160 is applied with a first transmission region (I) for transmitting all of the irradiated light and a diffraction pattern (in this case, a half-tone pattern when a half-tone mask is applied) to transmit only a part of the light. A part is provided with a second transmission region II for blocking and a blocking region III for blocking all the irradiated light, and only the light transmitted through the diffraction mask 160 is irradiated to the photosensitive film 170.

Subsequently, after the photoresist film 170 exposed through the diffraction mask 160 is developed, as shown in FIG. 4C, all of the light is blocked through the blocking region III and the second transmission region II. The first photoresist pattern 170a to the third photoresist pattern 170c having a predetermined thickness remain in the partially blocked region, and the photoresist is completely removed in the first transmission region I through which all light is transmitted. The surface of the conductive film 130 is exposed.

In this case, the first photoresist pattern 170a formed in the blocking region III is thicker than the second photoresist pattern 170b and the third photoresist pattern 170c formed through the second transmission region II. In addition, the photosensitive film is completely removed in a region where all the light is transmitted through the first transmission region I. This is because the photoresist of the positive type is used, and the present invention is not limited thereto. You can also use.

In particular, in the case of the first embodiment of the present invention, the second transmission region (II) of the diffraction mask according to the first embodiment of the present invention is applied to the source region and the drain region of the active layer to be patterned later. The blocking region III is applied to a channel region, that is, a gate electrode region.

Next, as shown in FIG. 4D, the amorphous zinc oxide semiconductor layer, the insulating layer, and the first photosensitive film pattern 170a to third photosensitive film pattern 170c formed as described above are used as a mask. When the one conductive film is selectively removed, the active layer 124 made of the amorphous zinc oxide semiconductor is formed on the substrate 110. In this case, the insulating layer and the first conductive layer are formed on the active layer 124 and patterned substantially the same as the active layer 124 and the first conductive layer pattern 130. ') Is formed.

Subsequently, when an ashing process of removing a portion of the first photoresist pattern 170a to the third photoresist pattern 170c is performed, as illustrated in FIG. 4E, the second transmission region II may be formed. The second photoresist pattern and the third photoresist pattern are completely removed.

In this case, the first photoresist pattern may be the fourth photoresist pattern 170a ′ removed by the thickness of the second photoresist pattern and the third photoresist pattern, and thus remain only in the gate electrode region corresponding to the blocking region III.

Subsequently, as shown in FIG. 4F, the insulating layer pattern and the first conductive layer pattern are partially removed by using the remaining fourth photoresist layer pattern 170a ′ as a mask to insulate the insulating layer from the substrate 110. A first insulating film 115a made of a layer and a gate electrode 121 made of the first conductive film are formed.

As described above, in the case of the first embodiment of the present invention, the active layer and the gate electrode are formed through one mask process using a diffraction mask having a diffraction pattern applied to the source / drain regions, thereby reducing the manufacturing process and cost. .

3B, a second insulating film 115b is formed on the entire surface of the substrate 110 to cover the gate electrode 121, and then a photolithography process (second mask process) is used. By selectively patterning, the first contact hole 140a and the second contact hole 140b exposing portions of the source region and the drain region of the active layer 124 are formed.

3C, a second conductive film is formed over the entire surface of the substrate 110 on which the second insulating film 115b is formed.

In this case, the second conductive layer may use a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, nickel, chromium, molybdenum, titanium, platinum, tantalum, etc. to form a source electrode and a drain electrode. In addition, an opaque conductive material such as indium tin oxide or indium zinc oxide may be used as the second conductive layer, and the second conductive layer may have a multilayer structure in which two or more conductive materials are stacked.

Here, a conductive material such as molybdenum or a molybdenum alloy may be directly applied to the second conductive film, and a low resistance conductive material such as aluminum or copper may be applied after hydrogen or argon plasma treatment.

The source region of the active layer 124 is selectively formed through the first contact hole 140a and the second contact hole 140b by selectively patterning the second conductive layer through a photolithography process (third mask process). And a source electrode 122 and a drain electrode 123 electrically connected to the drain region.

Next, as shown in FIG. 3D, a third insulating film 115c is deposited on the entire surface of the substrate 110 on which the source electrode 122 and the drain electrode 123 are formed, and then a photolithography process (fourth mask process). A portion of the third insulating layer 115c is removed to form a third contact hole 140c exposing a portion of the drain electrode 123.

As shown in FIG. 3E, the transparent conductive film is deposited on the entire surface of the substrate 110 and then selectively patterned using a photolithography process (a fifth mask process) to pass through the third contact hole 140c. The pixel electrode 118 electrically connected to the drain electrode 123 is formed.

On the other hand, the oxide thin film transistor according to the first embodiment of the present invention described above is to produce a thin film transistor through a mask process of five times the coplanar structure, the top of which the gate electrode is located on the top layer while applying the coplanar structure An oxide thin film transistor and a method of manufacturing the same according to a second embodiment of the present invention, which can manufacture a thin film transistor using only four mask processes using a gate structure, will be described in detail with reference to the accompanying drawings.

5 is a cross-sectional view schematically illustrating a structure of an oxide thin film transistor according to a second exemplary embodiment of the present invention.

In this case, the oxide thin film transistor according to the second embodiment has a coplanar structure in which a gate electrode and a source / drain electrode are positioned on the active layer, while the gate electrode has a top gate structure positioned above the source / drain electrode. It is characterized by.

As shown in the figure, the oxide thin film transistor according to the second embodiment of the present invention is a buffer layer 211 formed on a predetermined substrate 210, an active layer formed of an amorphous zinc oxide-based semiconductor on the buffer layer 211 layer ( 224, the source / drain electrodes 222 and 223 formed on the active layer 224 and electrically connected to the source / drain regions of the active layer 224, and the first insulating layer 215a therebetween. A gate electrode 221 formed on the drain electrodes 222 and 223, a second insulating layer 215b formed on the gate electrode 221, and exposing the drain electrode 223, and the exposed drain electrode 223. The pixel electrode 218 is electrically connected.

In this case, the oxide thin film transistor according to the second embodiment of the present invention is the same as the first embodiment of the present invention as described above to form the active layer 224 using an amorphous zinc oxide-based semiconductor, high mobility and constant current test It satisfies the conditions and secures uniform characteristics, which has the advantage of being applicable to large area displays.

In particular, the oxide thin film transistor according to the second embodiment of the present invention is characterized in that the active layer 224 is formed of an a-IGZO semiconductor in which ZnO contains heavy metals such as indium and gallium.

In addition, the oxide thin film transistor according to the second embodiment of the present invention can adjust the carrier concentration of the active layer 224 by adjusting the oxygen concentration in the reaction gas in the sputtering, it is possible to adjust the device characteristics of the thin film transistor It is done.

In the oxide thin film transistor according to the second embodiment of the present invention having the above characteristics, the oxide semiconductor and the first conductive film are sequentially deposited, and then the active layer and the source / drain electrodes are patterned simultaneously using a diffraction mask. A thin film transistor can be manufactured by a mask process, which will be described in detail through the following method of manufacturing an oxide thin film transistor.

Furthermore, the oxide thin film transistor according to the second embodiment of the present invention performs the same process as the existing top gate structure, while the oxide semiconductor does not need a buffer layer and an n + layer, and thus does not require a doping process and an activation process. It offers the advantage of simplifying the process.

6A through 6D are cross-sectional views sequentially illustrating a manufacturing process of an oxide thin film transistor according to a second exemplary embodiment of the present invention illustrated in FIG. 5.

As shown in FIG. 6A, a buffer layer 211 is formed on a substrate 210 made of a transparent insulating material.

In this case, as described above, the buffer layer 211 may not be formed as the active layer is formed using the oxide semiconductor.

Next, an oxide semiconductor and a first conductive film are deposited on the substrate 210 on which the buffer layer 211 is formed, and then selectively patterned through a photolithography process (first mask process) to form an active layer made of the oxide semiconductor ( Source / drain electrodes 222 and 223 formed of 224 and the first conductive film are formed at the same time.

In this case, the active layer 224 and the source / drain electrodes 222 and 223 may be formed through one mask process by using a diffraction mask according to the second embodiment of the present invention. It explains in detail.

7A to 7F are cross-sectional views illustrating in detail the first mask process illustrated in FIG. 6A.

As shown in FIG. 7A, a predetermined amorphous zinc oxide based semiconductor layer 220 and a first conductive layer 230 made of an amorphous zinc oxide based semiconductor are formed on the entire surface of the substrate 210 on which the buffer layer 211 is formed. .

In this case, the amorphous zinc oxide-based composite semiconductor, especially a-IGZO semiconductor is formed by a sputtering method using a composite target of gallium oxide (Ga ₂ O ₃ ), indium oxide (In ₂ O ₃ ) and zinc oxide (ZnO). In addition, it is also possible to use a chemical vapor deposition method such as chemical vapor deposition or atomic deposition.

Here, in the second embodiment of the present invention, the composite oxide targets having an atomic ratio of gallium, indium, and zinc of 1: 1: 1, 2: 2: 1, 3: 2: 1, and 4: 2: 1 are used, respectively. An amorphous zinc oxide semiconductor layer 220 may be formed, and in this case, when using a composite oxide target having an atomic ratio of gallium, indium and zinc of 2: 2: 1, an equivalent weight of gallium, indium and zinc The ratio is characterized by having approximately 2.8: 2.8: 1.

In addition, the amorphous zinc oxide-based composite semiconductor applied to the oxide thin film transistor according to the second embodiment of the present invention can be deposited at a low temperature, so that a substrate 210 that can be applied to a low temperature process such as a plastic substrate or soda lime glass may be used. Can be. In addition, because of the amorphous properties, it is possible to use a large-area display substrate 210.

The first conductive layer 230 may include aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), nickel (Ni), and chromium (chromium). Low resistance opaque conductive materials such as Cr), molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta), and the like may be used. In addition, the first conductive layer 230 may use an opaque conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), and the conductive material. It is also possible to form a multilayered structure in which two or more of these are stacked.

As shown in FIG. 7B, after the photoresist layer 270 formed of photosensitive material such as photoresist is formed on the entire surface of the substrate 210, the photoresist layer is formed through the diffraction mask 260 of the second embodiment of the present invention. 270 is selectively irradiated with light.

At this time, the diffraction mask 260 is applied to the first transmission region (I) and the diffraction pattern (in this case, half-tone pattern in case of applying a half-tone mask) to transmit all the irradiated light to transmit only a part of the light A part is provided with a second transmission region II for blocking and a blocking region III for blocking all irradiated light, and only the light transmitted through the diffraction mask 260 is irradiated to the photosensitive film 270.

Subsequently, after the photosensitive film 270 exposed through the diffraction mask 260 is developed, as shown in FIG. 7C, all of the light is blocked through the blocking region III and the second transmission region II. The first photoresist pattern 270a to the third photoresist pattern 270c having a predetermined thickness remain in the partially blocked region, and the photoresist is completely removed in the first transmission region I through which all light is transmitted. The surface of the conductive film 230 is exposed.

In this case, the first photoresist layer pattern 270a and the second photoresist layer pattern 270b formed in the blocking region III are formed thicker than the third photoresist layer pattern 270c formed through the second transmission region II. In addition, the photosensitive film is completely removed in a region where all the light is transmitted through the first transmission region I. This is because the photoresist of the positive type is used, and the present invention is not limited thereto. May be used.

In particular, in the case of the second embodiment of the present invention, unlike the case of the first embodiment described above, the second transmission region II of the diffraction mask according to the second embodiment of the present invention is formed in the channel region of the active layer to be patterned. The blocking region III is applied to the source / drain electrode region.

Next, as shown in FIG. 7D, the amorphous zinc oxide semiconductor layer and the first conductive film formed below the first photoresist pattern 270a to the third photoresist pattern 270c formed as a mask are used as a mask. If selectively removed, an active layer 224 made of the amorphous zinc oxide semiconductor is formed on the substrate 210. In this case, a first conductive layer pattern 230 ′ formed of the first conductive layer and patterned substantially the same as the active layer 224 is formed on the active layer 224.

Subsequently, when the ashing process of removing a portion of the first photoresist pattern 270a to the third photoresist pattern 270c is performed, as illustrated in FIG. 7E, the third photoresist layer of the second transmission region II is formed. The pattern will be completely removed.

In this case, the first photoresist pattern and the second photoresist pattern correspond to the blocking region III by the fourth photoresist pattern 270a 'and the fifth photoresist pattern 270b' where the thickness of the third photoresist pattern is removed. Only the source / drain electrode region remains.

Subsequently, as shown in FIG. 7F, a portion of the first conductive film pattern is selectively removed by using the remaining fourth photoresist pattern 270a 'and the fifth photoresist pattern 270b' as a mask. Source / drain electrodes 222 and 223 formed of the first conductive layer are formed on the 210.

As described above, in the second embodiment of the present invention, an active layer and a source / drain electrode are formed by using a diffraction mask having a diffraction pattern applied to the channel region of the active layer through a single mask process, thereby reducing manufacturing process and cost. To provide.

Next, as shown in FIG. 6B, a first insulating film 215a and a second conductive film are formed on the entire surface of the substrate 210 to cover the source / drain electrodes 222 and 223, and then a photolithography process ( By selectively patterning using a second mask process), a gate electrode 221 formed of the second conductive layer is formed on the active layer 224.

In this case, the first insulating layer 215a may be formed of an inorganic insulating layer such as silicon nitride layer (SiNx) or silicon oxide layer (SiO ₂ ), or a highly dielectric oxide layer such as hafnium (Hf) oxide or aluminum oxide. In this case, for example, when the silicon oxide film is applied to the first insulating film 215a, the silicon oxide film may be formed to a thickness of 300 to 1000 Å, and dry etching may be used for the etching.

In this case, the first insulating layer 215a may be formed by Chemical Vapor Deposition (CVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD).

In addition, the second conductive layer may use a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, nickel, chromium, molybdenum, titanium, platinum, tantalum, or the like to form the gate electrode 221. In addition, an opaque conductive material such as indium tin oxide or indium zinc oxide may be used as the second conductive layer, and the second conductive layer may have a multilayer structure in which two or more conductive materials are stacked.

6C, after the second insulating film 215b is formed on the entire surface of the substrate 210 on which the gate electrode 221 is formed, the first insulating film is formed through a photolithography process (third mask process). By selectively patterning a portion of the region 215a and the second insulating layer 215b, a contact hole 240 exposing a portion of the drain electrode 223 is formed.

Next, as shown in FIG. 6D, the transparent conductive film is deposited on the entire surface of the substrate 210 and then selectively patterned using a photolithography process (fourth mask process) to drain the drain through the contact hole 240. The pixel electrode 218 electrically connected to the electrode 223 is formed.

Meanwhile, the oxide thin film transistors according to the first and second embodiments of the present invention can use a coplanar structure applied to polycrystalline silicon thin film transistors because they do not require high mobility and no deposition of an n + layer, and thus have a low price. As a result, a thin film transistor having excellent performance can be manufactured.

In addition, the use of the coplanar structure enables the channel of the active layer to be protected from an external light source in the application of a reflective mode such as an electrophoretic display device, thereby reducing the light leakage current and improving driving characteristics.

The electrophoretic display device does not require an external light source, has excellent flexibility and portability, and is a kind of flat panel display having other characteristics such as light weight.

The electrophoretic display device is a reflective display that forms a thin film transistor array substrate on a thin, bendable base film such as paper or plastic, and coats a transparent conductive film to drive electrophoretic suspension. It is a display device that is expected to attract attention as an electric paper.

Hereinafter, the electrophoretic display device will be described in detail with reference to the accompanying drawings.

8 is a cross-sectional view schematically showing the structure of an electrophoretic display device.

As shown in the figure, the electrophoretic display device has a front panel lamination (FPL) 355 provided with capsules 351 on the lower array substrate 310 for active driving, and above the FPL 355. A protection sheet 356 is attached to protect the FPL 355 from moisture, and is sealed to prevent panel deterioration caused by the external environment by blocking the outer part from the atmosphere by using a sealant. .

The FPL 355 includes an upper electrode 354 formed on the upper plate 353, and capsules 351 positioned on the upper electrode 354 and including charged pigment particles.

In this case, although not shown in detail, the lower array substrate 310 is formed on the lower plate, and includes a gate line and a data line defining a pixel region by crossing a gate insulating layer therebetween, a thin film transistor formed in the cross region, and And a pixel electrode 325 formed in the pixel region.

Although not shown in the drawing, the thin film transistor includes a gate electrode supplied with a gate voltage, a source electrode connected to the data line, a drain electrode connected to the pixel electrode 325, and the source electrode overlapping the gate electrode. And an active layer forming a conductive channel between the drain electrode and the drain electrode. In this case, an ohmic contact layer for forming an ohmic contact with the source electrode and the drain electrode is further provided on the active layer.

The FPL 355, the lower array substrate 310, and the protective sheet 356 having such a structure are bonded by an adhesive 352 to form an electrophoretic display device.

In the electrophoretic display device, the pixel voltage signal supplied to the data line is charged in the pixel electrode 325 via the channel of the thin film transistor in response to the gate voltage supplied to the gate electrode of the lower array substrate 310, and the upper FPL ( When the reference voltage is supplied to the upper electrode 354 of the 355, the white dye particles and the black dye particles in the capsule 351 are divided into two by the electrophoresis caused by an electric field, thereby implementing black, white or predetermined gray. It becomes possible.

As described above, the present invention can be used not only in a liquid crystal display device but also in another display device manufactured using a thin film transistor, for example, an organic light emitting display device in which an organic light emitting element is connected to a driving transistor.

In addition, the present invention has an advantage that it can be used in a transparent electronic circuit or a flexible display by applying an amorphous zinc oxide-based semiconductor material capable of processing at low temperatures while having a high mobility as an active layer.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

1 is an exploded perspective view schematically showing a general liquid crystal display device.

2 is a cross-sectional view schematically showing the structure of an oxide thin film transistor according to a first embodiment of the present invention.

3A to 3E are cross-sectional views sequentially illustrating a manufacturing process of an oxide thin film transistor according to a first embodiment of the present invention shown in FIG.

4A to 4F are cross-sectional views illustrating in detail the first mask process illustrated in FIG. 3A.

5 is a cross-sectional view schematically showing the structure of an oxide thin film transistor according to a second embodiment of the present invention.

6A through 6D are cross-sectional views sequentially illustrating a manufacturing process of an oxide thin film transistor according to a second exemplary embodiment of the present invention illustrated in FIG. 5.

7A to 7F are cross-sectional views illustrating in detail the first mask process illustrated in FIG. 6A.

8 is a sectional view schematically showing the structure of an electrophoretic display element.

DESCRIPTION OF REFERENCE NUMERALS

110,210: array substrate 111,211: buffer layer

118,218 pixel electrode 121,221 gate electrode

122,222 source electrode 123,223 drain electrode

124,224 active layer

Claims (8)

Forming an active layer of amorphous zinc oxide semiconductor on the substrate using a diffraction mask with a diffraction pattern applied to the source / drain regions of the active layer, and forming a gate electrode on the channel region of the active layer with a first insulating film interposed therebetween. Making; Forming a second insulating film on the substrate on which the gate electrode is formed; Removing portions of the second insulating layer to form first and second contact holes exposing portions of the source / drain regions of the active layer; Forming a source / drain electrode electrically connected to the source / drain regions of the active layer through the first and second contact holes; Forming a third insulating film on the substrate on which the source / drain electrodes are formed; Removing a portion of the third insulating layer to form a third contact hole exposing a portion of the drain electrode; And And forming a pixel electrode electrically connected to the drain electrode through the third contact hole. The method of claim 1, wherein the active layer is formed of an a-IGZO semiconductor. The method of claim 1, wherein the substrate is formed of a glass substrate or a plastic substrate.  2. The method of claim 1, wherein the first insulating film is formed to a thickness of 300 to 1000 kW using a silicon oxide film. The method of claim 1, wherein the first contact hole and the second contact hole are formed, and then hydrogen or argon plasma treatment is performed on the surface of the substrate, followed by aluminum (Al), aluminum alloy (Al alloy), copper ( The source may be deposited by depositing low resistance conductive materials such as copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), platinum (Pt), and tantalum (Ta). A method for manufacturing an oxide thin film transistor, characterized in that it forms a drain electrode. Forming an active layer made of an amorphous zinc oxide-based semiconductor on a substrate using a diffraction mask having a diffraction pattern applied to a channel region of the active layer, and forming a source / drain electrode electrically connected to the source / drain regions of the active layer. step; Forming a first insulating film on the substrate on which the source / drain electrodes are formed; Forming a gate electrode on the substrate on which the first insulating film is formed; Forming a second insulating film on the substrate on which the gate electrode is formed; Removing a portion of the first insulating layer and the second insulating layer to form a contact hole exposing a portion of the drain electrode; And And forming a pixel electrode electrically connected to the drain electrode through the contact hole. The method of claim 6, wherein the active layer is formed of an a-IGZO semiconductor. The method of claim 6, wherein the substrate is formed of a glass substrate or a plastic substrate.

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