KR20080102665A - Thin film transistor and display device comprising the same - Google Patents

Abstract

A TFT of a display device is provided to improve the reliability of the display device by improving the characteristics of the TFT. A source electrode(205a) and a drain electrode(205b) is located on the surface of the substrate(200). A semiconductor layer(210) including oxide is electrically connected to the source electrode and drain electrode. A first gate insulating layer(215) is located on the surface of the semiconductor layer. A second gate insulating layer(220) is located on the surface the first gate insulating layer in order to cover the side of the semiconductor layer and the first gate insulating layer. A TFT including the gate electrode is located on the surface the second gate insulating layer, and is positioned to be corresponded to the specific area of the semiconductor layer.

Description

Thin film transistor and display device comprising same

1 is a cross-sectional view illustrating a thin film transistor and a display device according to an exemplary embodiment of the present invention.

2A to 2F are cross-sectional views illustrating processes of manufacturing a thin film transistor and a display device according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

200 substrate 205a source electrode

205b: drain electrode 210: semiconductor layer

215: first gate insulating film 220: second gate insulating film

225: gate electrodes 230a and 230b: contact holes

235a, 235b: first and second connection wiring

240: passivation film 245: beer hole

250: first electrode 255: insulating film

260: opening 265: light emitting layer

270: second electrode

The present invention relates to a thin film transistor and a display device including the same.

Recently, the importance of the flat panel display (FPD) has increased with the development of multimedia. In response, various liquid crystal displays (LCDs), plasma display panels (PDPs), field emission displays (FEDs), light emitting devices (Light Emitting Devices), etc. Has been put to practical use.

Among them, the liquid crystal display device has better visibility than the cathode ray tube, the average power consumption and the heat generation amount are small, and the electroluminescent display device has a response speed of 1 ms or less, high response speed, low power consumption, Since it is self-luminous, there is no problem in viewing angle, and thus it is attracting attention as a next generation display device.

There are two methods of driving the display device, a passive matrix method and an active matrix method using a thin film transistor. The passive matrix method forms the anode and the cathode to be orthogonal and selects and drives the lines, whereas the active matrix method connects the thin film transistors to each pixel electrode and drives them according to the voltage maintained by the capacitor capacitance connected to the gate electrode of the thin film transistor. That's the way it is.

In the thin film transistor for driving the display device, not only the characteristics of the basic thin film transistor such as mobility and leakage current, but also durability and electrical reliability that can maintain a long life is very important. Here, the semiconductor layer of the thin film transistor is mainly formed of amorphous silicon or polycrystalline silicon, the amorphous silicon has the advantage that the film forming process is simple and the production cost is low, but the electrical reliability is not secured. In addition, polycrystalline silicon is very difficult to apply a large area due to the high process temperature, there is a problem that the uniformity according to the crystallization method is not secured.

On the other hand, when the semiconductor layer is formed of oxide, high mobility can be obtained even when the film is formed at a low temperature, and since the resistance change is large according to the oxygen content, it is very easy to obtain the desired physical properties. It's attracting great attention. In particular, examples thereof include zinc oxide (ZnO), indium zinc oxide (InZnO), indium gallium zinc oxide (InGaZnO ₄ ), and the like.

An example of a manufacturing method of a thin film transistor made of a semiconductor layer containing a conventional oxide will be briefly described as follows.

A metal film such as aluminum (Al) is deposited on the substrate and patterned to form a source electrode and a drain electrode. The semiconductor layer is electrically connected to the source electrode and the drain electrode to form an oxide layer.

A gate insulating film is formed on the entire surface of the substrate including the semiconductor layer, and a gate electrode corresponding to a predetermined region is formed on the gate insulating film to complete a thin film transistor.

In the above-described method for manufacturing a thin film transistor, after the semiconductor layer is formed, a process such as a gate insulating film is performed by a separate processing device. Therefore, there is a problem that the manufacturing cost is increased by requiring a long manufacturing time.

In particular, since the semiconductor layer is exposed to the surface of the semiconductor layer in the air while moving to another chamber to deposit the gate insulating layer after the semiconductor layer is formed, there is a problem in that the characteristics of the semiconductor layer are deteriorated.

Accordingly, the present invention provides a thin film transistor capable of improving the characteristics of the thin film transistor and increasing the reliability of the display device and a display device including the same.

In order to achieve the above object, the present invention is a substrate, a source electrode and a drain electrode positioned on the substrate, a semiconductor layer electrically connected to the source electrode and the drain electrode, including an oxide, on the semiconductor layer A first gate insulating layer positioned on the second gate insulating layer and a second gate insulating layer positioned on the first gate insulating layer so as to cover side surfaces of the first gate insulating layer and the semiconductor layer. A thin film transistor including a gate electrode positioned to correspond to an area is provided.

The present invention also provides a substrate, a source electrode and a drain electrode positioned on the substrate, a semiconductor layer electrically connected to the source electrode and the drain electrode, the semiconductor layer including an oxide, a first gate insulating layer positioned on the semiconductor layer, A second gate insulating layer disposed on the first gate insulating layer so as to cover side surfaces of the first gate insulating layer and the semiconductor layer, and a gate electrode positioned on the second gate insulating layer and corresponding to a predetermined region of the semiconductor layer And a first electrode electrically connected to any one of the source electrode and the drain electrode.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

<Example>

1 is a cross-sectional view illustrating a thin film transistor and a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a source electrode 105a and a drain electrode 105b are positioned on a substrate 100. A semiconductor layer 110 including an oxide electrically connected to the source electrode 105a and the drain electrode 105b is positioned. The first gate insulating layer 115 is positioned on the surface of the semiconductor layer 110 on the semiconductor layer 110. The first gate insulating layer 115 is formed on the surface of the semiconductor layer 110 by collectively etching the semiconductor layer 110 and the first gate insulating layer 115. The second gate insulating film 120 is positioned on the entire surface of the substrate 100 including the first gate insulating film 115.

Here, the semiconductor layer 110 and the first gate insulating layer 115 may have a taper angle of 10 to 80 degrees. Here, when the taper angle of the semiconductor layer 110 and the first gate insulating film 115 is 10 ° or more, the distance between the patterns is too far to prevent the disadvantages of integration, and when it is 80 ° or less, the step becomes large and the subsequent gate When forming an insulating film or the like, there is an advantage in that the step coverage is not good and the insulation can be prevented from deteriorating.

A gate electrode 125 corresponding to a predetermined region of the semiconductor layer 110 is positioned on the second gate insulating layer 120, and contact holes 130a exposing a portion of the source electrode 105a and the drain electrode 105b. The thin film transistor is configured by placing the first connection line 135a and the second connection line 135b electrically connected to the source electrode 105a and the drain electrode 105b through 130b.

The passivation layer 140 is disposed to protect and insulate the thin film transistor including the source electrode 105a, the drain electrode 105b, the semiconductor layer 110, and the gate electrode 125. On the passivation layer 140, a first electrode electrically connected to the first or second connection wires 135a and 135b through a via hole 145 exposing one of the first and second connection wires 135a and 135b. 150) is located.

An insulating layer 155 having an opening 160 exposing a portion of the first electrode 150 is disposed on the entire surface of the substrate 100 including the first electrode 150, and the first exposed layer is exposed by the insulating layer 155. The emission layer 165 is positioned on the first electrode 150. The second electrode 170 is positioned on the substrate 100 including the emission layer 165, thereby forming a thin film transistor and a display device including the same.

The thin film transistor and the display device including the same according to the exemplary embodiment having the above structure improve the characteristics of the thin film transistor by collectively etching the semiconductor layer and the first gate insulating layer to have a predetermined taper angle, and the thin film transistor and There is an advantage to provide a thin film transistor and a display device including the same that can improve the reliability of the display device.

Hereinafter, a thin film transistor and a method of manufacturing a display device including the same according to an exemplary embodiment of the present invention will be described with reference to FIGS. 2A to 2F.

2A through 2F are cross-sectional views of processes of a thin film transistor and a display device including the same, according to an exemplary embodiment.

Referring to FIG. 2A, a source electrode 205a and a drain electrode 205b are formed on a substrate 200 including glass, plastic, or metal. The source electrode 205a and the drain electrode 205b may be any one selected from the group consisting of ITO, IZO, Al-doped ZnO, and SnO or molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), One selected from the group consisting of titanium (Ti), nickel (Ni) and copper (Cu) or an alloy thereof may be used.

Next, the semiconductor layer material 210a is stacked on the source electrode 205a and the drain electrode 205b. The semiconductor layer material 210a may be formed of an oxide, and may include zinc oxide (ZnO), indium zinc oxide (InZnO), zinc tin oxide (ZnSnO), or indium gallium zinc oxide (InGaZnO ₄ ).

Next, the first gate insulating material 215a is stacked to cover the semiconductor layer material 210a. The first gate insulating material 215a includes silicon oxide (SiOx), silicon nitride oxide (SiOxNy), aluminum oxide (AlOx), hafnium oxide (HfOx), iridium oxide (YOx), titanium oxide (TiOx), and strontium oxide (SrOx). One or more selected from the group consisting of gallium oxide (GaOx) and barium strontium titanium oxide (BST: BaSrTiO) may be used.

In this case, the first gate insulating material 215a may be formed to a thickness of 1 to 500nm. Here, when the thickness of the first gate insulating material 215a is 1 nm or more, it is possible to prevent the leakage current of the thin film transistor from increasing. When the thickness of the first gate insulating material 215a is 500 nm or less, the process time is too long to prevent productivity and manufacturing cost efficiency from being lowered. There is an advantage to this.

Here, the semiconductor layer material 210a and the first gate insulating material 215a may be formed in a cluster type chamber. The cluster type chamber may be formed by hermetically connecting a plurality of vacuum chambers to a common vacuum chamber. By the process method which does not expose to air | atmosphere, it becomes possible to prevent the air pollutant from adsorb | sucking to a board | substrate, and can solve the problem which must create a new vacuum atmosphere after each process is completed.

That is, after the semiconductor layer material 210a is stacked on the substrate 200, the first gate insulating material 215a may be formed by moving the substrate in a vacuum state without exposing the substrate 200 to air. Therefore, contaminants are adsorbed on the surface of the semiconductor layer exposed to the air, thereby preventing the deterioration of the characteristics of the thin film transistor.

Subsequently, referring to FIG. 2B, the semiconductor layer material 210a and the first gate insulating film 215a are collectively etched using one mask to form the semiconductor layer 210 and the first gate insulating film 215. In this case, the semiconductor layer 210 and the first gate insulating layer 215 may be formed to have a taper angle of 10 to 80 degrees.

FIG. 2C is an enlarged view of region A of FIG. 2B.

Referring to FIG. 2C, the semiconductor layer 210 and the first gate insulating layer 215 are collectively etched to exhibit the same taper angle. At this time, the taper angle (θ ₂₎ of the taper angle (θ ₁₎ and the first gate insulating film 215 of the semiconductor layer 210 may be 10 to 80 °. Here, when the taper angle of the semiconductor layer 210 and the first gate insulating film 215 is 10 ° or more, the gap between the patterns is too far to prevent the disadvantages of integration, and when it is 80 ° or less, the step becomes large and the subsequent gate When forming the insulating film or the like, there is an advantage in that the step coverage becomes poor and the insulation can be prevented from deteriorating.

Next, referring to FIG. 2D, a second gate insulating film 220 is formed on the entire surface of the substrate 200 including the first gate insulating film 215. The second gate insulating layer 220 may include silicon oxide (SiOx), silicon nitride oxide (SiOxNy), aluminum oxide (AlOx), hafnium oxide (HfOx), iridium oxide (YOx), titanium oxide (TiOx), strontium oxide (SrOx), Any one or more selected from the group consisting of gallium oxide (GaOx) and barium strontium titanium oxide (BST: BaSrTiO) may be used.

In this case, the second gate insulating layer 220 may be formed to a thickness of 1 to 500nm. Here, when the thickness of the second gate insulating material 220 is 1 nm or more, the leakage current of the thin film transistor may be prevented from increasing, and when the thickness of the second gate insulating material 220 is 500 nm or less, the process time may be too long to prevent the productivity and the manufacturing cost efficiency from being lowered. There is an advantage to this.

Subsequently, a metal film such as chromium (Cr), molybdenum (Mo), indium tin oxide (ITO), or aluminum (Al) is stacked on the second gate insulating layer 220. Thereafter, the semiconductor layer 210 is patterned using a photolithography process to form a gate electrode 225 to correspond to a predetermined region, thereby forming the source and drain electrodes 205a and 205b and the semiconductor layer 210. ), And manufacturing the thin film transistor including the first and second gate insulating layers 215 and 220 and the gate electrode 225.

The thin film transistor manufactured according to the above-described process is exposed to the air because the semiconductor layer material is stacked in the cluster type chamber, and the first gate insulating film material is stacked and etched together to form the semiconductor layer and the first gate insulating film. By preventing the semiconductor layer from being contaminated, there is an advantage in that the characteristics of the thin film transistor can be prevented from being lowered.

In addition, since the semiconductor layer and the first gate insulating film have a constant taper angle, there is an advantage in that the thin film transistor can be integrated and the insulation property can be prevented from deteriorating.

In the exemplary embodiment of the present invention, the method of manufacturing the thin film transistor having the top gate structure has been described. Alternatively, the thin film transistor having the bottom gate structure may be manufactured by forming a gate electrode and a gate insulating film and then forming a semiconductor layer.

Next, referring to FIG. 2E, contact regions 230a and 230b exposing portions of the source electrode 205a and the drain electrode 205b are formed by etching a predetermined region of the second gate insulating layer 220. Subsequently, first and second connection wirings 235a and 235b are formed on the source electrode 205a and the drain electrode 205b exposed by the contact holes 230a and 230b.

The passivation layer 240 is formed on the entire surface of the substrate 200 including the first and second connection wirings 235a and 235b. The passivation film 240 may be formed of an inorganic material such as silicon nitride or silicon oxide to insulate the first electrode and the gate electrode to be subsequently formed. On the other hand, it may be a planarization film for alleviating the step difference of the lower structure, and the organic material or silicon oxide such as polyimide, benzocyclobutene series resin, acrylate (acrylate) or the like in the form of a liquid coating It may also be formed using an inorganic material such as spin on glass (SOG) to be cured.

Thereafter, the passivation film 240 is etched to form a via hole 245 exposing any one of the first and second connection wirings 235a and 235b. The first electrode 250 connected to any one of the first and second connection wires 235a and 235b is formed through the via hole 245. Therefore, the first electrode 250 is connected to any one of the first and second connection wirings 235a and 235b to be electrically connected to the source electrode 205a or the drain electrode 205b.

The first electrode 250 may be formed of a transparent conductive film such as indium tin oxide (ITO) or indium zinc oxide (IZO). In addition, in the case of forming the front emission type structure, it has high reflectivity such as aluminum (Al), aluminum-neodymium (Al-Nd), silver (Ag), silver alloy (Ag alloy), etc. in the lower portion of the transparent conductive film. It may further include a reflective metal film.

Next, referring to FIG. 2F, an insulating film 255 is formed on the first electrode 250 to insulate adjacent first electrodes. Then, the insulating layer 255 is etched to form an opening 260 exposing the first electrode 250.

The light emitting layer 265 is formed in the opening 260 exposing the first electrode 250. The light emitting layer 265 may be formed using a vacuum deposition method, a laser thermal transfer method, a screen printing method, or the like. In addition, one or more layers of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer may be further included on or below the emission layer 265.

Subsequently, the second electrode 270 is formed on the entire surface of the substrate 200 including the emission layer 265 to complete the thin film transistor and the display device including the same.

In an exemplary embodiment of the present invention, an organic light emitting display device including a light emitting layer 265 between the first electrode 250 and the second electrode 270 is disclosed. Alternatively, the first electrode 250 and the second electrode are different from each other. It is also applicable to a liquid crystal display device including a liquid crystal layer between the electrodes 270.

A thin film transistor manufactured according to the above-described process and a display device including the same may be formed by stacking semiconductor layer materials in a cluster type chamber, stacking first gate insulating film materials, and then etching the bulk to form a semiconductor layer and a first gate insulating film. Therefore, there is an advantage that the characteristics of the thin film transistor can be prevented from being lowered by preventing the semiconductor layer from being exposed to the air and contaminating the semiconductor layer.

In addition, since the semiconductor layer and the first gate insulating film have a constant taper angle, there is an advantage in that a display device capable of achieving integration of a thin film transistor and preventing degradation of insulation characteristics can be provided.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention described above may be modified in other specific forms by those skilled in the art to which the present invention pertains without changing its technical spirit or essential features. It will be appreciated that it may be practiced. Therefore, the embodiments described above are to be understood as illustrative and not restrictive in all aspects. In addition, the scope of the present invention is shown by the claims below, rather than the above detailed description. Also, it is to be construed that all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention.

As described above, the thin film transistor of the present invention and the display device including the same have an advantage of preventing degradation of characteristics of the thin film transistor and improving reliability.

Claims (7)

Board; A source electrode and a drain electrode on the substrate; A semiconductor layer electrically connected to the source electrode and the drain electrode, the semiconductor layer including an oxide; A first gate insulating layer on the semiconductor layer; A second gate insulating layer disposed on the first gate insulating layer to cover side surfaces of the first gate insulating layer and the semiconductor layer; And And a gate electrode positioned on the second gate insulating layer and corresponding to a predetermined region of the semiconductor layer. The method of claim 1, The semiconductor layer may include at least one selected from the group consisting of zinc oxide (ZnO), indium zinc oxide (InZnO), indium gallium zinc oxide (InGaZnO), and zinc tin oxide (ZnSnO). The method of claim 1, The first and second gate insulating layers may include silicon oxide (SiOx), silicon nitride oxide (SiOxNy), aluminum oxide (AlOx), hafnium oxide (HfOx), iridium oxide (YOx), titanium oxide (TiOx), and strontium oxide (SrOx). A thin film transistor including any one or two selected from the group consisting of gallium oxide (GaOx) and barium strontium titanium oxide (BST: BaSrTiO). The method of claim 1, The thin film transistor of claim 1, wherein the first and second gate insulating layers have a thickness of 1 to 500 nm. The method of claim 1, The taper angle of the edge region of the semiconductor layer is 10 to 80 degrees thin film transistor. The method of claim 1, The taper angle of the edge region of the first gate insulating film is 10 to 80 degrees. Board; A source electrode and a drain electrode on the substrate; A semiconductor layer electrically connected to the source electrode and the drain electrode, the semiconductor layer including an oxide; A first gate insulating layer on the semiconductor layer; A second gate insulating layer disposed on the first gate insulating layer to cover side surfaces of the first gate insulating layer and the semiconductor layer; A gate electrode on the second gate insulating layer and corresponding to a predetermined region of the semiconductor layer; And And a first electrode electrically connected to any one of the source electrode and the drain electrode.

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