KR20160094528A - Gate shift register and display device using the same - Google Patents

Abstract

The present invention relates to a gate shift register capable of securing output safety, preventing signal distortion, and reducing the failure of image quality, and a display device using the same. The gate shift register and the display device using the same include stages comprising transistors. The transistors comprise a light shielding layer overlapped with a semiconductor layer. The light shielding layer can be electrically connected to one selected among the source electrode, the drain electrode, the gate electrode of each transistor.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a gate shift register,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate shift register, and more particularly, to a gate shift register capable of ensuring output stability and preventing signal distortion to reduce image quality defects and a display using the same.

2. Description of the Related Art Recently, a display device widely used includes a liquid crystal display device and an organic light emitting display device.

In general, a display device includes a display panel for displaying an image, a gate driver for supplying a scan pulse to gate lines of the display panel, a data driver for supplying a data voltage to data lines of the display panel, And a timing controller for controlling the data driver.

The gate driver includes a gate shift register for driving a plurality of gate lines, and the gate shift register includes a plurality of stages for sequentially outputting scan pulses.

Each of the plurality of stages includes a pull-up transistor and a pull-up transistor as an output buffer portion. The pull-up transistor is switched according to the voltage of the first node charged by the carry signal provided from the previous stage to output a scan pulse to the output terminal. The pull-down transistor is switched according to a voltage of a second node charged by a reset signal to supply a gate-off voltage to the output terminal.

On the other hand, in recent display devices, transistors are composed of oxide thin film transistors in order to satisfy high mobility and constant current test conditions. Oxide transistors have amorphous zinc oxide based semiconductors, which can satisfy high mobility and constant current test conditions, and have uniform characteristics and can be applied to large area displays. The zinc oxide (ZnO) is a material which can realize all three properties of conductivity, semiconductivity and resistance according to oxygen content.

On the other hand, the oxide transistor is characterized in that the threshold voltage is shifted by light. Therefore, when the oxide transistor is formed of a coplanar structure, it is required to arrange a light shielding layer (also called a light shield) on the back surface of the semiconductor layer in order to reduce the influence of external light.

However, when the gate shift register according to the related art is composed of oxide transistors, there is a problem that the light shielding layer affects the threshold voltage of the pull-up transistor and the output stability of the pull-up transistor is degraded and the signal is distorted.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a gate shift register and a display device using the gate shift register, which can reduce image quality by securing output stability and preventing signal distortion.

Other features and advantages of the invention will be set forth in the description which follows, or may be obvious to those skilled in the art from the description and the claims.

According to an aspect of the present invention, there is provided a gate shift register and a display device using the same, including a plurality of stages including a plurality of transistors, the plurality of transistors including a light shielding layer overlapping a semiconductor layer, The light-shielding layer may be electrically connected to any one of a source electrode, a drain electrode, and a gate electrode of each transistor.

Wherein the plurality of transistors includes a pull-up transistor that outputs the scan pulse to an output terminal in accordance with a voltage level of the first node, and a pull-down transistor that supplies a gate-off voltage to the output terminal in accordance with a voltage level of the second node And the light-shielding layer provided in the pull-up transistor may be electrically connected to the output terminal.

According to the solution of the above-mentioned problems, the present invention has the following effects.

The present invention is characterized in that a plurality of transistors constituting a gate shift register are provided with a light shielding layer overlapping a semiconductor layer, and the light shielding layer is electrically connected to any one of a source electrode, a drain electrode, and a gate electrode of each transistor . Particularly, since the light-shielding layer and the source electrode are connected to each other in the pull-up transistor, the output stability can be ensured and signal distortion such as multi-output can be prevented and image quality defects can be reduced.

In addition to the effects of the present invention mentioned above, other features and advantages of the present invention will be described below, or may be apparent to those skilled in the art from the description and the description.

1 is a configuration diagram of a display device having a gate shift register according to an embodiment of the present invention.
2 is a configuration diagram of a gate shift register constituting the gate driver 4 shown in FIG.
3 is a configuration diagram of the k-th stage STk shown in FIG.
4 is a configuration circuit diagram of the output buffer unit 12 shown in FIG.
5 is a schematic diagram of the pull-up transistor PU shown in FIG.
6 is a driving waveform diagram of the stage shown in Fig.
7 is a cross-sectional view of a pull-up transistor (PU) according to an example of the present invention.

The meaning of the terms described herein should be understood as follows. The word " first, "" second," and the like, used to distinguish one element from another, are to be understood to include plural representations unless the context clearly dictates otherwise. The scope of the right should not be limited by these terms. It should be understood that the terms "comprises" or "having" does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof. It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, Means any combination of items that can be presented from more than one. The term "on" means not only when a configuration is formed directly on top of another configuration, but also when a third configuration is interposed between these configurations.

Hereinafter, preferred embodiments of a gate shift register and a display device using the gate shift register according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of a display device having a gate shift register according to an embodiment of the present invention.

1 includes a display panel 2, a gate driver 4, a data driver 6, and a timing controller 8. The display panel 2 includes a display panel 2, a gate driver 4, a data driver 6,

The display panel 2 includes a plurality of gate lines GL and a plurality of data lines DL intersecting with each other and a plurality of pixels P are provided at intersections of the display lines GL and DL. Each pixel P displays an image according to a video signal (data voltage) supplied from the data line DL in response to the scan pulse G supplied from the gate line GL. The display panel 2 may be a liquid crystal display panel, a field emission display panel, a plasma display panel, an organic light emitting diode display panel, an electrophoretic display panel, or the like.

The gate driver 4 is a GIP (gate in panel) type gate driver and is disposed in a non-display area of the display panel 2. [ The gate driver 4 includes a gate shift register for supplying a plurality of gate lines GL with a scan pulse G in accordance with a plurality of gate control signals GCS provided from the timing controller 8. [ The plurality of gate control signals GCS include a plurality of clock signals CLKs having different phases and a gate start signal VST for instructing start of driving of the gate driver 4. [

The gate shift register is selectively connected to the lines to which a plurality of clock signals are supplied to sequentially output the scan pulses and includes a plurality of stages composed of a plurality of transistors. The plurality of transistors constituting each stage includes a light-shielding layer LS overlapping the semiconductor layer, and the light-shielding layer LS is electrically connected to any one of a source electrode, a drain electrode, and a gate electrode of each transistor . The present invention ensures output stability and prevents signal distortion, thereby reducing image quality defects. The gate shift register of the present invention will be described later in detail with reference to FIG. 2 to FIG.

The data driver 6 converts the digital image data RGB inputted from the timing controller 8 into a data voltage using a reference gamma voltage and supplies the converted data voltage to a plurality of data lines DL. This data driver 6 is controlled in accordance with a plurality of data control signals DCS provided from the timing controller 8. [

The timing controller 8 arranges image data (RGB) input from the outside in accordance with the size and resolution of the display panel 2 and supplies the image data to the data driver 6. The timing controller 8 generates a plurality of signals by using synchronizing signals SYNC input from the outside, for example, a dot clock DCLK, a data enable signal DE, a horizontal synchronizing signal Hsync, and a vertical synchronizing signal Vsync And supplies the gate and data control signals GCS and DCS to the gate driver 4 and the data driver 6, respectively.

2 is a configuration diagram of a gate shift register constituting the gate driver 4 shown in FIG.

Referring to FIG. 2, a gate shift register according to an embodiment of the present invention includes a plurality of stages ST1 to STn, which are connected in a dependent manner.

The stages ST1 to STn receive any one of the clock pulses CLKs, a high potential voltage VDD and a low potential voltage VSS. The high-potential voltage VDD is set to a voltage higher than the low-potential voltage VSS. The high-potential voltage VDD is the gate-on voltage VGH and the low-potential voltage VSS is the gate- have.

The stages ST1 to STn have two input terminals and one output terminal and output scan pulses G (G1, G2, G3, ...) through output terminals. The scan pulse G is applied to the gate line GL of the display panel 2 and serves as a carry signal CR transferred to the subsequent stage and a reset signal RST transferred to the previous stage. The front stage based on k (1 < k < n) stages STk is referred to as "the first stage ST1 to the k- 1 stage (STk-1) ". Stage is referred to as a " k + 1 stage (STk + 1) to an n-th stage STn " Indicate which one.

Each of the stages ST1 to STn operates in response to the carry signal CR of the front stage and the reset signal RST of the rear stage. However, in the first stage ST1, the gate start signal VST is inputted instead of the carry signal CR. In the n-th stage STn, a reset signal RST is inputted from a dummy stage (not shown).

3 is a configuration diagram of the k-th stage STk shown in FIG.

Referring to FIG. 3, the k-th stage STk includes a node control unit 10 and an output buffer unit 12. 4 is a configuration circuit diagram of the output buffer unit 12 shown in FIG.

The node control unit 10 includes a plurality of TFTs (not shown) and at least one capacitor (not shown) for controlling the voltages of the first and second nodes Q and QB in response to the carry signal CR and the reset signal RST (Not shown). The node controller 10 charges the first node Q to the high potential voltage VDD in response to the carry signal CR and simultaneously discharges the voltage of the second node QB to the low potential voltage VSS . The node controller 10 responds to the reset signal RST to charge the voltage of the second node QB to the high potential voltage VDD and at the same time the voltage of the first node Q to the low potential voltage VSS, .

The output buffer unit 12 receives any one of a plurality of clock pulses CLKs provided from the timing controller 8. The output buffer unit 20 applies the input clock pulse CLK to the output terminal as the scan pulse Gk when the voltage of the first node Q is charged to the high potential voltage VDD. When the voltage of the second node QB is charged to the high potential voltage VDD, the output buffer unit 12 discharges the voltage of the output terminal to the low potential voltage VSS.

The output buffer unit 12 includes a pull-up transistor PU and a pull-down transistor PD, as shown in FIG. The pull-up transistor PU is turned on or off according to the voltage level of the first node Q, and applies a clock signal CLK inputted through the drain inputted at turn-on to the output terminal. The pull-down transistor PD is turned on or off according to the voltage level of the second node QB and applies the low-potential voltage VSS to the output terminal when the turn-on transistor PD is turned on.

In particular, the light-shielding layer LS provided in the pull-up transistor PU is electrically connected to the output terminal of the stage STk, that is, the source electrode of the pull-up transistor PU. In the present invention, the voltage level of the light-shielding layer LS which overlaps with the gate electrode of the pull-up transistor PU is raised or lowered like the output terminal, so that the output stability of the pull-up transistor PU can be secured. This will be described in detail as follows.

5 is a schematic diagram of the pull-up transistor PU shown in FIG. 6 is a driving waveform diagram of the stage shown in Fig. The driving method of each stage will be described with reference to FIGS. 5 and 6, and the output stabilizing effect according to the connection between the light-shielding layer LS and the source electrode in the pull-up transistor PU will be described.

The plurality of clock signals CLKs may include four-phase clock signals, i.e., first to fourth clock signals CLK1 to CLK4, which are shifted and output by a predetermined period.

First, in the first period P1, the scan pulse Gk-1 is supplied from the previous stage STk-1 as the carry signal CR to the stage STk, or the gate start signal VST supplied from the outside And is supplied to the stage STk. Then, the node controller 10 precharges the first node Q to the gate-on voltage VGH in response to the carry signal CR and discharges the second node QB to the gate-off voltage VGL. .

In the second period P2, any one of the plurality of clock signals CLKs, for example, the first clock signal CLK1 is applied to the drain electrode of the pull-up transistor PU in the gate-on voltage VGH state . Then, the voltage level of the first node Q is bootstrapped by the parasitic capacitance of the pull-up transistor PU connected to the supply line of the first clock signal CLK1 to be higher than the gate-on voltage VGH Level.

Thus, the pull-up transistor PU is in a complete turn-on state, and the pull-up transistor PU supplies the first clock signal CLK1 as the kth scan pulse Gk to the output terminal. At this time, the source electrode, that is, the output terminal of the pull-up transistor PU is electrically connected to the light-shielding layer LS so that the metal electrode constituting the light-shielding layer LS is charged to the gate-on voltage VGH level.

This light shielding layer LS overlaps the gate electrode of the pull-up transistor PU, and shifts the threshold voltage of the pull-up transistor PU in the negative direction. As a result, the pull-up transistor PU maintains a more stable turn-on state, consequently, the output stability of the pull-up transistor PU is ensured and the signal distortion can be prevented.

Then, in the third period P3, the first clock signal CLK1 transitions from the gate-on voltage VGH to the gate-off voltage VGL, and thus the scan pulse Gk output to the output terminal OUT And becomes the gate-off voltage VGL. At this time, the voltage of the first node (Q) keeps the voltage precharged by the capacitor (C) provided between the first node (Q) and the output terminal.

Subsequently, in the fourth period P4, the third clock signal CLK3 as a reset signal and the scan pulse Gk + 2 output from at least one subsequent stage are input to the stage STk. Then, in response to the reset signal RST, the node controller 10 discharges the first node Q to the gate-off voltage VGL and charges the second node QB to the gate-on voltage VGH . Then, the pull-up transistor PU is turned off and the pull-down transistor PD is turned on to supply the gate-off voltage VGL to the output terminal.

Thus, the metal electrode constituting the light-shielding layer LS is discharged to the gate-off voltage VGL. The light-shielding layer LS overlaps the gate electrode of the pull-up transistor PU, and shifts the threshold voltage of the pull-up transistor PU in the positive direction. Then, the pull-up transistor PU has a relatively high threshold voltage and stably maintains the turn-off state. Thus, the multi-output can be prevented and the reliability can be improved.

7 is a cross-sectional view of a pull-up transistor (PU) according to an example of the present invention.

The gate shift register of the present invention can be composed of oxide thin film transistors having a coplanar structure. The light-shielding layer LS may be provided on the back surface of the semiconductor layer of the transistor.

Therefore, the pull-up transistor may also be composed of an oxide thin film transistor of a coplanar structure as shown in FIG. That is, the cross-sectional structure of the pull-up transistor includes a substrate GLS, a light-shielding layer LS composed of metal electrodes on the substrate GLS, a buffer layer BUF covering the light-shielding layer LS, A gate insulating film GI covering the semiconductor layer ACT and provided on the gate insulating film GI and overlapped with the semiconductor layer ACT; (ILD) covering the gate electrode G, a semiconductor layer (ACT) provided on the interlayer insulating film (ILD) and penetrating the interlayer insulating film (ILD) and the gate insulating film (GI) And a protective layer PAS covering the source electrode S and the drain electrode D connected to the source electrode S and the drain electrode D,

The drain electrode D is connected to a clock signal supply line (not shown), and the source electrode S is connected to the output terminal of the stage STk. In particular, the source electrode S is connected to the light-shielding layer LS through a plurality of insulating layers, that is, an interlayer insulating film (ILD), a gate insulating film GI, and a buffer layer BUF.

As described above, the present invention is characterized in that a plurality of transistors constituting a gate shift register are provided with a light-shielding layer superimposed on a semiconductor layer, and the light-shielding layer is formed of any one selected from a source electrode, a drain electrode, Respectively. In particular, since the light-shielding layer LS is connected between the light-shielding layer LS and the source electrode in the pull-up transistor PU, the output stability can be ensured and signal distortion such as multi-output can be prevented.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of. Therefore, the scope of the present invention is defined by the appended claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in the scope of the present invention.

PU: pull-up transistor
PD: pull-down transistor
LD: Shading layer
Q: First node
QB: Second node

Claims (6)

A plurality of transistors having a light-shielding layer superimposed on the semiconductor layer;
And the light shielding layer is electrically connected to any one of a source electrode, a drain electrode, and a gate electrode of each transistor. The method according to claim 1,
The plurality of transistors
A pull-up transistor for outputting the scan pulse to an output terminal according to a voltage level of the first node; And
And a pull-down transistor for supplying a gate-off voltage to the output terminal in accordance with the voltage level of the second node;
And the light shield layer provided in the pull-up transistor is electrically connected to the output terminal. 3. The method of claim 2,
Wherein each of the transistors has a coplanar structure, and the light shielding layer is provided on a back surface of the semiconductor layer of the transistor. The method of claim 3,
The pull-up transistor
A gate electrode connected to the first node;
A drain electrode connected to a clock signal supply line; And
And a source electrode connected to the output terminal;
And the source electrode is electrically connected to the light shielding layer through a plurality of insulating layers. The method according to claim 1,
And the plurality of transistors are composed of oxide thin film transistors. A display panel having a plurality of gate lines; And
And a gate shift register embedded in a non-display area of the display panel to drive the plurality of gate lines;
Wherein the gate shift register comprises the gate shift register according to any one of claims 1 to 5.

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