KR20050075221A - Tft for display device and flat panel display device containing the tft - Google Patents

Abstract

The present invention provides a thin film transistor for a display device and a flat panel display device having the thin film transistor. The flat panel display includes a semiconductor layer including source / drain regions and a channel region interposed between the source / drain regions, a gate electrode disposed on the upper or lower portion of the semiconductor layer to correspond to the channel region, and the semiconductor. A thin film transistor positioned to face the gate electrode with a layer interposed therebetween and having a light shielding layer pattern having a width of at least a length of the channel region and a length of the semiconductor layer; And a pixel electrode electrically connected to any one of the source / drain regions of the thin film transistor.

Description

Thin film transistor for display device and flat panel display device including the thin film transistor {TFT for display device and flat panel display device containing the TFT}

The present invention relates to a thin film transistor and a flat panel display device including the thin film transistor, and more particularly, to a thin film transistor for a display device having a light blocking film pattern and a flat panel display device including the thin film transistor.

The flat panel display device is divided into a passive matrix type and an active matrix type. The active matrix flat panel display has less power consumption than the passive matrix flat panel display and is suitable for large area and has a high resolution.

In the active matrix flat panel display, unit pixel regions arranged in a matrix form are defined by intersection of a plurality of scan lines and a plurality of data lines, and at least one thin film transistor is positioned in the unit pixel region. The thin film transistor includes a semiconductor layer having a channel region, a gate electrode, and source / drain electrodes. In the driving of the display device, the channel region may be exposed to external incident light or signal light of the display device. In this case, an electron-hole pair is generated in the channel region, and the generated electrons and holes are generated. May generate a light induced off current. Such photoexcitation leakage current may have a fatal effect on the image quality of the display device.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the problems of the prior art, and to provide a thin film transistor for a display device in which photoexcitation leakage current is suppressed.

Another object of the present invention is to provide a flat panel display having improved image quality.

In order to achieve the above technical problem, an embodiment of the present invention provides a thin film transistor for a display device. The thin film transistor may include a semiconductor layer having source / drain regions and a channel region interposed between the source / drain regions, a gate electrode disposed on the upper or lower portion of the semiconductor layer to correspond to the channel region, and the semiconductor layer. And a light shielding layer pattern positioned to face the gate electrode with a gap therebetween, the light shielding layer pattern having a width of at least a length of the channel region and a length of the semiconductor layer.

Another embodiment of the present invention to achieve the above technical problem provides a flat panel display device. The flat panel display includes a semiconductor layer including source / drain regions and a channel region interposed between the source / drain regions, a gate electrode disposed on the upper or lower portion of the semiconductor layer to correspond to the channel region, and the semiconductor. A thin film transistor positioned to face the gate electrode with a layer interposed therebetween and having a light shielding layer pattern having a width of at least a length of the channel region and a length of the semiconductor layer; And a pixel electrode electrically connected to any one of the source / drain regions of the thin film transistor. Preferably, the pixel electrode is a transparent electrode.

In some embodiments, the light blocking layer pattern may be formed of an opaque insulating material, a metal insulator hybrid layer (MIHL), or a metal material. The opaque insulating material is preferably chromium oxide (CrOx) or molybdenum oxide (MoOx). The MIHL is a film in which the transparent material component and the metal component have an inverse proportion to the thickness thereof, and the composition ratio of the metal component increases as the semiconductor layer approaches the semiconductor layer. The transparent material component is preferably at least one selected from the group consisting of silicon oxide, silicon nitride and ITO. On the other hand, the metal component is preferably at least one selected from the group consisting of aluminum, chromium, molybdenum, tungsten, titanium, silver and copper. When the light blocking layer pattern is made of the metal material, the metal material is preferably one selected from the group consisting of aluminum, tungsten, titanium, tantalum, chromium, chromium alloy, molybdenum and molybdenum alloy.

In some embodiments, the gate electrode and the light blocking layer pattern may be electrically connected to each other. In this case, the light blocking layer pattern preferably has a width equal to the length of the channel region. In this case, the thin film transistor may further include a first insulating film interposed between the light blocking film pattern and the semiconductor layer and having a thickness of 500 kV to 3000 kV. In this case, the light blocking film pattern is preferably made of one selected from the group consisting of chromium, chromium alloy, molybdenum and molybdenum alloy.

Hereinafter, exemplary embodiments of the present invention will be described in more detail with reference to the accompanying drawings in order to describe the present invention in more detail. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. In the figures, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout the specification.

1 is a plan view for explaining a thin film transistor according to a first embodiment of the present invention, Figures 2a and 2b is an embodiment of the present invention taken along the cutting line I-1 'and II-II' of FIG. Cross-sectional views for explaining a thin film transistor and a method of manufacturing the same.

1, 2A and 2B, a substrate 10 made of glass or transparent plastic is provided, and a buffer film 15 is formed on the provided substrate 10. The buffer layer 15 serves to protect the thin film transistor from impurities flowing out of the substrate 10. A light blocking film is formed on the buffer film 15, and the light blocking film is patterned to form a light blocking film pattern 20. The light blocking layer pattern 20 is formed of a material capable of blocking external incident light entering through the substrate 10. The light blocking layer pattern 20 may be formed using an opaque insulating material, a metal insulator hybrid layer (MIHL), or a metal material.

The opaque insulating material may be a material capable of absorbing the incident light and may be chromium oxide (CrOx) or molybdenum oxide (MoOx).

The MIHL has an inversely proportional composition ratio between the transparent material component and the metal component according to its thickness, so that the absorption coefficient may increase according to the traveling direction of the incident light. In the present embodiment, it is preferable that the light blocking film pattern 20 formed using the MIHL is formed so that the composition ratio of the metal component is gradually increased according to the advancing direction of the incident light. That is, in the light blocking film pattern 20, the composition ratio of the metal component is preferably increased gradually as the semiconductor layer is formed in a subsequent step. Thereby, the said incident light can be fully absorbed. Forming the light blocking layer pattern 20 with the MIHL may be performed by co-sputtering or co-evaporation of the transparent material component and the metal component. The transparent material component is preferably silicon oxide (SiO ₂ ), silicon nitride (SiN _X ), or indium tin oxide (ITO). In addition, the metal component is preferably one selected from the group consisting of aluminum (Al), chromium (Cr), molybdenum (Mo), tungsten (W), titanium (Ti), silver (Ag) and copper (Cu). Do.

Metal materials forming the light blocking layer pattern 20 may include aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), chromium (Cr), chromium alloy (Cr alloy), molybdenum (Mo), and the like. It may be one selected from the group consisting of molybdenum alloy (Mo alloy), but is not limited thereto. That is, any metal may be used as a material for forming the light blocking layer pattern 20 if it is formed to a thickness that can block light. As a result, the light blocking layer pattern 20 may not only block the incident light but also have conductivity.

Subsequently, a first insulating layer 25 is formed on the entire surface of the substrate including the light blocking layer pattern 20. The first insulating layer 25 may be a silicon oxide film, a silicon nitride film, or a composite film thereof. An amorphous silicon film is formed on the first insulating film 25 and patterned to form a semiconductor layer 30. The semiconductor layer 30 is formed to cross the light blocking layer pattern 20.

Before patterning the amorphous silicon film, the amorphous silicon film may be crystallized to form a polycrystalline silicon film. Alternatively, the semiconductor layer 30 made of polycrystalline silicon may be formed by crystallizing the semiconductor layer 30 made of amorphous silicon after patterning the amorphous silicon film. The crystallization may include excimer laser annealing (ELA), sequential lateral solidification (SLS), metal induced crystallization (MIC) or metal induced lateral crystallization (metal induced lateral crystallization). ; MILC) can be used. When the crystallization is performed using the excimer laser annealing method, an excimer laser beam is irradiated onto the amorphous silicon film or the semiconductor layer 30 made of the amorphous silicon. The light energy of the irradiated laser beam is converted into thermal energy to melt the amorphous silicon, and the molten amorphous silicon is recrystallized while cooling to form polycrystalline silicon. In this case, the light blocking layer pattern 20 may reduce the size of the crystal grains of the polycrystalline silicon by absorbing heat from the molten amorphous silicon. As a result, the polycrystalline silicon semiconductor layer 30 having uniform characteristics can be formed over the entire substrate.

Subsequently, a second insulating film 35 is formed on the entire surface of the substrate 10 having the semiconductor layer 30. The second insulating layer 35 may be a silicon oxide film, a silicon nitride film, or a composite film thereof. The gate electrode 40 is formed by forming and patterning a gate conductive layer on the second insulating layer 35. The gate electrode 40 is formed to cross the semiconductor layer 30. As a result, the gate electrode 40 and the light blocking layer pattern 20 face each other with the semiconductor layer 30 interposed therebetween. The gate electrode 40 may be formed using one selected from the group consisting of chromium (Cr), chromium alloy (Cr alloy), molybdenum (Mo), and molybdenum alloy (Mo alloy). Subsequently, source / drain regions 30a are formed by implanting ions into the semiconductor layer 30 using the gate electrode 40 as a mask. At the same time, a channel region 30b interposed between the source / drain regions 30a and positioned corresponding to the gate electrode 40 is defined.

Meanwhile, in forming the light blocking layer pattern 20, the light blocking layer pattern 20 has a width W equal to or greater than a length Lc of the channel region 30b and less than or equal to the length Ls of the semiconductor layer 30. To have). The light blocking layer pattern 20 may be formed to have a width W greater than or equal to the length Lc of the channel region 30b to prevent incident light from the lower portion of the substrate 10 from reaching the channel region 30b. Can be. In addition, the light blocking layer pattern 20 is formed to have a width W less than or equal to the length Ls of the semiconductor layer 30, thereby allowing signal light from the upper or lower portion of the substrate 10 to be displayed. The light blocking layer pattern 20 is not blocked unnecessarily. The signal light coming from the top of the substrate 10 may be light emitted from the organic light emitting layer in the back or double-sided organic light emitting display device. In addition, the gate electrode 40 may block incident light from the upper portion of the substrate 10 from reaching the channel region 30b. As a result, it is possible to suppress photoexcitation leakage current that may occur in the channel region 30b. In addition, it is possible to improve the image quality of a display device employing a thin film transistor whose photoexcitation leakage current is suppressed. In the present specification, the incident light includes external light and the signal light.

The light blocking layer pattern 20 and the gate electrode 40 may be formed by changing their positions. That is, the gate electrode 40 is formed before the semiconductor layer 30 is formed and disposed below the semiconductor layer 30, and the light blocking film pattern 20 is formed after the semiconductor layer 30 is formed. It may be formed and disposed on the semiconductor layer 30.

Next, a third insulating film 45 covering the gate electrode 40 is formed. The third insulating layer 45 may be formed of a silicon oxide film, a silicon nitride film, or a composite film thereof. Source / drain contact holes 45a exposing source / drain regions 30a of the semiconductor layer 30 are formed in the third insulating layer 45, respectively. First connection contacts that form the source / drain contact holes 45a and expose the light blocking film 20 and the gate electrode 40 in the third insulating film 45, respectively, as shown in FIG. 3B. The hole 45b and the second connection contact hole 45c may be formed. Source / drain electrodes are formed by forming a source / drain conductive layer on the substrate 10 having the source / drain contact holes 45a and the connection contact holes 45b and 45c, and patterning the source / drain conductive layer. 50 and the connection wiring 51 are formed. The connection wiring 51 is in contact with the light blocking film 20 and the gate electrode 40 at the same time through the first connection contact hole 45b and the second connection contact hole 45c. And the light blocking film 20 are electrically connected to each other. As a result, the light blocking layer 20 may act as the gate electrode with respect to the semiconductor layer 30 together with the gate electrode 40. As a result, the light blocking film 20 and the gate electrode 40 form a double gate. The thin film transistor having the double gate has not only a large on-current characteristic but also a uniform characteristic throughout the substrate.

In the case of forming the double gate, the light blocking layer pattern 20 may be formed to have a width W equal to the length Lc of the channel region 30b. In addition, the light blocking layer pattern 20 is preferably formed using one selected from the group consisting of chromium (Cr), chromium alloy (Cr alloy), molybdenum (Mo) and molybdenum alloy (Mo alloy). In this case, the first insulating film 25 is preferably formed to have a thickness of 500 kV to 3000 kV so that the light blocking film 20 can serve as a gate electrode.

3 is a circuit diagram illustrating a unit pixel driving circuit of an organic light emitting display device according to a second embodiment of the present invention.

Referring to FIG. 3, an n th scan line is positioned in one direction, and an m th data line intersecting while being insulated from the scan line is positioned. The common power line may be insulated from and intersect the scan line and spaced apart from each other on the data line.

The switching thin film transistor M1 is positioned at the intersection of the scan line and the data line. The switching thin film transistor M1 switches the data signal applied to the data line according to the signal applied to the scan line. The switching thin film transistor M1 is connected to the gate of the driving thin film transistor M2 to apply the switched data signal to the gate of the driving thin film transistor M2. At this time, the storage capacitor (Cst) for storing the applied data signal for a predetermined period of time is connected between the gate and the drain of the driving thin film transistor (M2). The data signal stored in the storage capacitor Cst enables a constant data signal to be applied to the gate of the driving thin film transistor M2 even when the switching thin film transistor is turned off. The data signal applied to the gate of the driving thin film transistor M2 causes a current to flow in the driving thin film transistor M2, and the current flowing in the driving thin film transistor M2 is an organic light emitting diode connected to the driving thin film transistor M2. It is supplied to the diode (D) to induce light emission of the organic light emitting diode (D).

The switching thin film transistor M1 and / or the driving thin film transistor M2 include a light blocking film (not shown) that blocks incident light entering the channel region. In the thin film transistor (s) including the light blocking film, generation of photoexcitation leakage currents LK1 and LK2 due to the incident light is suppressed. As a result, generation of the photoexcitation leakage current LK1 in the switching thin film transistor M1 is suppressed, so that the loss of the data signal stored in the storage capacitor Cst can be suppressed. In addition, since the occurrence of the photoexcitation leakage current LK2 in the driving thin film transistor M2 is suppressed, an error in the black of the organic light emitting diode D can be prevented. As a result, the image quality of the organic light emitting display device can be improved.

4 is a cross-sectional view illustrating an organic light emitting display device and a method of manufacturing the same according to a second exemplary embodiment of the present invention. The switching thin film transistor M1, the driving thin film transistor M2, and the organic light emitting diode D of FIG. It is a figure shown only in FIG.

Referring to FIG. 4, a substrate 10 made of glass or transparent plastic is provided, and a light blocking film 20, a semiconductor layer 30, a gate electrode 40, and a source / drain are formed in a predetermined region on the substrate 10. A driving thin film transistor M2 and a switching thin film transistor M1 including the electrodes 50 are formed. The driving thin film transistor M2 and the switching thin film transistor M1 are formed in the same manner as the thin film transistor described with reference to FIGS. 2A and 2B.

A fourth insulating layer 55 may be formed on the entire surface of the substrate 10 having the thin film transistors. The fourth insulating film 55 may be formed of an organic film or an inorganic film or a composite film thereof. The organic layer may be a benzocyclobutene (BCB) layer, and the inorganic layer may be a silicon oxide layer or a silicon nitride layer. A via hole 55a is formed in the fourth insulating layer 55 to expose any one of the source / drain electrodes 50 of the driving thin film transistor M2. The pixel electrode 60 is formed by stacking and patterning a pixel electrode material on a substrate having the via hole 55a. The pixel electrode 60 is preferably formed using a transparent conductive material. The transparent conductive material is preferably indium tin oxide (ITO) or indium zinc oxide (IZO). In addition, the pixel electrode 60 may be formed on the thin film transistors M1 and M2.

Subsequently, a fifth insulating layer 65 may be formed on the pixel electrode 60 to expose a predetermined portion of the surface of the pixel electrode 60. The fifth insulating layer 65 may be formed using one selected from the group consisting of benzocyclobutene (BCB), an acrylic polymer, and an imide polymer. An organic functional layer 70 including at least an organic light emitting layer is formed on the exposed pixel electrode 60. The counter electrode 80 is formed on the organic functional layer 70. The counter electrode 80 is also preferably formed using the transparent conductive material. The pixel electrode 60, the organic functional layer 70, and the counter electrode 80 constitute an organic light emitting diode D.

By forming both the pixel electrode 60 and the counter electrode 80 using a transparent conductive material, the organic light emitting display device may emit signal light in the substrate direction and the substrate opposite direction, that is, both surfaces. In this case, external light may also enter from the bottom of the substrate 10 and the top of the substrate.

At this time, the light emitted from the organic light emitting layer included in the organic functional film 80 toward the substrate is blocked by the gate electrode and is prevented from entering the channel region 30b. In addition, the external incident light coming from the upper and lower portions of the substrate is blocked by the light blocking film 20 and the gate electrode 40 to be prevented from entering the channel region 30b. In addition, the light blocking film 20 may be formed to have a width less than or equal to the length of the semiconductor layer 30, so that signal light emitted from the organic light emitting layer and going out through the substrate 10 may not be blocked unnecessarily. . Therefore, the aperture ratio can be improved.

As described above, the second embodiment of the present invention has described the present invention using an organic light emitting display device as an example, but one of ordinary skill in the art recognizes that the present invention is applicable to a liquid crystal display device. You can do it.

5 is a graph showing current transfer characteristics according to gate voltage changes when light is irradiated to each of the thin film transistor according to the first embodiment of the present invention and the thin film transistor according to the prior art.

Referring to FIG. 5, the thin film transistor P according to the first embodiment, that is, the thin film transistor P having the light blocking film, is lighter than the thin film transistor Q according to the prior art, that is, the thin film transistor Q having no light blocking film. It can be seen that the excitation leakage current is shown.

As described above, according to the present invention, a thin film transistor in which generation of photoexcitation leakage current is suppressed can be obtained. Further, by adopting the thin film transistor in which the generation of the photoexcited leakage current is suppressed, a flat panel display device having improved image quality can be obtained.

1 is a plan view illustrating a thin film transistor according to a first embodiment of the present invention.

2A and 2B are cross-sectional views illustrating a thin film transistor and a method of manufacturing the same according to an embodiment of the present invention, taken along cut lines II ′ and II-II ′ of FIG. 1, respectively.

3 is a circuit diagram illustrating a unit pixel driving circuit of an organic light emitting display device according to a second embodiment of the present invention.

4 is a cross-sectional view for describing an organic light emitting display device and a method of manufacturing the same according to a second embodiment of the present invention.

FIG. 5 is a graph showing current transfer characteristics according to gate voltage changes when light is irradiated to a thin film transistor having a light blocking film and a thin film transistor not including the light blocking film.

(Explanation of symbols for main parts of drawing)

10 substrate 20 light blocking film

30 semiconductor layer 40 gate electrode

Claims (27)

A semiconductor layer having source / drain regions and a channel region interposed between the source / drain regions; A gate electrode positioned above or below the semiconductor layer to correspond to the channel region; And And a light shielding layer pattern positioned to face the gate electrode with the semiconductor layer interposed therebetween, the light shielding layer pattern having a width of at least the length of the channel region and less than the length of the semiconductor layer. Thin film transistor. The method of claim 1, The light blocking layer pattern is a thin film transistor for a display device, characterized in that made of an opaque insulating material. The method of claim 2, The opaque insulating material is chromium oxide (CrOx) or molybdenum oxide (MoOx), a thin film transistor for a display device. The method of claim 1, The light blocking layer pattern is a thin film transistor for a display device, characterized in that the MIHL (Metal Insulator Hybrid Layer) having a composition ratio of the transparent material component and the metal component in inverse proportion to the thickness thereof. The method of claim 4, wherein The light blocking layer pattern, wherein the composition ratio of the metal component increases as the semiconductor layer approaches the thin film transistor. The method of claim 4, wherein The transparent material component is a thin film transistor for a display device, characterized in that at least one selected from the group consisting of silicon oxide, silicon nitride and indium tin oxide (ITO). The method of claim 4, wherein The metal component is a thin film transistor for a display device, characterized in that at least one selected from the group consisting of aluminum, chromium, molybdenum, tungsten, titanium, silver and copper. The method of claim 1, The light blocking layer pattern is a thin film transistor for a display device, characterized in that made of a metal material. The method of claim 8, The metal material is a thin film transistor for a display device, characterized in that one selected from the group consisting of aluminum, tungsten, titanium, tantalum, chromium, chromium alloy, molybdenum and molybdenum alloy. The method of claim 1, The gate electrode and the light blocking layer pattern are electrically connected to each other. The method of claim 10, The light blocking layer pattern has a width equal to the length of the channel region. The method of claim 10, And a first insulating film interposed between the light blocking film pattern and the semiconductor layer and having a thickness of 500 mW to 3000 mW. The method of claim 10, The light blocking layer pattern is a thin film transistor for a display device, characterized in that made of one selected from the group consisting of chromium, chromium alloy, molybdenum and molybdenum alloy. A semiconductor layer having source / drain regions and a channel region interposed between the source / drain regions, a gate electrode positioned to correspond to the channel region on or below the semiconductor layer, and the semiconductor layer interposed therebetween. A thin film transistor positioned to face the gate electrode and having a light shielding layer pattern having a width of at least a length of the channel region and a length of the semiconductor layer; And And a pixel electrode electrically connected to any one of the source / drain regions of the thin film transistor. The method of claim 14, And the pixel electrode is a transparent electrode. The method of claim 14, And the light blocking layer pattern is formed of an opaque insulating material. The method of claim 16, The opaque insulating material is chromium oxide (CrOx) or molybdenum oxide (MoOx) flat panel display device. The method of claim 14, The light blocking film pattern has a composition ratio in which a transparent material component and a metal component are inversely proportional to their thickness, and the composition ratio of the metal component increases as the semiconductor layer approaches the semiconductor layer. The method of claim 18, The transparent material component is at least one selected from the group consisting of silicon oxide, silicon nitride and ITO, And the metal component is at least one selected from the group consisting of aluminum, chromium, molybdenum, tungsten, titanium, silver, and copper. The method of claim 14, And the light blocking layer pattern is formed of a metallic material. The method of claim 20, And the metal material is one selected from the group consisting of aluminum, tungsten, titanium, tantalum, chromium, chromium alloys, molybdenum and molybdenum alloys. The method of claim 14, And the gate electrode and the light blocking layer pattern are electrically connected to each other. The method of claim 22, And the light blocking layer pattern has a width equal to a length of the channel region. The method of claim 22, And a first insulating film interposed between the light blocking film pattern and the semiconductor layer and having a thickness of 500 mW to 3000 mW. The method of claim 22, And the light blocking layer pattern is one selected from the group consisting of chromium, chromium alloys, molybdenum and molybdenum alloys. The method of claim 25, The flat panel display device is an organic light emitting display device. The method of claim 26, A counter electrode, which is a transparent electrode, And an organic light emitting layer interposed between the pixel electrode and the counter electrode.