KR20100052623A - Apparatus for driving liquid crystal panel - Google Patents

Abstract

PURPOSE: An apparatus for driving liquid crystal panel is provided to prevent the overlapping of a memory scan space and a memory storage space by scanning a memory by a period of frame over 2. CONSTITUTION: In an apparatus for driving liquid crystal panel, a memory stores display data. A source driver scans the memory. A source driver supplies the display data to a liquid crystal panel. A timing controller supplies the canning timing signal to the source driver. The source driver scans the memory by a frame according to a scanning timing signal. The source driver supplies the display data to the liquid crystal panel.

Description

Liquid crystal panel driving device {Apparatus for driving liquid crystal panel}

The present invention relates to an apparatus for driving a liquid crystal panel of a liquid crystal display device.

As information processing technology develops, display devices such as LCD, PDP and AMOLED are widely used. These displays have a built-in drive. The driving device determines the image quality of the display device.

The present invention provides an apparatus for driving a liquid crystal panel capable of improving the image quality of a display image.

A liquid crystal panel drive device according to an embodiment of the present invention includes a memory for storing display data; A source driver scanning the memory to supply the stored display data to a liquid crystal panel; And a timing controller configured to supply a scan timing signal to the source driver, wherein the source driver scans the memory at intervals of two or more frames in accordance with a scan timing signal supplied from the timing controller to display the display data in units of frames. Supply to the liquid crystal panel.

According to the present invention, the memory included in the liquid crystal panel driving apparatus is scanned at intervals of two or more frames, whereby the memory storage section and the memory scan section can be prevented from overlapping. It is possible to reduce the tearing phenomenon that may occur by.

Hereinafter, a panel driving apparatus according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 7.

1 is a block diagram illustrating an embodiment of a configuration of a liquid crystal panel driving apparatus according to the present invention.

Referring to FIG. 1, the liquid crystal display includes a liquid crystal panel 100 and a driver IC 200. The liquid crystal panel 100 has a plate shape and may display an image by adjusting the intensity of light passing in units of pixels.

The liquid crystal panel 100 may include a TFT substrate, a color filter substrate, and a liquid crystal layer interposed between the two substrates, and may include polarizing sheets disposed below the TFT substrate and on the color filter substrate. have.

The TFT substrate includes gate lines, data lines, thin film transistors, and pixel electrodes. In addition, the gate lines extend in parallel with each other in the first direction. The gate lines receive gate signals from the driver IC 200 to operate the thin film transistors.

The data lines extend side by side in a second direction to selectively transmit data signals for displaying an image on the pixel electrodes by an operation of the thin film transistors.

The thin film transistors are disposed in an area where the gate lines and the data lines cross, and the pixel electrodes receive the data signals from the data lines by the operation of the thin film transistors.

The color filter substrate is opposite to the TFT substrate and spaced apart from the TFT substrate. The color filter substrate includes color filters and a common electrode. The color filters correspond to the pixels and may filter white light to generate light having a color.

The common electrode is disposed over the entire pixels. The common electrode receives a common voltage signal from the driver IC 200 and forms an electric field in the liquid crystal layer due to a potential difference between the pixel electrodes. The driver IC 200 may be disposed on one side of the liquid crystal panel 100, and more specifically, the driver IC 200 may be mounted on the liquid crystal panel 100 by a chip on glass (COG) method.

The driver IC 200 drives the liquid crystal panel 100 and is a chip in which a plurality of circuits for driving the liquid crystal panel 100 are integrated.

As shown in FIG. 1, the driver IC 200 includes a first latch unit 210, a memory 220, a source driver 230, a gate driver 240, a common driver 250, and a control register 260. It may include a timing controller 270 and an oscillator 280.

The first latch unit 210 receives and latches display data for displaying an image from a system, and outputs and stores the latched display data to the memory 220. The memory 220 is preferably a random access memory (RAM), for example, a static random access memory (SRAM).

The memory 220 stores the display data latched by the first latch unit 210, loads the stored display data, and outputs the stored display data to the source driver 230.

The source driver 230 receives a scan timing signal from the timing controller 270, scans the memory 220 according to the scan timing signal, and uses the display data stored in the memory 220 in units of frames. Supply to (100).

In addition, the source driver 230 may include a DA converter (not shown). The DA converter (not shown) converts the display data scanned by the memory 220 to generate a data signal, which is an analog signal, to generate liquid crystal. It can be supplied to the panel 100.

The gate driver 240 receives the timing signal from the timing controller 270 to generate the gate signals, and the common driver 250 receives the timing signal from the timing controller 270 to generate a common voltage signal.

The control register 260 may receive command signals DE, HSYNC, and VSYNC from the system to control the timing controller 270, the memory 220, and the like, and generate a sampling signal for loading the display data. .

The timing controller 270 is supplied to the source driver 230 using the reference clock signal generated by the oscillator 280 and the command signals DE, HSYNC, and VSYNC input from the control register 260. Timing signals including the signal may be generated, and the generated timing signals may be controlled by outputting the generated timing signals to the memory 220 and the drivers 230, 240, and 250.

2 illustrates a section in which display data is stored in a memory and a section in which a memory is scanned.

Referring to FIG. 2, a frame, which is a unit in which an image is displayed, may be defined by a frame clock signal FRAME CLK. In addition, as shown in FIG. 2, the vertical synchronizing signal VSYNK input from the external system is generated every one frame.

The timing controller 260 generates a scan timing signal according to the vertical synchronization signal VSYNK and outputs the scan timing signal to the source driver 230, and the source driver 230 stores the memory 220 at s11 at which the scan timing signal is input. Scans the display data corresponding to one frame from the memory 220 and supplies it to the liquid crystal panel 100.

In FIG. 2, although the rising edge of the vertical synchronization signal VSYNK and the start time s11 of the memory 220 scan are coincident, the rising edge of the vertical synchronization signal VSYNK and the scan start of the memory 220 are started. A time error may occur between the time points s11, and in some cases, scanning of the memory 220 may be started according to the falling edge of the vertical synchronization signal VSYNK.

In addition, new display data is stored in the memory 220 during the data update period from the time point w11 at which display data starts to be stored to the memory 220 to the end time of storing w12.

However, as shown in FIG. 2, the speed of storing display data in the memory 220 may be different from each other, and the scan speed may be faster than the storage speed.

For example, the storage speed of the memory 220 may be about 30 frames / sec, and the scanning speed of the memory 220 may be about 80 frames / sec. In this case, one frame of display data is stored in the memory 220. A difference of about 13 ms may occur between the time required to scan and the time to scan the memory 220.

Accordingly, as shown in FIG. 2, the memory 220 scan is started in the second frame before the time point w12 at which the display data storage to the memory 220 started in the first frame ends, and the scan is ended first at s22. As a result, a section for storing display data in the memory 220 and a section for scanning the memory 220 may overlap.

As described above, when a memory storage speed and a scan speed are different, a tearing phenomenon may occur in which data of two or more frames is displayed on one screen.

FIG. 3 illustrates an example of a tearing phenomenon. As shown in FIG. 3, the data of the previous frame and the current frame in the overlapped portion of the storage section and the scan section caused by the difference between the memory storage speed and the scan speed are shown. The tearing of the screen may occur because the data of the frame appears on the same screen.

In order to reduce the tearing phenomenon as described above, in the liquid crystal panel driving apparatus according to the present invention, the source driver 230 scans the memory 220 at intervals of two or more frames to display the display data in units of frames on the liquid crystal panel 100. It is preferable to supply.

4 illustrates a vertical sync signal VSYNC and a memory storage section and a scan section according to the present invention. The source driver 230 may scan the memory 220 at intervals of n or more frames. For example, a vertical sync signal VSYNC may be generated every n frames.

 For example, the timing controller 270 adjusts the vertical sync signal VSYNC of one frame period input from an external system as shown in FIG. 2 to adjust an n (≥2) frame period as shown in FIG. The branch may generate a vertical sync signal VSYNC, and generate a scan timing signal according to the vertical sync signal VSYNC having the n (≥2) frame period and supply the scan timing signal to the scan driver 230.

As another embodiment, as shown in FIG. 5, the liquid crystal panel driving apparatus according to the present invention may further include a period adjusting unit 290, and the period adjusting unit 290 may include a vertical synchronization signal of an input frame period ( VSYNC may be adjusted to the vertical synchronization signal VSYNC having the n (≥2) frame period and output to the timing controller 270.

Referring to FIG. 4, when a vertical sync signal VSYNC is generated in one frame, the timing controller 270 generates a scan timing signal and supplies the scan timing signal to the scan driver 230, and the scan driver 230 inputs the input signal. The memory 220 starts scanning at s11 according to the scan timing signal.

In addition, display data storage in the memory 220 is started at the time w11 of the one frame. In this case, as shown in FIG. 4, in order to prevent the storage section to the memory 220 and the scan section of the memory 220 from overlapping, the scan start time point s11 of the memory 220 is the memory 220. It is preferable to be earlier than the start time w11 of storing the display data in the furnace.

Thereafter, a vertical sync signal VSYNC of n frame periods is generated in a (n + 1) frame that is n frames later than the one frame, and accordingly, the scan driver 230 stores the memory again in the (n + 1) frame. Scanning 220 begins. In the frames between the one frame and the (n + 1) frame, no vertical sync signal VSYNC is generated, and thus the memory 220 is not scanned.

In addition, as shown in FIG. 4, the display data storage to the memory 220 started in the first frame is terminated at a time w12 before the time when the scan of the memory 220 in the (n + 1) frame 220 ends (s22). Accordingly, the storage section to the memory 220 and the scan section of the memory 220 may not overlap.

As shown in FIG. 4, when the vertical sync signal VSYNC is generated at n (≥2) frame periods to prevent overlap between the storage section to the memory 220 and the memory 220 scan section, the tiering phenomenon as described above is performed. Can be prevented.

The period (n frame) of the vertical synchronization signal VSYNC may be two or more frames, such as two frames, three frames, four frames, and the like, and the memory 220 in the (n + 1) frame as shown in FIG. 4. The n value may be determined such that display data storage to the memory 220 started in one frame is ended before the scan is completed. That is, the value of n may be determined according to the storage speed of the memory 220 and the scanning speed of the memory 220. The value of n is decreased as the storage speed of the memory 220 becomes slower than the scanning speed of the memory 220. Can increase.

In another embodiment according to the present invention, the period (n frame) of the vertical synchronization signal VSYNC may be variably controlled according to the storage speed to the memory 220 and the scan speed of the memory 220.

For example, the period adjuster 290 of FIG. 5 measures or receives the display data storage speed and the memory 220 scan speed of the current driver (IC) into the memory 220, and uses the storage speed and the scan speed. The period (n frame) of the vertical synchronization signal VSYNC is automatically determined, and the vertical synchronization signal VSYNC of the input one frame period can be controlled to have the determined period.

In addition, the operation of automatically determining and periodically applying the period (n frame) of the vertical synchronization signal VSYNC may be performed by the timing controller 270.

6 and 7 illustrate embodiments of the vertical sync signal VSYNC according to the present invention and a memory storage section and a scan section according to the present invention.

Referring to FIG. 6, the scan period of the memory 220 may be two frames. In this case, a vertical sync signal VSYNC is generated in one frame, and the scan driver 230 scans the memory 220 to perform the frame unit. The display data is supplied to the liquid crystal panel 100, and then a vertical synchronizing signal VSYNC is generated again in three frames, and the scan driver 230 scans the memory 220 to display display data in units of frames. 100).

At this time, before the scan of the memory 220 in the three frames is finished, the storage of display data to the memory 220 started in the first frame is terminated, so that the storage section to the memory 220 and the memory 220 scan section are finished. By preventing the superposition of, the tearing phenomenon can be prevented.

When the memory 220 storage speed is slower than that shown in FIG. 6, the scan period of the memory 220 may be increased to three frames as shown in FIG. 7.

Although described above with reference to the embodiment is only an example and is not intended to limit the invention, those of ordinary skill in the art to which the present invention does not exemplify the above within the scope not departing from the essential characteristics of this embodiment It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiment can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

1 is a block diagram showing an embodiment of a configuration of a liquid crystal panel driving apparatus according to the present invention.

2 is a diagram illustrating a section in which display data is stored in a memory and a section in which a memory is scanned.

3 is a diagram illustrating an example of a tearing phenomenon.

4 is a diagram illustrating a vertical sync signal VSYNC, a memory storage section, and a scan section according to the present invention.

5 is a block diagram showing still another embodiment of the configuration of the liquid crystal panel driving apparatus.

6 and 7 illustrate embodiments of a vertical synchronization signal VSYNC and memory storage sections and scan sections according to the present invention.

Claims (9)

A memory for storing display data; A source driver scanning the memory to supply the stored display data to a liquid crystal panel; And A timing controller supplying a scan timing signal to the source driver, And the source driver scans the memory at intervals of n (≥2) frames in accordance with a scan timing signal supplied from the timing controller to supply the display data in units of frames to the liquid crystal panel. The method of claim 1, And the source driver scans the memory every two frames to supply the display data in frame units to the liquid crystal panel. The method of claim 1, And a rate at which the display data is stored in the memory is slower than a rate at which the memory is scanned. The method of claim 1, The liquid crystal panel driving device of the first frame section, wherein the start of scanning the memory is earlier than the start of storing the display data in the memory. The method of claim 4, wherein And a time point at which the storage of the display data started in the first frame period ends is earlier than a time point when the memory starts to be scanned in the (n + 1) th frame period. The method of claim 1, The timing controller generates the scan timing signal using a vertical sync signal (VSYNC), and the vertical sync signal has a period of the n frame. The method of claim 6, And the timing controller adjusts the vertical synchronization signal of one frame period input from the outside to have the period of the n frames, and generates the scan timing signal using the adjusted vertical synchronization signal. The method of claim 6, And a period adjuster which adjusts the vertical synchronization signal of one frame period input from the outside to have the period of the n frame and outputs it to the timing controller. The method of claim 1, And n is variable according to a speed of storing display data in the memory and a speed of scanning the memory.

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