KR101419225B1 - Driving apparatus for liquid crystal display device and method for driving the same - Google Patents

Abstract

The present invention relates to a driving apparatus for a liquid crystal display device and a driving method thereof, which can reduce the manufacturing cost of a liquid crystal display device and improve the image quality by eliminating the operation flow phenomenon of an image without changing the driving frequency.

To this end, the liquid crystal display device of the present invention includes: a liquid crystal panel having a plurality of pixels and divided into at least three regions; A plurality of data drivers for driving a plurality of data lines by adjusting a video signal supply period and a charge sharing period; At least three gate drivers for supplying a scan pulse to the gate lines of the respective regions in units of at least one sub-frame period in accordance with the video signal supply period or the charge sharing period, ; And a timing controller for generating data and gate control signals and controlling the respective data and gate drivers.

An impulsive driving method, a charge share period, a video signal input period

Description

[0001] The present invention relates to a driving apparatus for a liquid crystal display device and a method of driving the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display (LCD), and more particularly, to a driving apparatus and a driving method thereof for a liquid crystal display device capable of improving image quality by eliminating a motion blurring phenomenon of a displayed image.

In general, a liquid crystal display device displays an image using electrical and optical characteristics of a liquid crystal. Liquid crystals can have different anisotropic properties depending on the molecular axis and the direction of the short axis, such as refractive index and dielectric constant, and can easily control the molecular arrangement and optical properties. A liquid crystal display device using the same displays an image by varying the arrangement direction of liquid crystal molecules according to the electric field size to adjust the light transmittance.

Such a liquid crystal display device has a disadvantage in that the response speed is slow due to inherent characteristics of the liquid crystal such as viscosity and elasticity. That is, the liquid crystal response speed may vary depending on the physical properties of the liquid crystal material, the cell gap, and the like, but normally, the rising time is 20-80 ms and the polling time is 20-30 ms. Since the response speed of the liquid crystal is longer than one frame period of the moving display image (NTSC: 16.67 ms), the voltage charged in the liquid crystal cell is advanced to the next frame before reaching the desired voltage.

Accordingly, since the display image of each frame displayed on the liquid crystal panel affects the display image of the next frame, a motion blurring phenomenon occurs in which the moving display image displayed on the liquid crystal panel is blurred by the perception characteristic of the viewer . That is, the liquid crystal display according to the related art has a problem that the contrast ratio is lowered due to the operation flow phenomenon generated in the display image, and the image quality is deteriorated.

In order to prevent such a motion flow phenomenon, an impulsive driving method has been conventionally used. Among the impulsive driving methods, a data addressing method (data addressing method) for inputting image data in a certain area of each frame and inputting black or white data in the remaining areas is mainly used.

1 is a diagram illustrating a data addressing method according to the prior art. 2 is a driving waveform diagram for implementing the data addressing method shown in FIG.

1 and 2, the images of each frame (n-1 to n + 1 Frame) displayed according to the data addressing method have a blanking area in which black data is inserted in a certain area . Here, the blanking region is an area corresponding to four gate lines, and may be formed after four gate lines of a pixel column in which black data is input for each frame are added. Accordingly, the position of the blanking area can be shifted every frame.

2, the gate driving signals Gout1 to Goutn are sequentially supplied to the gate lines of the liquid crystal panel. At this time, the gate driving signals Goutn- 3 to Goutn) are supplied. Black data is supplied to each data line to form a blanking area so as to be synchronized with the driving timing A of the simultaneously driven gate lines. Of course, the position of the blanking area (blank) is shifted every frame.

However, in the above-described conventional data addressing method, since the input of the image data signal is delayed during the blanking interval and the charged amount of the image data signal is varied before and after the blanking interval, the horizontal line dim Dim) phenomenon occurs in many cases. In addition, since the conventional data addressing method requires at least one memory for storing black data, the manufacturing cost is increased and the driving frequency must be changed according to the blanking interval.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and it is an object of the present invention to provide a liquid crystal display device capable of reducing the manufacturing cost of a liquid crystal display device, And an object of the present invention is to provide a device and a driving method thereof.

According to an aspect of the present invention, there is provided a liquid crystal display comprising: a liquid crystal panel having a plurality of pixels and divided into at least three regions; A plurality of data drivers for driving a plurality of data lines by adjusting a video signal supply period and a charge sharing period; At least three gate drivers for supplying a scan pulse to the gate lines of the respective regions in units of at least one sub-frame period in accordance with the video signal supply period or the charge sharing period, ; And a timing controller for generating data and gate control signals and controlling the respective data and gate drivers.

The timing controller adjusts a high period and a low period of the SOE signal among the data control signals to supply the data to the data driver, and controls the phase of each of the first to third GOE signals in at least one subframe unit And supplies the converted signal to each of the at least three gate drivers.

Each of the gate drivers is connected to the gate lines of the respective regions corresponding to the respective gate drivers sequentially in accordance with at least one of the first to third GOE signals so as to be synchronized with the charge- And a scan pulse is synchronized with the video signal supply period to the gate lines of the regions where the scan pulses are sequentially supplied so as to be synchronized with the charge sharing period according to at least one of the first to third GOE signals, And a gate off voltage is supplied to the remaining regions excluding the two regions in which the respective scan pulses are sequentially supplied according to at least one of the first to third GOE signals.

Each of the gate drivers sequentially supplies scan pulses to the gate lines of one region during at least one sub-frame period to synchronize with the charge sharing period to display a black image according to charge sharing voltages from the data lines A scan pulse is sequentially supplied to the gate lines of the region where the black image is displayed during the at least one subframe period so as to be synchronized with the video signal supply period so that the input video is displayed according to the video signal from each data line, Off voltage is supplied to the gate lines of the remaining regions excluding the two regions in which the black image and the input image are displayed during the sub-frame period to maintain the previous sub-frame image.

Wherein each of the gate drivers includes at least one gate IC, and each of the gate ICs sequentially receives the at least one of the first to third GOE signals so as to be synchronized with the charge- A scan pulse is generated or the gate-off voltage is generated during at least one sub-frame period.

Wherein each of the data drivers includes at least one data IC and each of the data ICs supplies a video signal from the timing controller to each of the data lines during a supply period of the video signal in accordance with the SOE signal, And a charge sharing voltage is supplied to each of the data lines during the period.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display device including a liquid crystal panel having a plurality of pixels and divided into at least three regions, A method of driving a liquid crystal display (LCD) device having a controller, the method comprising: driving a plurality of data lines with a video signal supply period and a charge sharing period being the same; Sequentially supplying a scan pulse to the gate lines of the respective regions in synchronism with the video signal supplying period or the charge sharing period in units of at least one sub-frame period, or supplying a gate-off voltage during the one sub-frame period; And generating data and gate control signals to control the plurality of data and gate drivers.

Wherein the plurality of data and gate driver control stages adjust the high period and the low period of the SOE signal among the data control signals and supply the adjusted data to the data driver, And converting the phase into at least one subframe unit and supplying the converted signal to each of the plurality of gate drivers.

Wherein the gate line driving step of each of the regions sequentially applies scan pulses to the gate lines of the regions corresponding to the respective gate drivers in synchronism with the charge sharing period according to at least one of the first to third GOE signals Sequentially supplying scan pulses to the gate lines of the regions sequentially supplied with the scan pulses so that the scan pulses are synchronized with the video signal supply period in synchronization with the charge sharing period, And supplying a gate-off voltage to the remaining regions except for the two regions.

Wherein the step of driving the gate lines in each of the regions sequentially supplies scan pulses to the gate lines of one region during at least one subframe period in synchronism with the charge sharing period, A scan pulse is sequentially supplied to the gate lines of the region where the black image is displayed during the at least one sub-frame period so as to be synchronized with the video signal supply period, And maintaining the previous sub-frame image by supplying the gate-off voltage to the gate lines of the regions other than the two areas in which the black image and the input image are displayed during the sub-frame period .

The control step of each gate driver sequentially generates a scan pulse so as to synchronize with the charge sharing period or the video signal supply period according to at least one of the first to third GOE signals, And generating the gate-off voltage.

The control step of each data driver supplies a video signal from the timing controller to each of the data lines during a supply period of the video signal according to the SOE signal and supplies a charge sharing voltage to each data line during the charge sharing period The method includes the steps of:

The driving apparatus of the liquid crystal display apparatus and the driving method thereof according to the present invention having the above-described features have the following effects.

First, according to the present invention, a black image is displayed using a charge share voltage without a memory for storing black data, thereby simplifying the structure of the liquid crystal display device and reducing manufacturing cost.

Second, since the gate and the data line are driven by converting the pulse widths of the gate and data control signals, it is easy to convert the general driving method and the impulsive driving method.

Third, the present invention displays a black image by applying a charge sharing voltage to a first area that has retained an image of a previous sub frame, and displays an input image in a second area in which a black image is displayed in a previous sub frame, It is possible to improve the image quality by eliminating the operation flow phenomenon of the image. Accordingly, the present invention makes the moving display image more clear and displays the still image in a three-dimensional manner without noise.

Hereinafter, a driving apparatus and a driving method of a liquid crystal display according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram schematically showing a driving apparatus for a liquid crystal display according to an embodiment of the present invention.

The liquid crystal display device shown in FIG. 3 includes a liquid crystal panel 2 having a plurality of pixels and divided into at least three regions 1Do to 3Do; A plurality of data drivers for driving a plurality of data lines (DL1 to DLm) by adjusting a video signal supply period and a charge share period; Scan pulses are sequentially supplied to the gate lines (GL1 to GLn) of the respective regions (1Do to 3Do) in units of at least one subframe period in accordance with the video signal supply period or the charge sharing period, At least three gate drivers for supplying an off voltage; And a timing controller (8) for generating data and gate control signals and controlling the plurality of data drivers and each gate driver.

When the liquid crystal panel 2 is divided into at least three regions, for example, the first to third regions 1Do to 3Do, the first gate driver of each of the gate drivers is driven during the first to third sub frame periods Scan pulses are sequentially supplied to the gate lines of the first region 1Do in synchronization with the video signal supply period during the first sub frame period to display the input video. Next, the gate-off voltage is supplied to the gate lines of the first region 1Do during the second sub-frame period to hold the previous sub-frame image, and sequentially synchronized with the charge sharing period during the third sub- A scan pulse is supplied so that a black image is displayed in the first region 1Do according to the charge sharing voltage.

The second gate driver sequentially supplies scan pulses to the gate lines of the second region 2Do during the first sub frame period of the first to third sub frame periods to synchronize with the charge sharing period, Black images are sequentially displayed. Next, scan pulses are sequentially supplied to the gate lines of the second region 2Do so as to be synchronized with the video signal supplying period during the second sub-frame period to sequentially display the input video, and during the third sub-frame period Off voltage to maintain the image of the previous sub-frame.

The third gate driver supplies the gate-off voltage to the gate lines of the third region 3Do during the first sub-frame period of the first through third sub-frame periods to sustain the image of the previous sub-frame. Next, scan pulses are sequentially supplied to be synchronized with the charge sharing period during the second sub frame period to sequentially display a black image, and a third region The scan lines are sequentially supplied to the gate lines of the scan lines 3DO to sequentially display the input image.

Although not shown, the liquid crystal panel 2 can be divided into a plurality of regions according to the number and resolution of the gate driving units. In other words, the liquid crystal panel 2 can be divided into at least three regions, and the remaining regions other than the region where the input image is displayed or the black image is displayed can be driven to hold the image of the previous sub-frame.

In other words, when the input image is displayed in the first area 1Do and the black image is displayed in the second area 2Do, the areas over the fourth area are displayed in the same manner as the third area 3Do, . When the input image is displayed in the second area 2Do in which the black image is displayed and the black image is displayed in the third area 3Do that has kept the image of the previous sub frame, The image of the previous sub-frame is maintained by the same operation as the area 1Do. Similarly, when the input image is displayed in the third area 3Do in which the black image is displayed and the black image is displayed in the fourth area, the first area 1Do and the fifth area and more areas are the same as the second area 2Do And the image of the previous sub-frame is maintained by the operation. In this manner, when the area in which the input image is displayed and the area in which the black image is displayed are sequentially shifted, the remaining areas retain the images of the previous sub-frame. However, for convenience of description, only the case of the first to third regions will be described in detail below.

The data driver includes a plurality of data ICs (D-IC1 to D-IC5). Here, a plurality of data ICs (D-IC1 to D-IC5) are respectively mounted on the data circuit film 4 and connected between the liquid crystal panel 2 and the data PCB (D_PCB).

The first to third gate drivers may include first to third gate ICs (G-IC1 to G-IC3), respectively. Here, each of the first to third gate ICs (G-IC1 to G-IC3) is mounted on the gate circuit film 6 and connected to the liquid crystal panel 2. [

The data and gate circuit films 4 and 6 may be a TCP (Tape Carrier Package) film or a COF film. The data and gate circuit films 4 and 6 are attached between the data PCB D_PCB and the liquid crystal panel 4 by a TAB (Tape Automated Bonding) method.

The plurality of data ICs D-IC1 to D-IC5 are connected to the timing controller 8 via the data circuit film 4 and the data PCB D_PCB, and the first to third gate ICs G-IC1 to G IC3 are connected to the timing controller 8 via the gate circuit film 6, the liquid crystal panel 2, the data circuit film 4 and the data PCB D_PCB. Here, the numbers of the gate and data integrated circuits (G-IC1 to G-IC3, D-IC1 to D-IC5) are not limited to those shown in Fig.

The timing controller 8 is mounted on a data PCB D_PCB or mounted on a main PCB not shown and connected to a data PCB D_PCB via an FPC.

The liquid crystal panel 2 includes a thin film transistor (TFT) formed in each pixel region defined by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm, a liquid crystal capacitor (Clc). The liquid crystal capacitor Clc is composed of a pixel electrode connected to the TFT, and a common electrode arranged between the pixel electrode and the liquid crystal. The TFT supplies a video signal from each of the data lines DL1 to DLm to the pixel electrode in response to a scan pulse from each of the gate lines GL1 to GLn. The liquid crystal capacitor Clc charges the difference voltage between the video signal supplied to the pixel electrode and the reference common voltage supplied to the common electrode, and adjusts the light transmittance by varying the arrangement of the liquid crystal molecules according to the difference voltage to implement the gradation . The storage capacitor Cst is connected in parallel to the liquid crystal capacitor Clc so that the voltage charged in the liquid crystal capacitor Clc is maintained until the next data signal is supplied. The storage capacitor Cst may be formed by overlapping the pixel electrode with the previous gate line with the insulating film interposed therebetween, or the pixel electrode may be formed by overlapping the storage line with the insulating film interposed therebetween. Hereinafter, a liquid crystal panel 2 having a storage on command structure in which a storage capacitor Cst formed in parallel with the liquid crystal capacitor Clc, that is, a storage capacitor Cst is formed between the pixel electrode and the storage line is described as an example .

A plurality of data ICs (D-IC1 to D-IC5) provided in the data driver are supplied with a data control signal from the timing controller 8, for example, a source start signal SSP, a source shift clock SSC, A source shift clock (SOA), a source output enable (SOE) signal, and the like. In other words, each of the data ICs (D-IC1 to D-IC5) latches the digital data signal inputted in accordance with the SSC, and then outputs it in units of horizontal lines in response to the SOE signal inputted through the timing controller 8 . Then, each of the data ICs (D-IC1 to D-IC5) converts the digital data signal in the horizontal line unit into an analog data voltage, that is, a video signal and outputs it. Here, the SOE signal supplied from the timing controller 8 is a signal in which the high period and the low period are converted in accordance with the characteristics of the liquid crystal panel 2 and the luminance component. Accordingly, each data line DL1 to DLm is driven so that the period during which the video signal is supplied and the charge sharing period are changed according to the high or low period of the converted SOE signal. For example, a plurality of data ICs (D-IC1 to D-IC5) supply a charge sharing voltage to the data lines DL1 to DLm in the high period of the SOE signal, To the data lines DL1 to DLm. Here, the charge sharing voltage may be a common voltage input from the outside, or a plurality of data lines DL1 to DLm may be shorted to be an average voltage of the data lines DL1 to DLm. Hereinafter, for convenience of description, only the case where the SOE signal is converted so that the video signal input period and the charge share period become the same will be described as an example.

Each of the gate ICs (G-IC1 to G-IC3) provided in each gate driving unit receives a gate control signal from the timing controller 8, for example, a gate start signal GSP, a gate shift clock GSC A gate shift clock, and first to third gate output enable signals GOE1 to GOE3 to supply gate pulses or gate low voltages to the gate lines GL1 to GLn. In other words, each of the gate ICs (G-IC1 to G-IC3) shifts the GSP from the timing controller 8 according to the GSC to sequentially supply the gate pulse of the gate high voltage to the gate lines GL1 to GLn do. A gate low voltage is supplied during a period in which no scan pulse is supplied to each of the gate lines GL1 to GLn.

More specifically, the first gate IC (G-IC1) is controlled so as to be synchronized with the period during which the video signals are supplied to the respective data lines (DL1 to DLm) during the first sub frame period of the first to third sub frame periods And the scan pulses are sequentially supplied to the gate lines of the first region 1Do. The gate-off voltage is supplied to the gate lines of the first region 1Do during the second sub-frame period, and the scan pulses are sequentially supplied to be synchronized with the charge sharing period during the third sub-frame period. Here, in the third sub frame period, the charge sharing voltage may be applied to each pixel through the data lines DL1 to DLm. Therefore, the charge sharing period and the scan pulse need not necessarily be synchronized with the supply period.

On the other hand, in the second gate IC (G-IC2), the charge sharing voltages of the data lines DL1 to DLm are supplied to the pixels during the first sub frame period of the first to third sub frame periods, The scan lines are sequentially supplied with the scan pulses. Here, the scan pulses sequentially supplied to the second region 2Do may be supplied to be delayed by at least one phase difference from the scan pulses sequentially supplied to the first region 1Do. During the second sub frame period, scan pulses are sequentially supplied to the gate lines of the second region 2Do to synchronize with the video signal supply period, and the gate off voltage is supplied during the third sub frame period. Similarly, in the first sub frame period, the charge share voltages may be applied to the respective pixels through the data lines DL1 to DLm.

Also, the third gate IC (G-IC3) causes the gate line of the third region 3Do to be maintained at the gate-low voltage during the first sub frame period of the first to third sub frame periods. During the second sub frame period, the scan pulse is sequentially supplied so that the charge sharing voltages of the data lines DL1 to DLm are supplied to the respective pixels, and the third And sequentially supplies scan pulses to the gate lines of the region 3Do.

The first to third gate ICs (G-IC1 to G-IC3) will be described later in detail with reference to the accompanying drawings.

The timing controller 8 arranges image data from the outside so as to be suitable for driving the liquid crystal panel 2, and supplies the image data to the data ICs (D-IC1 to D-IC5) in units of horizontal lines or frames. The timing controller 8 generates the gate control signal GCS using the dot clock DCLK, the data enable signal DE and the horizontal and vertical synchronization signals Hsync and Vsync input from the outside, IC1 through D-IC5 by controlling the first to third gate ICs G-IC1 to G-IC3 and the data control signal DCS.

More specifically, the timing controller 8 generates GOE1 to GOE3, GSP, and GSC using a dot clock DCLK and a vertical synchronization signal Vsync input from the outside, and then, (G-IC1 to G-IC3). The timing controller 8 receives the SOE signal having the high and low periods converted by using the dot clock DCLK, the data enable signal DE and the horizontal synchronization signal Hsync input from the outside, for example, The SOE signal is converted so that the high and low periods are identical, and then supplied to each of the first to fifth data ICs (D-IC1 to D-IC5).

FIG. 4 is a configuration diagram specifically showing the timing controller and the first to third gate ICs shown in FIG. 3, and FIG. 5 is a driving waveform diagram of a liquid crystal display device according to an embodiment of the present invention.

The timing controller 8 shown in Fig. 4 uses the dot clock DCLK, the data enable signal DE and the horizontal and vertical synchronization signals Hsync and Vsync input from the outside to generate GSP, GSC and GOE1 to GOE3 . The GSP is supplied sequentially to the first to third gate ICs (G-IC1 to G-IC3) via the first gate IC (G-IC1) As shown in FIG. Also, the timing controller 8 may convert the high and low periods of the SOE signal to be equal to each other, and convert the high period of the SOE signal to be shorter than the low period, as shown by O_SOE. Then, by supplying the converted SOE signals to the respective data ICs (D-IC1 to D-IC5), the supply periods of the video signals and the charge sharing periods of the data ICs (D-IC1 to D- Thereby driving the data lines DL1 to DLm. When the O_SOE signal is supplied to each of the data ICs (D-IC1 to D-IC5), the charge share period becomes shorter than the video signal supply period.

5, the timing controller 8 converts the phases of the GOE1 to GOE3 signals in units of at least one subframe, and outputs them to the first to third gate ICs (G-IC1 to G-IC3) Supply. For example, during the first sub-frame period, the GOE1 signal is generated so as to have a phase opposite to that of the SOE signal and supplied to the first gate IC (G-IC1). The GOE2 signal is generated so as to have a phase opposite to that of the GOE1 signal, that is, the same phase as the SOE signal, to be supplied to the second gate IC (G-IC2), and the GOE3 signal is maintained at the high level during the first sub- To the third gate IC (G-IC3). Here, the GOE2 signal may be generated so as to have opposite phases by delaying the GOE1 signal for at least one clock pulse period.

Thereafter, during the second sub frame period, the GOE1 signal is maintained at the high level and supplied to the first gate IC (G-IC1). The GOE2 signal may be generated to have the same phase as the SOE signal and may be supplied to the second gate IC (G-IC2). The GOE3 signal may be generated to have a phase opposite to that of the GOE2 signal, . Here, the GOE3 signal can be generated so as to have opposite phases by delaying the GOE2 signal for at least one clock pulse period.

Next, during the third sub frame period, the GOE1 signal can be generated to have the same phase as the SOE signal and supplied to the first gate IC (G-IC1). The GOE2 signal can be supplied to the second gate IC (G-IC2) while maintaining the high level during the third sub-frame period, and the GOE3 signal is generated so as to have a phase opposite to that of the GOE1 signal, G-IC3). Here, the GOE3 signal can be generated so as to have opposite phases by delaying the GOE1 signal for at least one clock pulse period. The phase difference and the degree of delay of each of the GOE1 to GOE3 signals described above are not limited as shown in Fig. 5 because they can be changed depending on the situation of the signals to be the same as or opposite to the SOE signal.

On the other hand, the plurality of data ICs (D-IC1 to D-IC5) latch the digital image data in the high section of the SOE signal in response to the converted SOE signal, convert the digital image data into the video signal in the low section of the SOE signal And output to the respective data lines DL1 to DLm. Accordingly, each of the data lines DL1 to DLm is held at the charge sharing voltage in the high period of the SOE signal and charged in accordance with the level of the video signal in the low period of the SOE signal (D_Out).

The plurality of gate ICs (G-IC1 to G-IC3) are connected to each other to output scan pulses sequentially in accordance with the GOE1, GOE2 or GOE3 signals inputted to the GSP and GSC, respectively, or a gate low voltage, The gate-off voltage is outputted. In other words, the first gate IC (G-IC1) sequentially supplies the gate line of the corresponding region, for example, the first region 1Do, in synchronization with the video signal supply period or the charge sharing period in accordance with the GSP, GSC and GOE1 signals And outputs a gate-off voltage during one sub-frame period (G1_Out). The second gate IC (G-IC2) sequentially outputs scan pulses to the gate lines of the second region 2Do in synchronization with the video signal supply period or the charge sharing period according to the GSP, GSC and GOE2 signals, And outputs a gate-off voltage during the frame period (G2_Out). The third gate IC (G-IC3) sequentially outputs scan pulses to the gate lines of the third region 3Do in synchronization with the video signal supply period or the charge sharing period according to the GSP, GSC and GOE3 signals, And outputs a gate-off voltage during the frame period (G3_Out).

6A to 6C are views showing a display screen of a liquid crystal panel according to an embodiment of the present invention.

The driving method of the liquid crystal display according to the embodiment of the present invention will be described in more detail with reference to the display screen of the liquid crystal panel 2 shown in FIGS. 6A to 6C and the following Table 1.

First, as shown in FIG. 6A, during the first sub frame period of FIG. 5 and Table 1, a first gate driver IC (G-IC1) sequentially applies a first gate signal The input image is displayed. A black image is sequentially displayed in the second region 2Do in which the plurality of gate lines are sequentially driven by the second gate IC G-IC2 according to the charge share voltage, and the third gate IC (G-IC3) The third region 3Do in which the plurality of gate lines are driven by the first region maintains the image of the previous sub-frame.

Specifically, during the first sub frame period, the plurality of data ICs (D-IC1 to D-IC5) output video signals to the respective data lines DL1 to DLm in the same period as the charge sharing period according to the converted SOE signal do. Accordingly, the voltage (D_Out) level applied to each of the data lines DL1 to DLm is maintained at the charge share voltage in the high period of the SOE signal, and is changed to the level of the video signal in the low period of the SOE signal.

At this time, the first gate IC (G-IC1) sequentially outputs the scan pulse G1_Out to the gate lines of the first region 1Do so as to be synchronized with the period in which the video signals are applied to the data lines DL1 to DLm do. Accordingly, the pixels of the first region 1Do sequentially display the video signals from the data lines DL1 to DLm in response to the sequentially input scan pulses.

In addition, the second gate IC (G-IC2) sequentially applies the scan pulses G2_Out (G2_Out) to the gate lines of the second region (2Do) so that the charge sharing voltages are applied to the respective pixels through the data lines ). Accordingly, the pixels of the second area 2Do sequentially display the black images according to the charge share voltages inputted from the data lines DL1 to DLm in response to the sequentially input scan pulse G2_Out. Here, since the level of the charge share voltage may be input at the same level as the level of the common voltage applied to the liquid crystal panel 2, and converted into a level similar to or the same as the common voltage level, The black image is displayed according to the share voltage.

The third gate IC (G-IC3) supplies the gate line voltage, that is, the gate-off voltage, to the gate lines of the third region 3Do during the first sub frame period so that the gate lines of the third region 3Do So that the gate-off voltage is maintained. Accordingly, the pixels of the third region Do maintain the image of the previous sub-frame.

As shown in FIG. 6B, the first region 1Do in which a plurality of gate lines are driven by the first gate IC (G-IC1) during the second sub frame period of FIG. 5 and Table 1, . An input image is sequentially displayed in a second region 2Do in which a plurality of gate lines are sequentially driven by the second gate IC (G-IC2), and a plurality of gates A black image is sequentially displayed in the third area 3Do where the line is driven.

Specifically, even during the second sub frame period, the plurality of data ICs (D-IC1 to D-IC5) output video signals to the respective data lines DL1 to DLm in the same period as the charge sharing period according to the converted SOE signals . Accordingly, the voltage (D_Out) level applied to each of the data lines DL1 to DLm is maintained at the charge share voltage in the high period of the SOE signal and is charged to the level of the video signal in the low period of the SOE signal.

At this time, the first gate IC (G-IC1) supplies the gate-off voltage to the gate lines of the first region 1Do during the second sub-frame period so that the gate lines of the first region 1Do are maintained at the gate- . Accordingly, the pixels of the first area 1Do maintain the image of the previous sub-frame.

The second gate IC G-IC2 sequentially outputs the scan pulse G2_Out to the gate lines of the second region 2Do so as to be synchronized with the period during which the video signal is applied to the data lines DL1 to DLm. Accordingly, the pixels of the second area 2Do sequentially display the video signals from the data lines DL1 to DLm in response to the sequentially input scan pulses.

The third gate IC (G-IC3) sequentially applies the scan pulse (G3_Out) to the gate lines of the third region (3Do) so that a charge sharing voltage is applied to each pixel through each data line (DL1 to DLm) . Accordingly, the pixels of the third area 3Do sequentially display the black images according to the charge sharing voltages inputted from the data lines DL1 to DLm in response to the sequentially input scan pulses. Since the level of the charge sharing voltage may be supplied in the same level as the common voltage applied to the liquid crystal panel 2 and is similar to or the same as the common voltage level, The image is displayed.

As shown in FIG. 6C, the first region 1Do in which a plurality of gate lines are driven by the first gate IC (G-IC1) during the third sub frame period of FIG. 5 and Table 1, Is displayed. The second region 2Do in which a plurality of gate lines are sequentially driven by the second gate IC (G-IC2) holds the image of the previous sub-frame, and a plurality The input image is sequentially displayed in the third area 3Do where the gate line of the display device is driven.

Specifically, even during the third sub frame period, the plurality of data ICs (D-IC1 to D-IC5) output video signals to the respective data lines DL1 to DLm in the same period as the charge sharing period according to the converted SOE signals . Accordingly, the voltage (D_Out) level applied to each of the data lines DL1 to DLm is maintained at the charge share voltage in the high period of the SOE signal, and is changed to the level of the video signal in the low period of the SOE signal.

At this time, the first gate IC G-IC1 sequentially applies the scan pulse G1_Out to the gate lines of the first region 1Do so that the charge sharing voltage is applied to the respective pixels through the data lines DL1 to DLm, . Accordingly, the pixels of the first region 1Do sequentially display the black images according to the charge share voltages inputted from the data lines DL1 to DLm in response to the scan pulses sequentially input. Similarly, since the level of the charge share voltage is equal to or similar to the level of the common voltage applied to the liquid crystal panel 2, the pixels of the first region 1Do display the black image according to the charge share voltage.

On the other hand, the second gate IC (G-IC2) supplies the gate-off voltage to the gate lines of the second region 2Do during the third sub-frame period so that the gate lines of the second region 2Do are turned off . Accordingly, the pixels of the second area 2Do maintain the image of the previous sub-frame.

The third gate IC (G-IC3) sequentially outputs the scan pulse (G3_Out) to the gate lines of the third region (3Do) so as to be synchronized with the period in which the video signal is applied to the data lines (DL1 to DLm) do. Accordingly, the pixels of the third area 3Do sequentially display the video signals from the data lines DL1 to DLm in response to the sequentially input scan pulses.

Meanwhile, although not shown, when the liquid crystal panel 2 is divided into the areas of the first to third areas 1Do to 3Do, as shown in Table 2, in addition to the area where the input image is displayed or the black image is displayed, May be driven to hold the image of the previous sub-frame.

Specifically, when the input image is displayed in the first area 1Do and the black image is displayed in the second area 2Do, the areas of the third area or more maintain the image of the previous sub-frame. In the case of the second sub-frame in which the input image is displayed in the second area 2Do and the black image is displayed in the third area 3Do, The image is maintained. Similarly, in the case of the third sub-frame in which the input image is displayed in the third area 3Do and the black image is displayed in the fourth area, the first and second areas 1Do, And the image of the frame is maintained. In this manner, when the area in which the input image is displayed and the area in which the black image is displayed are sequentially shifted, the remaining areas retain the images of the previous sub-frame.

As described above, in the driving apparatus for a liquid crystal display according to the embodiment of the present invention, each frame is divided into three or more subframes and driven, and the liquid crystal panel 2 is also dividedly driven in three or more areas. The input image or the black image may be shifted or displayed in each region in at least one subframe unit, or an image of the previous subframe may be maintained. Accordingly, the present invention can simplify the structure of the liquid crystal display device and reduce the manufacturing cost, as well as the gate and data lines GL1 to GLn, DL1 to DLm by converting the phase and pulse width of the gate and data control signals, It is easy to convert the general driving method and the impulsive driving method. Meanwhile, since the present invention can improve the image quality by eliminating the operation flow phenomenon of the image, the moving display image can be made more clear and the still image can be displayed in a three-dimensional manner without noise.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

1 shows a data addressing method according to the prior art;

Fig. 2 is a driving waveform diagram for implementing the data addressing method shown in Fig. 1. Fig.

3 is a block diagram schematically showing a driving apparatus of a liquid crystal display according to an embodiment of the present invention.

4 is a configuration diagram specifically showing the timing controller and the first to third gate ICs shown in FIG. 3;

5 is a driving waveform diagram of a liquid crystal display according to an embodiment of the present invention.

6A to 6C are views showing a display screen of a liquid crystal panel according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

2: liquid crystal panel 4: data circuit film

6: gate circuit film 8: timing controller

D-IC1 to D-IC5: First to fifth data ICs

G-IC1 to G-IC3: First to third gate ICs

1Do to 3Do: first to third regions

GOE1 to GOE3: The first to third gate output enable signals

D_PCB: Data PCB

Claims (12)

A liquid crystal panel having a plurality of pixels and divided into at least three regions; A plurality of data drivers for driving a plurality of data lines by adjusting a video signal supply period and a charge sharing period; At least three gate drivers for supplying a scan pulse to the gate lines of the respective regions in units of at least one sub-frame period in accordance with the video signal supply period or the charge sharing period, ; And And a timing controller for generating data and gate control signals and controlling the respective data and gate drivers, The timing controller Generating the data control signal so that the charge sharing period is shorter than or equal to the video signal supply period, and generating the scan pulse synchronized with the charge sharing period or the video signal supply period for each of the at least three areas, Or generates the gate control signal so that only the gate-off voltage is output. The method according to claim 1, The timing controller And a data driver for supplying the data driver with the high and low periods of the SOE signal, Wherein the phase of each of the first to third GOE signals of the gate control signal is converted into at least one subframe unit and supplied to each of the plurality of gate drivers. 3. The method of claim 2, Each of the gate drivers Sequentially supplying scan pulses to the gate lines of the regions corresponding to the respective gate drivers sequentially in synchronism with the charge sharing period according to at least one of the first to third GOE signals, Sequentially supplying scan pulses to the gate lines of the regions sequentially supplied with the scan pulses so as to be synchronized with the charge sharing period according to at least one of the first to third GOE signals, Off voltage is supplied to the remaining regions except for the two regions in which the respective scan pulses are sequentially supplied according to at least one of the first to third GOE signals. The method of claim 3, Each of the gate drivers A scan pulse is sequentially supplied to the gate lines of one region during the at least one sub-frame period to synchronize with the charge sharing period so that a black image is displayed according to a charge sharing voltage from each data line, A scan pulse is sequentially supplied to the gate lines of the region where the black image is displayed during the at least one subframe period so as to be synchronized with the video signal supply period so that the input video is displayed according to the video signal from each data line, Off voltage is supplied to the gate lines of the remaining regions excluding the two regions in which the black image and the input image are displayed during the sub-frame period to sustain the previous sub-frame image. Device. 3. The method of claim 2, Each of the gate drivers And each of the gate ICs sequentially generates a scan pulse so as to be synchronized with the charge sharing period or the video signal supply period according to at least one of the first to third GOE signals, And the gate-off voltage is generated during one sub-frame period. 3. The method of claim 2, Each of the data drivers Wherein each of the data ICs supplies a video signal from the timing controller to each of the data lines during a supply period of the video signal in accordance with the SOE signal and supplies the charge sharing voltage during the charge sharing period And supplies the data to each of the data lines. A driving method of a liquid crystal display device including a liquid crystal panel having a plurality of pixels and divided into at least three regions, and a timing controller for controlling a plurality of gates and a data driver, Driving a plurality of data lines by adjusting a video signal supply period and a charge sharing period; Sequentially supplying a scan pulse to the gate lines of the respective regions in synchronism with the video signal supplying period or the charge sharing period in units of at least one sub-frame period, or supplying a gate-off voltage during the one sub-frame period; And And generating data and gate control signals to control the plurality of data and gate drivers, The plurality of data and gate driver control steps Generating the data control signal so that the charge sharing period is shorter than or equal to the video signal supply period, and generating the scan pulse synchronized with the charge sharing period or the video signal supply period for each of the at least three areas, Or the gate control signal is generated so that only the gate-off voltage is output. 8. The method of claim 7, The plurality of data and gate driver control steps Adjusting a high period and a low period of the SOE signal among the data control signals and supplying the adjusted data to the data driver; And converting the phases of at least first to third GOE signals of the gate control signals into at least one subframe unit and supplying the converted signals to each of the plurality of gate driving units. 9. The method of claim 8, The gate line driving step of each of the regions Sequentially supplying scan pulses to the gate lines of the regions corresponding to the respective gate drivers in synchronism with the charge sharing period according to at least one of the first to third GOE signals, Sequentially supplying scan pulses to the gate lines of the regions to which the scan pulses are sequentially supplied so as to be synchronized with the charge sharing period so as to be synchronized with the video signal supply period, And supplying a gate-off voltage to the remaining regions excluding the two regions in which the respective scan pulses are sequentially supplied. 10. The method of claim 9, The gate line driving step of each of the regions Sequentially supplying scan pulses to the gate lines of one region during the at least one subframe period in synchronism with the charge sharing period so that a black image is displayed according to a charge sharing voltage from each data line, Sequentially supplying scan pulses to the gate lines of the region where the black image is displayed during the at least one sub-frame period so as to be synchronized with the video signal supplying period so that the input video is displayed according to the video signal from each data line, And And maintaining the previous sub-frame image by supplying the gate-off voltage to the gate lines of the regions other than the two regions in which the black image and the input image are displayed during the sub-frame period. A method of driving a device. 9. The method of claim 8, The control step of each gate driver Sequentially generating scan pulses to synchronize with the charge sharing period or the image signal supply period according to at least one of the first to third GOE signals or generating the gate off voltage during at least one sub frame period And a driving method of the liquid crystal display device. 9. The method of claim 8, The control step of each data driver Supplying a video signal from the timing controller to each of the data lines during a supply period of the video signal according to the SOE signal and supplying a charge sharing voltage to each of the data lines during the charge sharing period, And a driving method of the liquid crystal display device.

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