KR20100045042A - Address generation method, address generation slave device, master slave system and multi master slave system - Google Patents

Abstract

PURPOSE: A method for generating an address, an address generation slave device, a master slave system and a multi master slave system thereof are provided to reduce address alteration on a bus circuit by creating an address for accessing a memory with a previous access address. CONSTITUTION: An address increase/decrease value register(620) outputs an address gradient value. An access address storage unit(630) outputs the first access address as a previous access address. An address operation unit(640) occurs a generation address with operation of an address gradient value about the previous access address. A multiplexer(650) selects one between a master transmission address and the generated address. The multiplexer outputs the second access address.

Description

Address generation method, address generation slave device, master slave system and multi master slave system {ADDRESS GENERATION METHOD, ADDRESS GENERATION SLAVE DEVICE, MASTER SLAVE SYSTEM AND MULTI MASTER SLAVE SYSTEM}

The present invention relates to an address and a master slave system. More specifically, the present invention relates to an address generation slave device, a master slave system, a multi master slave system, and an address generation method, in which a slave device can generate an access address using a previous access address.

Recently, a multi-master multi-slave system for transmitting and receiving data between a plurality of master devices and a plurality of slave devices via a bus has been widely used. Each master device may have a different memory access pattern when accessing memory in a slave. That is, they may have different memory access address patterns.

1 is a block diagram illustrating a conventional multi-master multi-slave system.

Referring to FIG. 1, the multi master multi slave system 100 includes a first master device 110, a second master device 120, a first slave device 130, a second slave device 140, and a bus circuit ( 150, the bus circuit 150 includes a master transmit address multiplexer 160, a write data multiplexer 170, an arbiter 180, and a read data multiplexer 190.

The first master device 110 transmits a first master transmission address MA1 for accessing the memory in the first slave device 130 and the second slave device 140. The second master device 110 transmits a second master send address MA2 for accessing the memory in the first slave device 130 and the second slave device 140. The master transmission address multiplexer 160 in the bus circuit 150 receives the first master transmission address MA1 and the second master transmission address MA2, and applies the address bus control signal ABC output from the arbiter 180. In response, one of the first master transmission address MA1 or the second master transmission address MA2 is transmitted to the first slave device 130 and the second slave device 140 through the address bus ABUS.

The first slave device 130 and the second slave device 140 that have received one of the first master transmission address MA1 or the second master transmission address MA2 are either the first master device 110 or the second master device. The write data MD1 and MD2 transmitted by the 120 are written into the memory through the write data multiplexer 170 and the write data bus WDBUS, or the read data multiplexer reads the read data SD1 and SD2 stored from the memory. The read data SDm selected by 190 is transmitted to the first master device 110 or the second master device 120 through the read data bus RDBUS.

2 is a timing diagram illustrating a procedure of transferring data between a master and a slave.

Referring to FIG. 2, first, the first master device 110 or the second master device 120 sends a bus use request signal to the arbiter 160 in the bus circuit 150 in a request and grant phase. (REQ), and the arbiter 160 transmits a bus license signal GRANT that gives the bus device a right to use the bus. The master device receiving the bus license signal GRANT transmits the memory access address ADDR, the address control signal, and the address mode signal to the first slave device 130 or the second slave device 140 in the address phase ADDR phase. send. Finally, in the data phase, in the write mode, the master device writes data DATA to the memory, and in the read mode, the slave device reads data from the memory and transmits the data DATA to the master device.

However, when the first master device 110 or the second master device 120 transmits the memory access address ADDR through the address bus ABUS each time the memory device accesses the memory, the address value on the address bus ABUS is transmitted. Must be changed from time to time, which causes a lot of power consumption.

Accordingly, what is needed are circuits, systems, and methods that can access a memory without going through an address bus in a bus circuit.

In order to solve the above problem, the present invention provides an address generation slave device capable of generating an address for accessing a memory using a previous access address.

The present invention also provides a master slave system capable of generating an address that accesses a memory using a previous access address.

The present invention also provides a multi-master slave system capable of generating an address that accesses a memory using a previous access address.

The present invention also provides an address generation method that can generate an address that accesses a memory using a previous access address.

In order to achieve the above object, an address generation slave device according to an embodiment of the present invention includes an address increment value register, an access address storage unit, an address calculation unit, and a multiplexer. The address increase and decrease value register stores an address increase and decrease value, when the master device accesses the memory, receives an address control signal indicating a pattern of addresses, and outputs the address increase and decrease value based on the address control signal. The access address storage unit receives and stores a first access address, and outputs the first access address as a previous access address. The address calculator generates a generation address by calculating the address increase / decrease value output from the address increase / decrease value register to the previous access address output from the access address storage unit based on the address control signal. The multiplexer is coupled between the access address storage and the address calculator to receive a master transmit address and the generation address sent by the master device to access the memory, and transmit when the master device accesses the memory Based on the address mode signal, one of the master transmission address and the generation address is selected to output a second access address. The pattern of addresses may have a constant increasing trend and a constant decreasing trend.

The address calculator is configured to add the previous access address and the address increase / decrease value when the pattern of addresses increases, and to subtract the previous access address and the address increase / decrease value when the pattern of addresses decreases. It may include a retarder.

The address control signal may include size information of the addresses and trend information indicating whether the addresses have an increasing trend or a decreasing trend.

The address mode signal controls the multiplexer to output the master transmission address as the second access address before the generation address is generated, and the multiplexer generates the master transmission address and the generation after the generation address is generated. One of the addresses may be selected and controlled to be output as the second access address.

The access address storage unit may include a de-flip flop that receives the address mode signal through an enable terminal and outputs the first access address as the previous access address according to the address mode signal.

The master slave system according to an embodiment of the present invention includes a master device, an address increment value register, an access address storage unit, an address operator and a multiplexer. When the master device accesses the memory, it transmits an address control signal representing a pattern of addresses. The address increase and decrease value register stores an address increase and decrease value, and outputs the address increase and decrease value based on the address control signal. The access address storage unit receives and stores a first access address, and outputs the first access address as a previous access address. The address calculator generates a generation address by calculating the address increase / decrease value output from the address increase / decrease value register to the previous access address output from the access address storage unit based on the address control signal. The multiplexer is coupled between the access address storage and the address calculator to receive a master transmit address and the generation address sent by the master device to access the memory, and transmit when the master device accesses the memory Based on the address mode signal, one of the master transmission address and the generation address is selected to output a second access address. The pattern of addresses may have a constant increasing trend and a constant decreasing trend.

The address calculator is configured to add the previous access address and the address increase / decrease value when the pattern of addresses increases, and to subtract the previous access address and the address increase / decrease value when the pattern of addresses decreases. It may include a retarder.

The address control signal may include size information of the addresses and trend information indicating whether the addresses have an increasing trend or a decreasing trend.

The address mode signal controls the multiplexer to output the master transmission address as the second access address before the generation address is generated, and the multiplexer generates the master transmission address and the generation after the generation address is generated. One of the addresses may be selected and controlled to be output as the second access address.

The access address storage unit may include a de-flip flop that receives the address mode signal through an enable terminal and outputs the first access address as the previous access address according to the address mode signal.

The multi-master slave system according to an embodiment of the present invention includes a plurality of master devices, an address increment value register, an access address storage unit, an address operation unit, and a multiplexer. When the master devices access the memory, they each transmit address control signals indicative of patterns of addresses. The address increase and decrease value register stores an address increase and decrease value, and outputs the address increase and decrease value based on the address control signal. The access address storage unit receives and stores a first access address, and outputs the first access address as a previous access address. The address calculator generates a generation address by calculating the address increase / decrease value output from the address increase / decrease value register to the previous access address output from the access address storage unit based on the address control signal. The multiplexer is coupled between the access address storage and the address calculator to receive a master transmission address and the generation address sent by each master device to access the memory, and each master device to the memory. On the basis of the address mode signal transmitted upon access, one of the master transmission address and the generation address is selected to output a second access address. The patterns of addresses may have different constant increasing trends and constant decreasing trends, respectively.

The address calculator is configured to add the previous access address and the address increase / decrease value when the pattern of addresses increases, and to subtract the previous access address and the address increase / decrease value when the pattern of addresses decreases. It may include a retarder.

The address control signal may include size information of the addresses and trend information indicating whether the addresses have an increasing trend or a decreasing trend.

The address mode signal controls the multiplexer to output the master transmission address as the second access address before the generation address is generated, and the multiplexer generates the master transmission address and the generation after the generation address is generated. One of the addresses may be selected and controlled to be output as the second access address.

A register for storing an address increase / decrease value and outputting the address increase / decrease value based on an address control signal transmitted from a master device according to an embodiment of the present invention, and receives a first access address and the first mode according to an address mode signal. An access address storage section for outputting an access address as a previous access address, an address calculating section for generating a generation address by calculating the address increment value to the previous access address based on the address control signal, and based on the address mode signal And a multiplexer for selecting one of a master transmission address transmitted by the master device and the generation address output by the operation unit and outputting a second access address, wherein the address generation method of the address generation circuit includes: Storing, by the dress increase / decrease value register, the address increase / decrease value, the address increase / decrease value register receive the address control signal from the master device, and the multiplexer and the access address store receive the address mode signal; An address increase / decrease value register outputting the address increase / decrease value based on the address control signal, wherein the access address storage outputs the first access address as the previous access address according to the address mode signal, An address calculating unit generating the generation address by calculating the address increment value to the previous access address based on the address control signal, and the multiplexer causes the master transmission address and the generation add Receiving a reply and selecting one of the master transmission address and the generation address based on the address mode signal to output the second access address.

In the address generation slave device, the master slave system, the multi-master slave system, and the address generation method according to an embodiment of the present invention, the slave device uses the previous access address in the memory even if the address is not received from the master device through the bus every time. The address can be generated to access, reducing power consumption by reducing address changes on the bus circuit. Accordingly, it is possible to reduce the power consumption by applying to the embedded system and the mobile system using the master slave system.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in. As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well. The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features It should be understood that it does not exclude in advance the possibility of the presence or addition of numbers, steps, operations, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram illustrating a multi-master slave system according to an embodiment of the present invention.

Referring to FIG. 3, the multi master slave system 300 may include a first master device 310, a second master device 320, a first slave device 330, a second slave device 340, and a bus circuit 350. ).

In the multi-master slave system 300 illustrated in FIG. 3, two master devices 310 and 320 and slave devices 330 and 340 are respectively shown, but the multi-master slave system 300 is not limited thereto. May include a plurality of master devices and slave devices.

The master devices 310 and 320 and the slave devices 330 and 340 transmit and receive data through the bus circuit 350. The structure and operation of the bus circuit 350 shown in FIG. 3 may be the same as the structure and operation of the bus circuit 150 shown in FIG. 1.

Each of the master devices 310 and 320 has a variety of characteristics, so that the pattern of addresses for accessing the memory in the slave devices 330 and 340 is different, and address control indicating the pattern of addresses when accessing the memory. Sends a signal to the slave devices 330, 340.

4A is an address pattern diagram of a first master device according to an embodiment of the present invention, and FIG. 4B is an address pattern diagram of a second master device according to an embodiment of the present invention.

4A and 4B, the master devices 310 and 320 have different address patterns, respectively. That is, the first master device 310 has a pattern that increases from 100 to 110 at intervals of two addresses in T0 to T5 and then increases from 100 to 110 again in T6 to T11 and the second master device ( 320) decreases from 105 to 100 at intervals of address 1 in T0 to T5 and then increases from 100 to 105 in T5 to T10.

5 is a block diagram illustrating an address generation slave device and a memory according to an embodiment of the present invention.

The address generation slave device 510 may be the first slave device 330 or the second slave device 340 shown in FIG. 3.

Referring to FIG. 5, the address generation slave device 510 generates an access address AADDR to access the memory 520 and based on the read / write control signal received from the master devices 310 and 320. To generate the memory control signal MC. The address generation slave device 510 accesses the memory 520 according to the access address AADDR and the memory control signal MC, and then reads data from the memory 520 to read the data to the master devices 310 and 320. Transmit or write data transmitted from master devices 310, 320. Memory 520 may be any storage device that is accessed by cache memory or addresses that have a tendency to constantly increase or decrease over time.

6 is a block diagram illustrating an address generation slave device according to an embodiment of the present invention.

Referring to FIG. 6, the address generation slave device 600 includes an address increment value register 620, an access address storage 630, an address operation unit 640, and a multiplexer 650.

The address increase / decrease value register 620 receives and stores an address increase / decrease value IDC from the outside, and receives an address control signal ADDRC indicating a pattern of addresses for the master device to access the memory. For example, the address control signal ADDRC may represent a pattern of addresses for the first master device 310 or the second master device 320 to access the memory 520 with a constant increasing trend and a constant decreasing trend. have. That is, the address control signal ADDRC may represent a pattern of addresses shown in FIGS. 4A and 4B.

The address control signal ADDRC includes trend information indicating whether the pattern of addresses has an increasing trend or a decreasing trend, and size information of the addresses. For example, the address control signal ADDRC may represent the address pattern illustrated in FIG. 4A, and may indicate information that the address pattern of the first master device 310 increases by two addresses from T0 to T5.

The address increase / decrease value register 620 outputs the address increase / decrease value IDC based on the received address control signal ADDRC. The access address storage unit 630 receives and stores the first access address AADDR1, which is the address that accessed the memory 520, and outputs the first access address AADDR1 as the previous access address PAADDR. The access address storage unit 630 may include a de-flip-flop 630 that receives the first access address AADDR1 and outputs it as a previous access address PAADDR.

The first access address AADDR1 may be a master transmission address MADDR or an address calculator transmitted by the first master device 310 or the second master device 320 through the bus circuit 350 to access the memory 520. It may be one of the generation addresses GADDR previously output by 640.

The multiplexer 650 connected between the access address storage unit 630 and the address operation unit 640 to select one of the master transmission address MADDR and the generation address GADDR to output as the first access address AADDR1 is an address. In response to the mode signal ADDRM, one of the master transmission address MADDR and the generation address GADDR is selected and outputted, and before the generation address GADDR is generated, the master transmission address MADDR rule first access address AADDR1 is generated. Output as For example, assuming that T0 shown in FIG. 4A is before the generation address GADDR is generated, the multiplexer 650 receives the master transmission address MADDR corresponding to 100 and receives the master transmission address MADDR. It can be output as the first access address AADDR1.

The address mode signal ADDRM controlling the output of the multiplexer 650 may have four modes including BUSY [00], IDLE [01], LDADDR [10], and SECADDR [11]. In the BUSY [00] and IDLE [01] modes, the access request to the memory 520 is ignored, and in the LDADDR [10] mode, the master transmission address MADDR is output as the first access address AADDR1 and SEQADDR [11]. In the] mode, the generation address GADDR output by the address calculator 640 is output as the first access address AADDR1.

Only in the LDADDR [10] and SEQADDR [11] modes, to the enable terminal EN of the access address storage unit 630 to transfer the first access address AADDR1 to the address calculation unit 640 as the previous access address PAADDR. An address mode signal ADDRM [1X] corresponding to the LDADDR [10] and SEQADDR [11] modes may be applied.

The address calculator 640 may convert the address increase / decrease value IDC output from the address increase / decrease value register 620 to the previous access address PAADDR output from the access address storage unit 630 based on the address control signal ADDRC. The operation generates a generation address GADDR. That is, the calculator 640 adds or subtracts the address increment value IDC to or from the previous access address PAADDR by using the trend information and the address size information indicated by the address control signal ADDRC. For example, the address operation unit 640 receives the master transmission address MADDR corresponding to the address 100 shown in FIG. 4A through the multiplexer 650 and the access address storage unit 630 as a previous access address PAADDR. The generation address GADDR may be output by adding the address address increment value IDC to the address 100 based on the address control signal ADDRC.

The address operation unit 640 calculates the sum of the previous access address PAADDR and the address increment value IDC when the pattern of addresses is increasing, and the previous access address PAADDR and the address increment value when the pattern of addresses is decreasing. And an adder, subtractor or adder to subtract the IDC).

The multiplexer 650 receives the generation address GADDR and the master transmission address MADDR output by the address calculating unit 640, and based on the address mode signal ADDRM, the multiplexer 650 receives the generation address GADDR and the master transmission address ( One of the MADDRs is selected to output the second access address AADDR2.

Here, the first access address AADDR1 is an address previously accessed to the memory before the second access address AADDR2, and is output from the multiplexer 650 before the second access address AADDR2 is output, thereby accessing the access address storage unit ( 630 is an address.

7 is a block diagram illustrating an address increase and decrease value register according to an embodiment of the present invention.

Referring to Fig. 7, the address increase / decrease value register 620 stores the address increase / decrease value IDC according to the address size SIZE. For example, if the address size (SIZE) is byte (BYTE), it has an address increment value (IDC) of the size corresponding to address 1, and if the address size (SIZE) is a half word (HALF WORD) Has an address increase / decrease value (IDC) of a size corresponding to, and if the address size (SIZE) is a word (WORD), it has an address increase / decrease value (IDC) of a size corresponding to address 4, and the address size (SIZE) is doubled. In the case of a word, it may have an address increment value IDC corresponding to eight addresses. Therefore, the address increase / decrease value register 620 may receive the address control signal ADDRC and output the address increase / decrease value IDC based on the address size information included in the address control signal ADDRC.

8 is a flowchart illustrating a method of generating an address according to an embodiment of the present invention.

Referring to Fig. 8, a register for storing an address increment value and outputting an address increment value based on an address control signal transmitted from a master device, receiving a first access address and outputting the first access address as a previous access address. On the basis of the access address storage unit, an address operation unit for calculating an address increment value to the previous access address based on the address control signal, and outputting a generation address, a master transmission address sent by the master device and a generation address output by the operation unit are selected. In the address generation method of the address generation circuit including the multiplexer which selects and outputs the second access address, the address increase / decrease value register first stores the address increase / decrease value (S810). For example, the address increase / decrease value has a size corresponding to address 1 when the address size is byte, has a size corresponding to address 2 when the address size is a half word, and 4 when the address size is a word. If the address size is a double word and the address size is a double word, it may have a size corresponding to eight addresses. Next, the address increase and decrease value register receives an address control signal from the master device, and the multiplexer and the access address storage unit receive an address mode signal (S820). The address increase / decrease value register outputs the address increase / decrease value based on the address control signal (S830). The access address storage unit receives the first access address according to the address mode signal and outputs the first access address as the previous access address (S840). The address calculator generates a generation address by calculating an address increment value to a previous access address based on the address control signal (S850). The multiplexer receives the master transmission address and the generation address, selects one of the master transmission address and the generation address according to the address mode signal, and outputs a second access address (S860). It is determined whether there is an access request to the memory from the master device, and thus it is necessary to generate an access address (S870). If it is necessary to generate an access address further (S870: Yes), the address increment value register receives an address control signal from the master device, and the multiplexer and the access address storage receive an address mode signal (S820). Repeat step S820 to step S870. If it is not necessary to generate an access address further (S870: No), the procedure ends.

Thus, in the address generation slave device, the master slave system, the multi master slave system, and the address generation method according to the present invention, the slave device accesses the memory by using the previous access address without receiving the address from the master device through the bus every time. Address can be generated.

According to the present invention, an address generating slave device, a master slave system, a multimaster slave system, and an address generating method are addresses in which a slave device accesses a memory using a previous access address without receiving an address from the master device via a bus each time. Can reduce the address change on the bus circuit to reduce power consumption. Accordingly, it is possible to reduce the power consumption by applying to the embedded system and the mobile system using the master slave system.

While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

1 is a block diagram illustrating a conventional multi-master multi-slave system.

2 is a timing diagram illustrating a procedure of transferring data between a master and a slave.

3 is a block diagram illustrating a multi-master slave system according to an embodiment of the present invention.

4A is an address pattern diagram of a first master device according to an embodiment of the present invention.

4B is an address pattern diagram of a second master device according to an embodiment of the present invention.

5 is a block diagram illustrating an address generation slave device and a memory according to an embodiment of the present invention.

6 is a block diagram illustrating an address generation slave device according to an embodiment of the present invention.

7 is a block diagram illustrating an address increase and decrease value register according to an embodiment of the present invention.

8 is a flowchart illustrating a method of generating an address according to an embodiment of the present invention.

Description of the main parts of the drawing

510: address generation slave device

520: memory

620: address increment value register

630: access address storage unit

640: address operation unit

650: multiplexer

Claims (15)

An address increase and decrease value register for storing an address increase and decrease value, when the master device accesses the memory, receiving an address control signal indicating a pattern of addresses, and outputting the address increase and decrease value based on the address control signal; An access address storage unit for receiving and storing an access address and outputting the first access address as a previous access address; An address calculation unit for generating a generation address by calculating the address increase / decrease value output from the address increase / decrease value register to the previous access address output from the access address storage unit based on the address control signal; And An address mode connected between the access address storage unit and the address operation unit to receive a master transmission address and the generation address sent by the master device to access the memory, and to transmit when the master device accesses the memory A multiplexer for selecting one of the master transmission address and the generation address to output a second access address based on the signal; And wherein said pattern of addresses has a constant increasing trend and a constant decreasing trend. The method of claim 1, wherein the address calculation unit, And adding and subtracting the previous access address and the address increment value when the pattern of addresses is increasing, and subtracting the previous access address and the address increment value when the pattern of addresses is decreasing. An address generation slave device characterized by the above-mentioned. The method of claim 1, And the address control signal includes size information of the addresses and trend information indicating whether the addresses have an increasing trend or a decreasing trend. The method of claim 1, The address mode signal controls the multiplexer to output the master transmission address as the second access address before the generation address is generated, and the multiplexer generates the master transmission address and the generation after the generation address is generated. Selecting one of the addresses and controlling to output as the second access address. The method of claim 1, wherein the access address storage unit, And a de-flip-flop that receives the address mode signal through an enable terminal and outputs the first access address as the previous access address in accordance with the address mode signal. A master device for transmitting an address control signal indicative of a pattern of addresses when accessing the memory; An address increase and decrease value register for storing an address increase and decrease value and outputting the address increase and decrease value based on the address control signal; An access address storage unit for receiving and storing a first access address and outputting the first access address as a previous access address; An address calculation unit for generating a generation address by calculating the address increase / decrease value output from the address increase / decrease value register to the previous access address output from the access address storage unit based on the address control signal; And An address mode connected between the access address storage unit and the address calculating unit to receive a master transmission address and the generation address sent by the master device to access the memory, and an address mode transmitted when the master device accesses the memory A multiplexer for selecting one of the master transmission address and the generation address and outputting a second access address based on the signal; And wherein said pattern of addresses has a constant increasing trend and a constant decreasing trend. The method of claim 6, wherein the address calculation unit, And adding and subtracting the previous access address and the address increment value when the pattern of addresses is increasing, and subtracting the previous access address and the address increment value when the pattern of addresses is decreasing. Characterized by a master slave system. The method of claim 6, The address control signal includes size information of the addresses and trend information indicating whether the addresses have an increasing trend or a decreasing trend. The method of claim 6, The address mode signal controls the multiplexer to output the master transmission address as the second access address before the generation address is generated, and the multiplexer generates the master transmission address and the generation after the generation address is generated. Selecting one of the addresses and controlling to output as the second access address. The method of claim 6, wherein the access address storage unit, And a de-flip-flop that receives the address mode signal through an enable terminal and outputs the first access address as the previous access address in accordance with the address mode signal. A plurality of master devices each transmitting address control signals indicative of patterns of addresses when accessing the memory; An address increase and decrease value register for storing an address increase and decrease value and outputting the address increase and decrease value based on the address control signal; An access address storage unit for receiving and storing a first access address and outputting the first access address as a previous access address; An address calculation unit for generating a generation address by calculating the address increase / decrease value output from the address increase / decrease value register to the previous access address output from the access address storage unit based on the address control signal; And Is connected between the access address storage unit and the address calculating unit to receive the master transmission address and the generation address sent by each master device to access the memory, and when each master device accesses the memory A multiplexer for selecting one of the master transmission address and the generation address and outputting a second access address based on the address mode signal to be transmitted, And the patterns of the addresses have different constant increasing trends and constant decreasing trends, respectively. The method of claim 11, wherein the address operation unit, And adding and subtracting the previous access address and the address increment value when the pattern of addresses is increasing, and subtracting the previous access address and the address increment value when the pattern of addresses is decreasing. Multi-Master Slave System The method of claim 11, The address control signal includes the size information of the addresses and trend information indicating whether the addresses have an increasing trend or a decreasing trend. The method of claim 11, The address mode signal controls the multiplexer to output the master transmission address as the second access address before the generation address is generated, and after the generation address is generated, the multiplexer sends the master transmission address and And select one of the generation addresses to control the output as the second access address. A register for storing an address increment value and outputting the address increment value based on an address control signal transmitted from a master device, receiving a first access address and outputting the first access address as a previous access address according to an address mode signal An access address storage unit configured to generate a generation address by calculating the address increase / decrease value to the previous access address based on the address control signal, and a master transmitted by the master device based on the address mode signal. A method for generating an address in an address generation circuit, comprising: a multiplexer for selecting one of a transmission address and the generation address output by the operation unit to output a second access address, The address increment value register storing the address increment value; The address increase / decrease register receives the address control signal from the master device, and the multiplexer and the access address store receive the address mode signal; The address increment value register outputting the address increment value based on the address control signal; Outputting, by the access address storage unit, the first access address as the previous access address according to the address mode signal; Generating, by the address calculator, a generation address by calculating the address increment value to the previous access address based on the address control signal; And The multiplexer receives the master transmission address and the generation address, and selects one of the master transmission address and the generation address based on the address mode signal transmitted when the master device accesses a memory to the second; Outputting an access address.

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