KR20100041625A - Method for fabricating three-dimensional semiconductor device and three-dimensional semiconductor device fabricated thereby - Google Patents

Abstract

PURPOSE: A method for manufacturing a three dimensional semiconductor device and the three dimensional semiconductor device are provided to reduce a leakage current between a gate electrode and a dopant layer by forming a thick insulation layer on the other region of an vertical transistor except for a channel region between the gate electrode and a gate insulation layer. CONSTITUTION: A first semiconductor substrate is prepared. Lower semiconductor elements are formed on the first semiconductor substrate. An interlayer insulation layer is formed to cover the lower semiconductor elements. A junction layer is formed on the interlayer insulation layer. A second semiconductor substrate(200) which includes a plurality of dopant layers(201, 202, 203) is formed on the interlayer insulation layer. The dopant layers are patterned to form vertical semiconductor elements.

Description

Method for fabricating a three-dimensional semiconductor device and a three-dimensional semiconductor device manufactured according to the present invention

The present invention relates to a method for manufacturing a 3D semiconductor device and a 3D semiconductor device manufactured according to the present invention, and more particularly, to a method for manufacturing a 3D semiconductor device capable of forming a vertical channel transistor through a substrate bonding, and thus manufacturing It relates to a three-dimensional semiconductor device.

In order to highly integrate a semiconductor device, the size of a pattern formed on a chip and the distance between the formed patterns are gradually reduced. However, when the size of the pattern is reduced as described above, an unexpected problem occurs such that the resistance is greatly increased. Therefore, there is a limit in increasing the degree of integration by reducing the size of the pattern. Therefore, recently, in order to highly integrate a semiconductor device, three-dimensional semiconductor devices in which semiconductor unit elements such as MOS transistors are stacked on a substrate have been developed.

 The three-dimensional structure semiconductor device can be formed by bonding another second semiconductor substrate onto one semiconductor element composed of a base semiconductor substrate and insulating layers already manufactured.

In addition, in order to improve the degree of integration of the semiconductor device, semiconductor devices having a vertical channel structure may be formed.

However, when the semiconductor device having the vertical channel structure is formed on the semiconductor substrate bonded to the upper portion, it is difficult to form the impurity layer in a desired region according to the size of the impurity ions when forming the impurity layers.

Accordingly, an object of the present invention is to provide a method of manufacturing a three-dimensional semiconductor device capable of forming a vertical channel transistor through a substrate junction.

In addition, another object of the present invention is to provide a three-dimensional semiconductor device manufactured according to the above manufacturing method.

Technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a method of manufacturing a three-dimensional semiconductor device, including an interlayer insulating layer that provides a first semiconductor substrate, forms lower semiconductor devices on the first semiconductor substrate, and covers the lower semiconductor devices. Forming a second semiconductor substrate including a plurality of impurity layers on the interlayer insulating film, and patterning the plurality of impurity layers to form vertical semiconductor elements on the interlayer insulating film.

In accordance with another aspect of the present invention, a three-dimensional semiconductor device includes a semiconductor substrate, lower semiconductor devices formed on the semiconductor substrate, an interlayer insulating film covering the lower semiconductor devices, and a vertical semiconductor device formed on the interlayer insulating film. The vertical semiconductor devices may include a gate electrode surrounding the sidewalls of the impurity patterns through the impurity layer patterns formed in the columnar shape on the interlayer insulating film, the sidewalls of the impurity patterns, and the insulating film and the insulating film formed between the impurity patterns. Include.

Specific details of other embodiments are included in the detailed description and the drawings.

As described above, according to the method of manufacturing the 3D semiconductor device and the 3D semiconductor device manufactured according to the present invention, impurity layers may be provided through substrate bonding, and the impurity layer may be patterned to form vertical channel transistors. The thickness of the gate insulating film formed on the channel region and the insulating film positioned under the gate electrode of the vertical channel transistor may be different.

Accordingly, in the vertical channel transistor formed by patterning the impurity layers provided through the substrate junction, the parasitic capacitance between the gate electrode and the impurity layer may be prevented from increasing at other portions except the channel region formed between the gate electrode and the gate insulating film. . As the insulating film is formed thicker at portions other than the channel region, leakage current between the gate electrode and the impurity layer can be reduced.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the dimensions of the substrates, layers (films), regions, recesses, pads, patterns or structures are shown to be larger than actual for clarity of the invention. In the present invention, each layer (film), region, pad, recess, pattern or structure is formed on the substrate, each layer (film), region, pad or patterns "on", "top" or "bottom". When referred to as meaning that each layer (film), region, pad, recess, pattern or structure is formed directly over or below the substrate, each layer (film), region, pad or patterns, or Other layers (films), other regions, different pads, different patterns or other structures may additionally be formed on the substrate.

Hereinafter, a method of manufacturing a 3D semiconductor device according to embodiments of the present invention will be described in detail with reference to the drawings.

1 through 8C are cross-sectional views sequentially illustrating a method of manufacturing a 3D semiconductor device according to example embodiments.

First, referring to FIG. 1, lower semiconductor devices are formed on the first semiconductor substrate 100. Although the shape of the lower semiconductor device is not limited, in general, a MOS-FET, a DRAM, an SRAM, a PRAM, or a flash memory device may be formed. In an embodiment of the present invention, it will be described as forming NMOS or PMOS transistors on the first semiconductor substrate 100.

In more detail, the first semiconductor substrate 100 may be bulk silicon, bulk silicon-germanium, or a semiconductor substrate having a silicon or silicon-germanium epi layer formed thereon. In addition, the first semiconductor substrate 100 may include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) ), Doped and undoped semiconductors, silicon epitaxial layers supported by the underlying semiconductor, and other semiconductor structures well known to those skilled in the art.

Then, the well region 104 is formed in the first semiconductor substrate 100. The well region 104 may be formed by ion implanting impurities into the surface of the first semiconductor substrate 100. The well region 104 may be formed by implanting impurities into the surface of the first semiconductor substrate 100. The well region 104 may form a p-type well region by implanting ions such as boron in a region where an NMOS device is to be formed, and form an n-type well region by implanting ions such as phosphorus in a region where the PMOS device is to be formed. Can be. In an embodiment of the present invention, only NMOS devices are formed on the first semiconductor substrate 100.

Afterwards, device isolation layers 102 for defining an active region are formed on the first semiconductor substrate 100. The device isolation layers 102 may be formed by forming trenches in the first semiconductor substrate 100 and filling an insulating material such as an HDP (High Density Plasma) oxide film in the trench.

After defining an active region in the first semiconductor substrate 100 through the device isolation layer 102, the gate insulating layer and the gate conductive layer are stacked and patterned on the first semiconductor substrate 100 to form the gate electrode 110. do. After the gate electrode 110 is formed, impurities are ion implanted into the first semiconductor substrate 100 on both sides of the gate electrode 110 to form the source / drain region 112. Accordingly, the transistors are completed on the first semiconductor substrate 100.

Next, referring to FIG. 2, a multilayer wiring layer 150 is formed on the first semiconductor substrate 100 on which the transistors are formed.

In detail, after the transistors are formed on the first semiconductor substrate 100, an insulating material having excellent step coverage is deposited to form the first interlayer insulating layer 120. For example, the first interlayer insulating layer 120 may be formed of a material such as PhosphoSilicate Glass (PSG), BoroPhosphoSilicate Glass (BPSG), Undoped Silicate Glass (USG), or Plasma Enhanced-TetraEthlyOrthoSilicate Glass (PE-TEOS).

In the first interlayer insulating layer 120, contacts and wirings 132 electrically connected to the lower transistors are formed. The contacts 132 selectively anisotropically etch the first interlayer insulating film 120 to form contact holes exposing the source / drain region 112 or the gate electrode 110, and then filling the conductive material in the contact holes. Can be formed. In detail, the contacts and the wirings 132 may be connected to the gate electrode 110 or the source / drain region 112 of the transistors.

After the contacts and the wirings 132 are formed in the first interlayer insulating layer 120, the second to third interlayer insulating layers 130 and 140 may be formed, and each of the interlayer insulating layers 130 and 140 may be formed. The contact and the wirings 132 may be formed.

As such, when forming the contacts and the wirings 132, various conductive materials may be used. In general, aluminium or copper wirings used in semiconductor integrated circuits may be used, and refractory metal materials may be used to reduce thermal effects of subsequent processes. For example, the contacts and wires 132 may include tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta) titanium nitride (TiN), tantalum nitride (TaN), zirconium nitride (ZrN), and tungsten. It may be formed of an alloy made of a nitride film (TiN) and a combination thereof.

Next, referring to FIG. 3, a second semiconductor substrate (see 200 of FIG. 5) for forming upper semiconductor elements is formed on a third interlayer insulating layer 140 positioned on the top layer on the first semiconductor substrate 100. The bonding layer 160 which can be bonded is formed.

For example, the bonding layer 160 may use various curable adhesives, such as photo-setting adhesives such as reaction curable adhesives, thermosetting adhesives, and ultraviolet curable adhesives, and anaerobic adhesives. Or metal-based Ti, TiN, Al, etc.), epoxy-based, acrylate-based, silicon-based, and the like.

Here, when the bonding layer 160 is formed of a metal material, the metal material may be formed of a material that melts at a lower temperature than the metal materials formed in the lower wiring layer 150. In addition, in order to prevent voids that may be formed due to microscopic non-uniformity of the surface at the time of bonding with the semiconductor substrate 200, the material may be formed of a material that may be reflowed at a low temperature during the planarization process. That is, the bonding layer 160 may increase the bonding strength when the second semiconductor substrate 200 is adhered to the upper portion, and may serve to reduce fine defects that may occur during bonding.

In the exemplary embodiment of the present invention, the bonding layer 160 made of the metal material and the semiconductor substrate 200 are bonded to each other. You may join.

Next, a second semiconductor substrate to be bonded on the bonding layer 160 is prepared.

4A to 4C, a single crystal semiconductor substrate 207 including a plurality of impurity layers 200 doped with impurities uniformly to a predetermined depth is prepared as a second semiconductor substrate. . Here, the plurality of impurity layers 200 may be formed by ion implanting impurities into the single crystal semiconductor substrate 207 or by adding impurities during the epitaxial layer growth process for forming the single crystal semiconductor substrate 207.

In this case, the plurality of impurity layers 200 may be formed by ion implantation of impurities such that the n-type impurity layers 201 and 203 and the p-type impurity layer 202 may be alternately positioned. That is, an impurity layer having an n / p / n or p / n / p structure may be formed from the surface of the second semiconductor substrate. The plurality of impurity layers 200 formed on the second semiconductor substrate may provide a channel region and a source / drain region when forming transistors according to a subsequent process.

That is, referring to FIG. 4B, when the plurality of impurity layers 200 are formed in the second semiconductor substrate, impurity ions having large particles are formed near the surface of the semiconductor substrate. In other words, when the impurity layer having an n / p / n structure is formed, n-type impurity ions having large particles are formed at a shallow depth from the surface of the semiconductor substrate to form the first impurity layer 201. Then, the p-type impurity is implanted under the first impurity layer 201 to form the second impurity layer 202. Then, the n-type impurity ions having smaller particles than the ions of the first impurity layer 201 are implanted to form the third impurity layer 203 at the deepest depth from the surface of the semiconductor substrate.

For example, relatively large particles of n-type impurity ions are formed at a shallow depth from the surface of the semiconductor substrate. Thereafter, boron (B) ions, which are p-type impurities, are formed under the acne impurity layer. In addition, phosphorus ions are formed under the boron impurity layer with n-type impurities having a smaller ionic particle than those of the ionic.

Thereafter, as shown in FIG. 5, a fourth impurity layer 210 is further formed on the second semiconductor substrate to increase the thickness of the first impurity layer 201 formed shallowly from the surface of the semiconductor substrate.

In detail, the polycrystalline semiconductor layer is further formed on the surface on which the first impurity layer 201 is formed of the acetic ions. Thereafter, the fourth impurity layer 210 may be formed by injecting n-type impurities such as arsenic or phosphorus into the polycrystalline semiconductor layer. Alternatively, the fourth impurity layer 210 may be formed by forming a polycrystalline semiconductor layer on the surface on which the first impurity layer 201 is formed and simultaneously doping n-type impurities in-situ.

Alternatively, the epitaxial layer may be formed on the surface of the first impurity layer 201 and the fourth impurity layer 210 may be formed by doping the epitaxial layer with n-type impurities.

Meanwhile, when the bonding layer 160 is formed of a metal layer, the bonding layer 160 may serve to increase the impurity region of the first impurity layer 210 formed on the surface of the semiconductor substrate.

In addition, instead of further forming a fourth impurity layer 210 on the first impurity layer 201 having large ion particles to increase the thickness of the n-type impurity layer, a phosphorus having small ion particles from the surface of the semiconductor substrate to a predetermined depth An impurity may be ion implanted to form a thick n-type impurity layer.

A separation layer 205 is formed at the interface of the plurality of impurity layers 200, that is, the third impurity layer 203 and the single crystal semiconductor layer 207. The separation layer 205 is a strained layer formed by a difference between the crystal lattice (for example, Si-Ge) of a porous layer having fine pores, an insulating film such as an oxide film or a nitride film, an organic adhesive layer, or a substrate. Say Among the techniques for forming the separation layer 205, one of the most popular techniques is a method of separating an wafer by ion implanting a vaporizing gas such as hydrogen.

The separation layer 205 serves to prevent the impurity layer 200 from being removed when the second semiconductor substrate 200 is attached to the bonding layer 160 and then the region of the single crystal semiconductor substrate 207 is removed. can do. In addition, the isolation layer 205 serves to allow the single crystal semiconductor substrate 207 to be separated accurately and easily, leaving only the impurity layer 200.

Thereafter, as shown in FIG. 6, the surfaces of the plurality of impurity layers 200 and 210 face the bonding layer 160 to bond the single crystal semiconductor substrate 207. In other words, the thick n-type impurity layers 201 and 210, that is, the surface of the fourth impurity layer 210 are bonded to the surface of the bonding layer 160.

After the plurality of impurity layers 200 and 210 are bonded onto the bonding layer 160, heat treatment may be performed while applying a predetermined pressure to increase the bonding strength.

As described above, when the single crystal semiconductor substrate 207 including the plurality of impurity layers 200 and 210 is adhered to the bonding layer 160, other semiconductor elements are not formed on the single crystal semiconductor substrate 207. It is not required to align the single crystal semiconductor substrate 207 exactly on the bonding layer 150.

After the impurity layer 200 of the single crystal semiconductor substrate 207 is completely bonded, all portions other than the impurity layers 200 and 210 are removed as shown in FIG. 6.

In more detail, the grinding, polishing, or etching process is performed from the top surface of the bonded single crystal semiconductor substrate 207 until the separation layer 205 is exposed. After the separation layer 205 is exposed, the surface of the plurality of impurity layers 200 is exposed by performing an anisotropic or isotropic etching process. That is, the n-type impurity layer 203 made of phosphorus ions is exposed.

Exposing the plurality of impurity layers 200 may be selectively etched using different materials or different densities of the same material in the impurity layer 200 and the separation layer 205 in the semiconductor substrate. Alternatively, a physical impact may be applied to the separation layer 205 to cause cracks along the separation layer 205 having weak crystal lattice to separate the single crystal semiconductor substrate 207 and the plurality of impurity layers 200.

On the other hand, the single crystal semiconductor substrate 207 may be a medium such as a glass wafer in some cases. For example, when the impurity layer is provided, it may be provided to the glass wafer and again to another semiconductor substrate.

As described above, the single crystal semiconductor substrate 207 including the impurity layer is bonded on the bonding layer 160, and the single crystal semiconductor substrate 207 except for the impurity layer 200 is removed, thereby forming a large number on the bonding layer 160. Impurity layers 200 and 210 are formed.

That is, the fourth impurity layer 210 is positioned on the junction layer 160 surface, and the first, second, and third impurity layers are sequentially arranged on the fourth impurity layer. That is, fourth and first impurity layers 210 and 201 made of n-type impurities are formed on the surface of the bonding layer 160. Therefore, an n-type impurity layer having a thick thickness can be formed on the bonding layer 160.

Next, a plurality of impurity layers 210 and 200 are patterned to form transistors having a vertical channel structure.

That is, an etching mask (not shown) for patterning the impurity layers 210 and 200 is formed on the plurality of impurity layers 200. In this case, the etching mask may be formed by applying and patterning a photoresist.

Then, the plurality of impurity layers 200 and 210 and the bonding layer 160 are patterned using an etching mask. That is, the plurality of impurity layers and the bonding layer 160 are sequentially etched until the third interlayer insulating layer 140 is exposed.

As described above, the patterning of the plurality of impurity layers 210 and 200 may be performed one or more patterning processes according to the characteristics of the semiconductor device formed thereon.

That is, as shown in FIG. 8, in the exemplary embodiment of the present invention, a plurality of columnar impurity layer patterns 200 ′ are formed on the upper side. At this time, each impurity layer pattern 200 ′ has an n / p / n structure, and the n-type impurity layer on the junction layer pattern 162 includes first and fourth impurity layers. That is, the n-type impurity layer on the junction layer pattern 162 has a structure formed thicker than the p-type or n-type impurity layer positioned on the upper portion. In addition, the n-type impurity layers on the bonding layer pattern 162 may be electrically connected to each other. Accordingly, the channel region and the source / drain region of the vertical channel transistor can be formed. Here, when the patterned bonding layer 162 is formed of a conductive material, the patterned bonding layer 162 may serve to electrically connect the lower contact 132 and the vertical channel transistors.

Next, a gate insulating film and a gate electrode are formed around the columnar impurity layer patterns 200 ′. A method of forming the gate insulating film and the gate electrode will be described in more detail with reference to FIGS. 9A to 9E.

Referring to FIG. 9A, first, third and fourth impurity layers 201 ′, 203 ′, and 210 ′ may be provided as source / drain regions, and a second impurity layer 202 ′ may be provided as a channel region. In this case, the first and fourth impurity layers 201 ′ and 210 ′ may form one source / drain region.

After the pillar-type impurity layer patterns are formed, the gate insulating layer 220 is conformally formed along the pillar-type impurity layer patterns 201 ', 202', 203 ', and 210'. At this time, in order to prevent the parasitic capacitance and / or leakage current from increasing, the gate insulating film 220 is formed thick. That is, the gate insulating layer 220 may completely cover the impurity layer patterns 201 ′, 202 ′, 203 ′, and 210 ′ in the form of pillars.

Then, as illustrated in FIG. 9B, a planarization process such as chemical-mechanical polishing (CMP) is performed on the gate insulating film 220 to planarize the top surface of the gate insulating film 220. Here, the gate insulating layer 222 may expose the top surface of the impurity layer pattern 203.

Next, referring to FIG. 9C, a dry etching process may be performed on the gate insulating layer 222 having the flattened top surface, thereby forming a horizontal gate insulating layer pattern between the impurity layer patterns 201 ′, 202 ′, 203 ′, and 210 ′. Remove 224) leaving only a certain thickness. Here, the horizontal gate insulating layer pattern 224 between the impurity layer patterns 201 ′, 202 ′, 203 ′, and 210 ′ may be formed above the fourth impurity layer pattern 210 ′.

That is, a thick horizontal gate insulating layer pattern 224 is formed on and around the fourth impurity layer pattern 210 ′. The method of forming the horizontal gate insulating layer pattern 224 is not limited thereto, and may be formed using other methods.

Thereafter, as illustrated in FIG. 9D, a thin vertical gate insulating layer 232 is formed on sidewalls of the impurity layer patterns 201 ′, 202 ′, 203 ′, and 210 ′. The vertical gate insulating layer 232 controls the charge between the gate electrode (see 242 in FIG. 9E) and the channel region formed subsequently. In this case, the vertical gate insulating film 232 may be formed of an oxide film, or may be formed of a composite insulating film capable of storing charge, such as an ONO film. In addition, a floating gate may be further formed on the gate insulating film.

9E, gate electrodes 242 are formed on the horizontal and vertical gate insulating layers 224 and 232. In detail, the gate conductive film is deposited to cover the top surfaces of the horizontal and vertical gate insulating layers 224 and 232 and the impurity layer pattern 203 '. The gate conductive layer is anisotropically etched to form the gate electrode 242 that simultaneously encloses the columnar impurity layer patterns 201 ′, 202 ′, 203 ′, and 210 ′. That is, one word line may be formed by simultaneously surrounding the impurity layer patterns 201 ', 202', 203 ', and 210'.

After forming the gate electrode 242 in this manner, as shown in FIG. 10, a fifth interlayer insulating layer 250 is formed to completely fill the vertical channel transistors. Then, the contacts and the wirings 262 are formed in the fifth interlayer insulating film 250. Some of the contacts and wires 262 may be electrically connected to the semiconductor devices positioned on the first semiconductor substrate 100.

As such, when the vertical channel transistor is formed through the substrate junction, an n-type impurity layer is formed deep from the surface of the substrate to be bonded to the upper portion, and then the vertical channel transistor is formed. The parasitic capacitance may be prevented from increasing in contact with the impurity region 210 ′ other than the channel region. As the horizontal gate insulating layer pattern 224 is formed thick, leakage current between the gate electrode 242 and the impurity layer 210 ′ may be reduced.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is shown by the following claims rather than the above description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 through 10 are cross-sectional views sequentially illustrating a method of manufacturing a 3D semiconductor device according to example embodiments.

<Description of the code | symbol about the principal part of drawing>

100: first semiconductor substrate 120, 130, 140: interlayer insulating film

132 and 242: wiring 150: wiring layer

160: bonding layer 201: first impurity layer

202: second impurity layer 203: third impurity layer

210: fourth impurity layer 232: gate insulating film

234: gate electrode

Claims (31)

Providing a first semiconductor substrate, Forming lower semiconductor devices on the first semiconductor substrate, Forming an interlayer insulating film covering the lower semiconductor devices, Bonding a second semiconductor substrate including a plurality of impurity layers on the interlayer insulating film, Patterning the plurality of impurity layers to form vertical semiconductor elements on the interlayer insulating film. The method of claim 1, wherein the forming of the vertical semiconductor devices is performed. And forming transistors having a vertical channel with respect to the first semiconductor substrate. The method of claim 2, And patterning the plurality of impurity layers to form a channel region and a source / drain region of the transistors. The method of claim 1, wherein before bonding the second semiconductor substrate, And forming a bonding layer on the interlayer insulating film. The method of claim 4, wherein And said bonding layer is formed of an insulating material or a conductive material. The method of claim 1, wherein the bonding of the second semiconductor substrate, Providing a single crystal semiconductor substrate, Forming first to third impurity layers to a predetermined depth from an upper surface of the single crystal semiconductor substrate, Bonding the single crystal semiconductor substrate to face an upper surface of the interlayer insulating film and the first impurity layer; Removing a portion of the single crystal semiconductor substrate until the surface of the first impurity layer is exposed. The method of claim 6, wherein forming the first to third impurity layer, Method for manufacturing three-dimensional semiconductor device in which n-type and p-type impurity layers are alternately formed The method of claim 7, wherein forming the first to third impurity layer, A first impurity layer is formed by doping n-type impurities having large particles at a depth close to the surface of the single crystal semiconductor substrate, P-type impurities are doped under the first impurity layer to form a second impurity layer, And forming a third impurity layer under the second impurity layer by doping an n-type impurity having a smaller particle size than the n-type impurity of the first impurity layer. 8. The method of claim 7, wherein after forming the first to third impurity layers, And forming a fourth impurity layer of the same conductivity type as the first impurity layer on the surface of the first impurity layer. The method of claim 9, wherein the fourth impurity layer is formed, A method for manufacturing a three-dimensional semiconductor device, which is formed by doping an impurity layer in a polycrystalline or single crystal semiconductor layer. 10. The method of claim 9, wherein after joining the second semiconductor substrate, Patterning the first to fourth impurity layers to form columnar impurity layer patterns, A gate insulating film and a gate conductive film are sequentially formed conformally along surfaces of the impurity layer patterns, And patterning the gate conductive layer to complete a plurality of vertical channel transistors. The method of claim 11, And the gate insulating film is formed to have a greater thickness of the gate insulating film located horizontally between the impurity layer patterns than the thickness of the gate insulating film perpendicular to the sidewalls of the impurity layer pattern. The method of claim 12, The thickness of the gate insulating film positioned horizontally between the impurity layer patterns is smaller than the total thickness of the first and fourth impurity layers. The method of claim 11, The gate electrode is a manufacturing method of a three-dimensional semiconductor device including a floating gate or an ONO layer. The method of claim 7, wherein after bonding the second semiconductor substrate, Patterning the first to third impurity layers to form columnar impurity layer patterns, A gate insulating film and a gate conductive film are sequentially formed conformally along surfaces of the impurity layer patterns, And patterning the gate conductive layer to complete a plurality of vertical channel transistors. The method of claim 15, And the gate insulating film is formed to have a greater thickness of the gate insulating film located horizontally between the impurity layer patterns than the thickness of the gate insulating film perpendicular to the sidewalls of the impurity layer pattern. The method of claim 16, The thickness of the gate insulating film positioned horizontally between the impurity layer patterns is smaller than the thickness of the first impurity layer. The method of claim 15, The gate electrode is a manufacturing method of a three-dimensional semiconductor device including a floating gate or an ONO layer. The method of claim 6, wherein after forming the first to third impurity layers, And forming a separation layer in the single crystal semiconductor substrate at a depth in contact with the third impurity layer. The method of claim 19, The method for manufacturing a three-dimensional semiconductor device is such that the separation layer is formed of a bubble layer. The method of claim 19, And the separation layer prevents the impurity layer from being removed when a portion of the single crystal semiconductor substrate is removed. The method of claim 1, wherein after forming the vertical semiconductor devices, Forming an upper interlayer insulating layer covering the vertical semiconductor elements; The method of claim 3, further comprising forming a wiring layer including wirings electrically connected to the lower semiconductor devices. The method of claim 22, A method for manufacturing a three-dimensional semiconductor device, wherein wirings in the wiring layer are formed of refractory metal. The method of claim 23, The wirings are made of any one selected from the group consisting of cobalt (Co), titanium (Ti), tungsten (W), nickel (Ni), platinum (Pt), hafnium (Hf), molybdenum (Mo), and palladium (Pd). The manufacturing method of a three-dimensional semiconductor device. Semiconductor substrates; Lower semiconductor devices formed on the semiconductor substrate; An interlayer insulating layer covering the lower semiconductor elements; Vertical semiconductor devices formed on the interlayer insulating film, The vertical semiconductor device, Impurity layer patterns formed in a pillar shape on the interlayer insulating layer; An insulating film formed between sidewalls of the impurity patterns and the impurity patterns; And And a gate electrode surrounding the sidewalls of the impurity patterns via the insulating layer. The method of claim 25, And the gate insulating layer is thicker than the gate insulating layer having a thickness of the gate insulating layer positioned between the impurity patterns covering the sidewall of the impurity pattern. The method of claim 25, The impurity layer pattern may include a first conductive impurity layer and a second conductive impurity layer alternately stacked. 28. The method of claim 27, And the first conductivity type impurity layer is in contact with the interlayer insulating film and formed thicker than the thickness of the second conductivity type impurity layer. 28. The method of claim 27, And the impurity layer pattern is an n-type / p-type / n-type or a p-type / n-type / p-type impurity layer pattern. The method of claim 25, The gate electrode includes a floating gate or an ONO layer. The method of claim 25, And the vertical semiconductor devices are electrically connected to the lower semiconductor devices.

Images