KR101120676B1 - Method for fabricating semiconductor memory device - Google Patents

Abstract

A method for manufacturing a semiconductor memory device having a three-dimensional structure is provided. A method of manufacturing a semiconductor memory device includes forming first information storage elements on a first semiconductor substrate, forming switching elements on the first information storage elements, and forming second information storage elements on the switching elements. Include.

Semiconductor Memory, DRAM, Integration

Description

Method for fabricating semiconductor memory device

The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly, to a method for manufacturing a semiconductor memory device having a three-dimensional structure that can improve the degree of integration.

In order to highly integrate a semiconductor device, the size of a pattern formed on a chip and the distance between the formed patterns are gradually reduced.

However, when the size of the pattern is reduced as described above, a problem such as an increase in leakage current occurs. Therefore, there is a limit to increasing the degree of integration by reducing the size of the pattern.

Therefore, recently, in order to highly integrate a semiconductor device, three-dimensional semiconductor devices having semiconductor unit elements such as MOS transistors stacked on a substrate have been developed.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor memory device having a three-dimensional structure that can improve the degree of integration.

Technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, a method of manufacturing a semiconductor device may include forming first information storage elements on a first semiconductor substrate, forming switching elements on the first information storage elements, and switching. Forming second information storage elements on the elements.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, wherein switching elements are formed on an entire surface of a first semiconductor substrate, and on the switching elements, first information is electrically connected to the switching elements. Forming storage elements, and forming second information storage elements on the back surface of the first semiconductor substrate, the second information storage elements being electrically connected to the switching elements.

Specific details of other embodiments are included in the detailed description and drawings.

According to the manufacturing method of the semiconductor device of the present invention, the degree of integration of the semiconductor memory device can be further improved by forming the information storage devices on the top / bottom side or the side of the switching device.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the dimensions of the substrates, layers (films), regions, recesses, pads, patterns or structures are shown to be larger than actual for clarity of the invention. In the present invention, each layer (film), region, pad, recess, pattern or structure is formed on the substrate, each layer (film), region, pad or patterns "on", "top" or "bottom". When referred to as meaning that each layer (film), region, pad, recess, pattern or structure is formed directly over or below the substrate, each layer (film), region, pad or patterns, or Other layers (films), other regions, different pads, different patterns or other structures may additionally be formed on the substrate.

A method of manufacturing a semiconductor memory device according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1 through 11. 1 to 11 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention.

Referring to FIG. 1, logic elements are formed on a first semiconductor substrate 100. That is, logic elements may be formed on the first semiconductor substrate 100 by forming NMOS and PMOS transistors 110 and 112, a resistor (not shown), a diode (not shown), and wires (not shown). have.

In more detail, the device isolation layers 102 are formed in the first semiconductor substrate 100 to define an active region. Here, the first semiconductor substrate 100 may be bulk silicon, bulk silicon-germanium, or a semiconductor substrate on which a silicon or silicon-germanium epi layer is formed. In addition, the first semiconductor substrate 100 may include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) ), Doped and undoped semiconductors, silicon epitaxial layers supported by the underlying semiconductor, and other semiconductor structures well known to those skilled in the art.

In addition, the device isolation layers 102 may be formed by forming trenches in the first semiconductor substrate 100 and filling an insulating material such as a high density plasma (HDP) oxide film in the trench.

Meanwhile, before forming the device isolation layers 102, a well region for forming NMOS or PMOS transistors may be formed in the first semiconductor substrate 100 for each predetermined region. The well region may be formed by implanting impurities into the surface of the first semiconductor substrate 100.

After defining an active region in the first semiconductor substrate 100, the gate insulating layers and the gate conductive layers are stacked and patterned on the first semiconductor substrate 100 to form the gate electrodes 110. After the gate electrode 110 is formed, impurities are ion implanted into the first semiconductor substrate 100 on both sides of the gate electrode 110 to form the source / drain regions 112. Accordingly, transistors may be formed on the first semiconductor substrate 100.

Referring to FIG. 2, the first interlayer insulating layer 120 is formed on the transistors by depositing an insulating material having excellent step coverage. Here, a resistor (not shown), a diode (not shown), and wires (not shown) may be buried in the first interlayer insulating layer 120.

Subsequently, lower information storage elements are formed on the first interlayer insulating layer 120 having logic elements embedded therein. In an embodiment of the present invention, capacitors may be formed as lower information storage elements. Meanwhile, as the lower information storage elements, an information storage element using a phase change of a phase change material may be formed. In addition, an information storage element may be formed that utilizes high residual polarization of the ferroelectric material as the lower information storage elements.

When the capacitors are formed as information storage elements, the capacitors may be formed in various forms such as a stack type, a pillar type, a cylinder type, and the like. That is, in the case of a stacked capacitor, the first electrode and the second electrode may have a stacked structure when they face each other. In the case of a columnar capacitor, the first electrode may be formed in a columnar shape, and the second electrode may be conformally formed along the outer wall surface of the first electrode. In addition, in the case of a cylindrical capacitor, the first electrode may be formed in a cylinder shape, and the second electrode may be conformally formed along the inner wall surface of the first electrode. In an embodiment of the present invention, the cylindrical capacitors 132 and 134 are formed as an example.

In more detail, the first electrodes 132, which are plate electrodes, are formed on the first interlayer insulating layer 120 having logic elements embedded therein. That is, a conductive film having a sufficient thickness is deposited on the first interlayer insulating film 120, and a photolithography process is performed on the conductive film to form first electrodes 132 in the form of pillars connected to each other.

After the first electrodes 132 are formed, a dielectric film (not shown) and a conductive film for the second electrode are conformally formed on the surface of the first electrode 132. Thereafter, the conductive film for the second electrode is etched to separate the second electrode conductive film into the second electrodes 134. That is, second electrodes 134 covering the pillar surface of the first electrode 134 and separated from each other may be formed. In this case, the second electrodes 134 may be formed as a storage node electrode and have a cylindrical shape open downward.

As such, when the lower capacitors 132 and 134 having a cylindrical shape are formed, the first and second electrodes may be formed of polysilicon or a metal material, and the dielectric layer (not shown) may be a tantalum oxide layer (Ta ₂ O ₅ ). Alternatively, it may be formed of a single film of aluminum oxide (Al ₂ O ₃ ) or a laminated film of a tantalum oxide film / titanium oxide film or an aluminum oxide film / titanium oxide film.

Referring to FIG. 3, capacitors 132 and 134 are formed, and then an insulating film made of oxide is deposited on the entire surface of the resultant. The second interlayer insulating layers 140 and 150 may be formed by performing a planarization process such as chemical mechanical polishing (CMP) or etch back.

Thereafter, contact plugs 162 for lower storage nodes connected to the second electrode 134 and logic contact plugs 164 connected to the lower logic elements, that is, the transistors 110 and 112, respectively. Form. Then, conductive lines 174 are formed on the contact plugs 162 and 164. In this case, conductive lines that are not connected to the contact plug 162 for the lower storage node may also be formed on the capacitors 132 and 134. At this time, the conductive lines not connected to the contact plug 162 for the lower storage node correspond to the bit lines 172 connected to the switching element to be formed by a subsequent process. That is, the bit line 172 and the conductive line 174 may be alternately formed on the capacitors 132 and 134.

Subsequently, a third interlayer insulating layer 180 covering the bit lines 172 and the conductive lines 174 is formed, and the bit lines 172 and the second electrodes 134 are respectively formed in the third interlayer insulating layer 180. Electrically connected contact plugs 182 are formed.

Referring to FIG. 4, a bonding layer 190 for bonding a second semiconductor substrate 200 for forming switching elements onto a third interlayer insulating layer 180 positioned on the top layer on the first semiconductor substrate 100. To form.

The bonding layer 190 may use, for example, various curable adhesives such as photo-setting adhesives such as reaction curable adhesives, thermosetting adhesives, and ultraviolet curable adhesives, and anaerobic adhesives. Or metal-based Ti, TiN, Al, etc.), epoxy-based, acrylate-based, silicon-based, and the like.

Here, when the bonding layer 190 is formed of a metal material, the metal material is formed of a material that melts at a lower temperature than the conductive materials formed in the contact plugs 162 and 164 and the conductive lines 172 and 174. Can be. In addition, the bonding layer 190 may be reflowed at a low temperature during the planarization process in order to prevent voids that may be formed due to microscopic non-uniformity of the surface during bonding with the second semiconductor substrate 200. Formed of material. That is, the bonding layer 190 may increase the bonding strength when the second semiconductor substrate 200 is adhered to the upper portion, and may serve to reduce fine defects that may occur during bonding.

Next, the second semiconductor substrate 200 is bonded to the bonding layer 190. In more detail, the second semiconductor substrate 200 may be a single crystal semiconductor substrate including a plurality of impurity layers 201, 203, and 205 from a surface to a predetermined depth. Here, the plurality of impurity layers 201, 203, and 205 may be formed by ion implanting impurities into the single crystal semiconductor substrate or by adding impurities during the epitaxial growth process for forming the single crystal semiconductor substrate.

In this case, the plurality of impurity layers 200 may be formed by ion implantation of impurities such that the n-type impurity layers 201 and 205 and the p-type impurity layer 203 may be alternately positioned. In an embodiment of the present invention, since the NMOS transistors are formed as a switching element, an n-type impurity layer 201 is formed on a surface of the plurality of impurity layers 201, 203, and 205 in contact with the bonding layer 190. Form.

In addition, in the second semiconductor substrate 200 including the plurality of impurity layers 201, 203, and 205, the separation layer 207 is included at the interface between the impurity layers 201, 203, and 205 and the single crystal semiconductor substrate. . Separation layer 207 is a strained layer formed by a difference between a microporous bubble layer (Porous), an insulating film such as an oxide film or a nitride film, an organic adhesive layer, or a crystal lattice of a substrate (for example, Si-Ge). Say Among the technologies for forming the separation layer 207, one of the most popular techniques is an ion implantation of an evaporable gas such as hydrogen (exfoliating implant) to separate the wafer, but in this case, ion implantation is excessively used. The lattice structure of the powder layer 201, 203, 205 may be destroyed. In addition, in order to recover such a broken lattice structure, heat treatment is required for a certain time at a very high temperature, and such a very high temperature treatment may cause a severe change in the cell element located below.

The separation layer 207 prevents the impurity layers 201, 203, and 205 from being removed when the single crystal semiconductor substrate region is removed after the second semiconductor substrate 200 is bonded onto the bonding layer 190. Can play a role. In addition, the separation layer 207 leaves only the impurity layers 201, 203, and 205, and serves to accurately and easily separate the single crystal semiconductor substrate.

Subsequently, referring to FIG. 5, the surfaces of the impurity layers 201, 203, and 205 face the bonding layer 190 to bond the second semiconductor substrate 200. After the second semiconductor substrate 200 is bonded onto the bonding layer 190, heat treatment may be performed while applying a predetermined pressure to increase the bonding strength.

As such, when adhering the second semiconductor substrate 200 including the impurity layers 201, 203, and 205 onto the bonding layer 190, no other semiconductor elements are formed on the second semiconductor substrate 200. As such, it is not required to accurately align the second semiconductor substrate 200 on the bonding layer 190.

After the second semiconductor substrate 200 is completely bonded onto the bonding layer 190, all of the remaining portions except for the impurity layer 200 are removed. Accordingly, a plurality of impurity layers 201, 203, and 205 may be formed on the bonding layer 190 made of a metal material.

In more detail, the single crystal semiconductor region is ground or polished until the separation layer 207 is exposed in the bonded second semiconductor substrate 200. After the separation layer 207 is exposed, an anisotropic or isotropic etching process is performed to expose the surfaces of the plurality of impurity layers 201, 203, and 205. That is, the n-type impurity layer 205 is exposed.

Exposing the plurality of impurity layers 201, 203, and 205 may result in a difference in impurity concentration gradients in the impurity layers 201, 203, and 205 and the separation layer 207 in the second semiconductor substrate. Selective etching is possible for. Alternatively, a physical impact may be applied to the separation layer 207 to cause cracks along the separation layer 207, which are weak in crystal lattice, to separate the single crystal semiconductor region and the plurality of impurity layers 201, 203, and 205. have.

As such, the second semiconductor substrate 200 including the impurity layers 201, 203, and 205 is bonded to the junction layer 190, and the single crystal semiconductor except for the impurity layers 201, 203, and 205 is removed. As a result, the n-type impurity layer 201, the p-type impurity layer 203, and the n-type impurity layer 205 may be sequentially formed on the bonding layer 190.

Next, referring to FIG. 6, pillar-shaped semiconductor layer patterns 202, 204, and 206 are formed to form switching elements having a vertical channel structure, that is, a transistor. Since the pillar-shaped semiconductor patterns 202, 204, and 206 are formed by patterning the impurity layers 201, 203, and 205, the semiconductor patterns 202, 204, and 206 are formed in the channel region 204 and the source / drain regions 202 and 206 of the switching device. This may be the case.

In more detail, the photolithography process may be performed on the plurality of semiconductor layers to form the semiconductor layer patterns 202, 204, and 206. That is, an n / p / n type impurity layer pattern may be formed. In addition, when forming the semiconductor layer patterns 202, 204, and 206, the bonding layer 190 may also be etched together. Accordingly, the bonding layer pattern 190 may be formed under the pillar-shaped semiconductor layer pattern 202, and a portion of the surface of the third interlayer insulating layer 180 may be exposed.

Referring to FIG. 7, a gate electrode 220 having a spacer shape is formed on both sides of a semiconductor layer pattern 204 positioned in the middle of the semiconductor layer patterns 202, 204, and 206.

That is, a fourth interlayer insulating layer 230 is formed on the third interlayer insulating layer 180 to cover sidewalls of the semiconductor layer pattern 202 in contact with the bonding layer 190. Subsequently, contact plugs are formed in the third and fourth interlayer insulating layers 180 and 210 to connect the lower logic elements and the gate electrode 220. The gate insulating film and the gate conductive film are conformally deposited on the fourth interlayer insulating film 210 along the surfaces of the semiconductor layer patterns 204 and 206. The gate insulating film and the gate conductive film may be anisotropically etched to form a gate electrode 220 having a spacer shape surrounding the channel region, that is, the p-type semiconductor layer pattern 204 located at the center. Accordingly, transistors having vertical channels can be formed.

 Referring to FIG. 8, a fifth interlayer insulating layer 230 covering the pillar-shaped semiconductor layer patterns 202, 204, and 206 and the gate electrodes 220 is formed. Thereafter, contact plugs 242 connected to the source / drain regions 206 may be formed in the fifth interlayer insulating film 230, and contact plugs 244 connected to the logic elements may be formed at the same time. Then, conductive lines 252 and 254 are formed on the respective contact plugs 242 and 244. Here, the conductive lines 252 of the semiconductor layer patterns 202, 204, and 206 to which the capacitors 132 and 134 are connected among the contact plugs 242 connected to the source / drain regions 206 may be bit lines. It may correspond to.

Referring to FIG. 9, after the conductive lines 252 and 254 are formed, a sixth interlayer insulating layer 260 is formed, and a contact plug 262 for an upper storage node that is connected to the conductive lines 252 is selectively formed. Form.

The storage node electrode, that is, the second electrode and the source / Contact plugs 262 for upper storage nodes are formed to electrically connect the drain region 206.

Thereafter, upper information storage elements, that is, upper capacitors, are formed on the sixth interlayer insulating layer 260. The upper information storage elements are formed symmetrically with the lower information storage elements, that is, the lower capacitors 132 and 134, and may be electrically connected to the switching elements to which the lower information storage elements are not connected. In addition, the switching elements connected to the lower information storage elements and the switching elements connected to the upper information storage elements may be formed in a structure in which they are alternately arranged. In one embodiment of the present invention, the upper information storage elements may be formed of a cylindrical capacitor.

In more detail, a seventh interlayer insulating layer 270 having a sufficient thickness is formed on the sixth interlayer insulating layer 260. Subsequently, the seventh interlayer insulating layer 270 is patterned to form openings that respectively expose an upper surface of the contact plug 262 for the upper storage node.

Next, referring to FIG. 10, a conductive film for an electrode for a second electrode of the upper capacitor is conformally deposited along the surface of the seventh interlayer insulating film on which the openings are formed. By depositing an insulating film (not shown) having excellent gap filling characteristics on the conductive film for the second electrode, and planarizing the conductive film for the second electrode until the seventh interlayer insulating film 270 is exposed, The second electrodes 282 having a cylindrical shape open to the top are formed. A dielectric film (not shown) is conformally formed on the surfaces of the second electrodes 282, and a conductive film for the first electrode filling the inside of the second electrode 282 is deposited. Subsequently, the first electrode 284 is completed by patterning the first electrode conductive film.

Referring to FIG. 11, an eighth interlayer insulating layer 280 may be formed on the seventh interlayer insulating layer 270 to cover the upper information storage elements 282 and 284. Finally, contact plugs 292 and metal wires 294 may be formed to be connected to logic elements.

That is, according to the first embodiment of the present invention, switching elements having a vertical channel may be formed on the logic elements through bonding of a semiconductor substrate, and information storage elements may be formed on and under the switching elements. .

12 to 19, a method of manufacturing a semiconductor device according to the second embodiment of the present invention will be described. 12 to 19 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

Referring to FIG. 12, logic elements are formed on the first semiconductor substrate 100. That is, logic elements may be formed on the first semiconductor substrate 100 by forming NMOS and PMOS transistors 110 and 112, a resistor (not shown), a diode (not shown), and wires (not shown). have.

In detail, the device isolation layers 102 may be formed in the first semiconductor substrate 100 to define an active region. Subsequently, the gate insulating layer and the gate conductive layer are stacked and patterned on the first semiconductor substrate 100 in which the active region is defined, thereby forming the gate electrodes 110. After the gate electrode 110 is formed, impurities are ion implanted into the first semiconductor substrate 100 on both sides of the gate electrode 110 to form the source / drain regions 112. Accordingly, transistors may be formed on the first semiconductor substrate 100.

Subsequently, an insulating material having excellent step coverage is deposited on the transistors 110 and 112 to form the first interlayer insulating film 120. Here, a resistor (not shown), a diode (not shown), and wires (not shown) may be buried in the first interlayer insulating layer 120.

Referring to FIG. 13, lower information storage elements are formed on a first interlayer insulating layer 120 having logic elements embedded therein. In an embodiment of the present invention, capacitors may be formed as lower information storage elements.

In more detail, the first electrodes 132, which are plate electrodes, are formed on the first interlayer insulating layer 120 having logic elements embedded therein. That is, a first electrode conductive film having a sufficient thickness is deposited on the first interlayer insulating layer 120, and a photolithography process is performed on the first electrode conductive film to form first pillars 132 having a pillar shape. do. In this case, the first electrodes 132 to which the ground voltage is applied may be electrically connected to each other.

After the first electrodes 132 are formed, a dielectric film (not shown) and a conductive film for the second electrode are conformally formed on the surface of the first electrode 132. Thereafter, the conductive film for the second electrode is etched to separate the second electrode conductive film into the second electrodes 134. That is, second electrodes 134 may be formed to conformally cover the surface of the pillar-shaped first electrode 132 and be separated from each other. In this case, the second electrodes 134 may be formed as a storage node electrode and have a cylindrical shape open downward.

After the capacitors 132 and 134 are formed, the second interlayer insulating layers 140 and 150 made of oxide are deposited on the entire surface of the resultant. In this case, the top surfaces of the second interlayer insulating layers 140 and 150 may be planarized by chemical mechanical polishing (CMP) or an etch back process. Thereafter, contact plugs 162 and conductive pads 172 connected to the second electrode 134 may be formed.

On the other hand, the lower information storage elements on the first interlayer insulating film 120 in which the logic elements are embedded, have low resistance, low stress, good step coverage, and good coefficient of thermal expansion in order to reduce influence from subsequent high temperature processes. It may be formed of a refractory metal material having. That is, the first and second electrodes 132 and 134 of the capacitor, the contact plug 162 and the conductive pad 172 may be formed of a refractory metal material. Examples of such refractory metal materials include tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium nitride film (TiN), tantalum nitride film (TaN), zirconium nitride film, and tungsten nitride film (TiN). And alloys thereof. In addition, the first and second electrodes 132 and 134 of the capacitor may be formed of a polysilicon film. Accordingly, even if the high temperature subsequent process (that is, the process of forming switching elements) is performed, the electrical characteristics and reliability of the lower information storage element can be maintained.

Referring to FIG. 14, the third interlayer insulating layer 180 covering the conductive pads 172 positioned on the lower capacitors 132 and 134 is formed and planarized. Subsequently, a bonding layer 190 for bonding the second semiconductor substrate 200 is formed on the third interlayer insulating layer 180 positioned on the uppermost layer on the first semiconductor substrate 100.

The bonding layer 190 may use, for example, various curable adhesives such as photo-setting adhesives such as reaction curable adhesives, thermosetting adhesives, and ultraviolet curable adhesives, and anaerobic adhesives. Or metal-based Ti, TiN, Al, etc.), epoxy-based, acrylate-based, silicon-based, and the like.

Here, when the bonding layer 190 is formed of a metal material, the metal material may be formed of a material that melts at a lower temperature than the conductive materials formed in the contact plugs 162 and the conductive lines 172. In addition, the bonding layer 190 may be reflowed at a low temperature during the planarization process in order to prevent voids that may be formed due to microscopic non-uniformity of the surface during bonding with the second semiconductor substrate 200. Form into material. That is, the bonding layer 190 may increase the bonding strength when the second semiconductor substrate 200 is adhered to the upper portion, and may serve to reduce fine defects that may occur during bonding.

Next, the second semiconductor substrate 200 is bonded to the bonding layer 190.

In more detail, a single crystal semiconductor substrate including the impurity layer 201 doped with impurities uniformly to a predetermined depth is prepared as the second semiconductor substrate 200. The impurity layer 201 may be formed by ion implanting impurities into the single crystal semiconductor substrate or by adding impurities during the epitaxial layer growth process for forming the single crystal semiconductor substrate. In addition, within a predetermined depth of the single crystal semiconductor substrate, a separation layer 207 may be formed in contact with the impurity layer 201. The separation layer 207 is a strained layer formed by a pore of a fine hole, an insulating film such as an oxide film or a nitride film, an organic adhesive layer, or a crystal lattice of a substrate (for example, Si-Ge). Can be. In addition, the bonding layer 209 may also be formed on the surface of the impurity layer 201.

Thereafter, the second semiconductor substrate 200 is bonded on the bonding layer 190 such that the impurity layer 201 of the second semiconductor substrate faces the bonding layer 190 of the first semiconductor substrate 100. After the second semiconductor substrate 200 is bonded onto the bonding layer 190, heat treatment may be performed while applying a predetermined pressure to increase the bonding strength.

Referring to FIG. 15, after the second semiconductor substrate 200 is completely bonded onto the bonding layer 190, all portions except the single crystal semiconductor impurity layer 201 are removed. Accordingly, the single crystal semiconductor impurity layer 201 doped with n-type or p-type impurities may be formed on the bonding layer 190 made of a metal material.

In more detail, the single crystal semiconductor region is ground or polished until the separation layer 207 is exposed in the bonded second semiconductor substrate 200. After the separation layer 207 is exposed, an anisotropic or isotropic etching process is performed to expose the surface of the impurity layer.

The exposing the impurity layer 201 may be selectively etched on the single crystal semiconductor substrate because the impurity concentration gradients of the impurity layer 201 and the separation layer 207 are different in the second semiconductor substrate. Alternatively, only the single crystal semiconductor impurity layer 201 doped with impurities due to a physical impact on the separation layer 207 and a crack formed along the separation layer 207 having a weak crystal lattice is formed on the bonding layer 190. can do.

Next, switching elements having a horizontal channel, that is, transistors, may be formed on the bonded single crystal semiconductor impurity layer 201.

In more detail, the device isolation layer 202 is formed in the bonded single crystal semiconductor impurity layer 201 to define an active region. Then, the gate insulating layer and the gate conductive layer patterns are formed on the single crystal semiconductor impurity layer 201 to form the gate electrodes 210. The source / drain regions 212 and 214 are formed by doping impurities into the single crystal semiconductor impurity layer 201 on both sides of the gate electrodes 210. Here, a common source region 212 may be formed between the adjacent gate electrodes 210. The drain region 214 may be formed in the single crystal semiconductor impurity layer 201 spaced apart from the source region 212 and adjacent to the sidewall of the gate electrode 210. In addition, when forming transistors, predetermined drain regions 214 may be formed on upper capacitors 132 and 134.

In addition, the source / drain regions 212 and 214 on both sides of the gate electrodes 210 may be formed by performing an ion implantation and annealing process of impurities. At this time, the ion implantation and annealing process of the impurities may be performed at a high temperature (about 800 ~ 850 ℃). As such, when the high temperature process is performed, the lower information storage elements (for example, electrodes and wirings) formed under the switching elements may be formed of a refractory metal material, thereby preventing a decrease in reliability due to high temperature. .

Referring to FIG. 16, a fourth interlayer insulating layer 220 covering the transistors 210, 212, and 214 formed on the second semiconductor substrate 200 is formed. Contact holes 221 are formed through the fourth interlayer insulating layer 220 and the second semiconductor substrate 220 to expose the conductive line 172 on the lower capacitors 132 and 134.

After forming the contact holes 221, an insulating film may be deposited along the surface of the contact hole 221 and anisotropically etched to form an insulating spacer 222 in the form of a spacer on the inner wall of the contact hole 221. The insulating spacer 222 may prevent the bonding layer 190 made of a conductive material from being exposed by the contact hole 221.

Referring to FIG. 17, a conductive material is partially filled in the contact hole 221 penetrating the second semiconductor substrate 200 to complete the contact plug 224 for the lower storage node. In this case, the contact plug 224 for the lower storage node may be buried up to the surface of the second semiconductor substrate 200 and electrically connected to the drain region 214 formed in the second semiconductor substrate 200.

Referring to FIG. 18, a fifth interlayer insulating layer filling a contact hole is formed on the fourth interlayer insulating layer 220. Thereafter, contact plugs 232 for bit lines are formed in the fourth and fifth interlayer insulating layers 220 and 230 to contact the common source region 212. In forming the bit line contact plug 232, contact plugs electrically connected to the logic elements may be formed. Thereafter, a bit line 234 is formed across the gate electrode 210 on the bit plug contact plugs 232. In addition, when the bit line 234 is formed, a conductive line (not shown) connected to the logic element may be formed together.

Referring to FIG. 19, a sixth interlayer insulating layer 240 covering the bit line 234 is formed, and a contact plug 242 for an upper storage node connected to the drain region 214 is formed in the sixth interlayer insulating layer 240. Form.

Although the upper storage node contact plug 242 and the bit line 234 overlap each other, the bit line 234 and the storage node contact plug 242 are electrically insulated in three dimensions.

On the contact plug 242 for the upper storage node, as described in the first embodiment of the present invention, the second electrodes 252 having a cylindrical shape open to the top may be formed. A dielectric film (not shown) and a first electrode 254 are formed on the second electrode 252. The first electrode 254 may fill the inside of the cylindrical second electrode 252.

Thereafter, an eighth interlayer insulating layer 270 covering the upper capacitors 252 and 254 is formed, and a contact plug 282 and a final metal wiring 292 connected to the logic elements 110 and 112 are formed.

20 to 27 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with a third embodiment of the present invention.

Referring to FIG. 20, a first semiconductor substrate on which logic elements are formed is prepared.

In detail, the transistors 110 and 112 are formed on the first semiconductor substrate 100, and the first interlayer insulating layer 120 covering the transistors 110 and 112 is formed. Contact plugs may be formed in the first interlayer insulating layer 120, and wirings 122 may be formed on the contact plugs. Thereafter, a second interlayer insulating film is formed to cover the wirings 122 connected to the transistors 110 and 112, and the top is planarized.

After the logic elements are formed on the first semiconductor substrate as described above, the bonding layer 140 is formed on the second interlayer insulating layer 130.

Referring to FIG. 21, a second semiconductor substrate 200 on which switching elements 210, 212, and 214 and first information storage elements 242 and 244 are formed is prepared. In detail, the second semiconductor substrate 200 may be a single crystal semiconductor substrate including an impurity layer doped with impurities uniformly to a predetermined depth. The single crystal semiconductor substrate includes an impurity layer from an upper surface to a predetermined depth. In addition, the isolation layer 205 may be included in contact with the impurity layer within a predetermined depth of the single crystal semiconductor substrate.

In addition, transistors 210, 212, and 214 having horizontal channels as switching elements are formed on the second semiconductor substrate 200. After forming the transistors, the transistors 210, 212, and 214 are buried in the first interlayer insulating layer 220, and then contact plugs 222 and bit lines 224 for bit lines connected to the common source region 212 of the transistors. ) In order. Subsequently, a second interlayer insulating layer 230 covering the bit line is formed, and contact plugs 232 for storage nodes are formed in the first and second interlayer insulating layers 220 and 230. Thereafter, capacitors 242 and 244 are formed on the contact plugs 232 for each storage node. That is, a third interlayer insulating film 240 having a sufficient thickness is formed on the second interlayer insulating film 230, and a storage node electrode 242 having a cylindrical shape is formed in the third interlayer insulating film 240. A dielectric film (not shown) and a plate electrode 244 are sequentially formed on the storage node electrode 242. Thereafter, after forming the fourth interlayer insulating layer 250 covering the capacitors 242 and 244, the bonding layer 255 is formed on the fourth interlayer insulating layer 250.

Referring to FIG. 22, a first semiconductor substrate 100 on which logic elements 110, 112, and 122 are formed, and a second on which switching elements 210, 212, and 214 and information storage elements 242 and 244 are formed. The semiconductor substrates 200 are bonded to each other.

That is, the bonding layer 140 formed on the first semiconductor substrate 100 and the bonding layer 255 formed on the second semiconductor substrate 200 face each other, so that the second layer is formed on the first semiconductor substrate 100. The semiconductor substrate 200 may be formed. Accordingly, the first information storage elements 242 and 244 and the switch elements 210, 212 and 214 are sequentially formed on the logic elements 110, 112 and 122.

Referring to FIG. 23, a portion of the rear surface of the second semiconductor substrate 200 is removed. Removing a portion of the second semiconductor substrate 200 may be controlled by the separation layer 205 formed in the second semiconductor substrate 200.

Thereafter, a contact plug 208 connected to the predetermined drain region 214 of the transistor is formed in the second semiconductor substrate 200.

Referring to FIG. 24, second information storage elements 262 and 264 are formed on the rear surface of the second semiconductor substrate 200. That is, capacitors 262 and 264 connected to the contact plug 208 may be formed on the rear surface of the second semiconductor substrate 200. That is, on the rear surface of the second semiconductor substrate 200, a streak node electrode 262 having a cylindrical shape opened upward is formed, and a dielectric film (not shown) and a sequence are sequentially formed on the surface of the storage node electrode 262. The plate electrode 264 is formed.

 After the capacitors 262 and 264 are formed, the contact plugs 272, 274 and 276 and the conductive line (ie, corresponding to the bit line 224, the gate electrode 210 and the logic elements 110 and 112, respectively) are formed. 278).

Thereafter, an interlayer insulating film 280 covering the conductive lines 278 is formed, and a bonding layer 285 is formed on the interlayer insulating film 280.

Referring to FIG. 25, a third semiconductor substrate 300 on which switching elements 310, 312, and 314 and third information storage elements 342 and 344 are formed is prepared and bonded to an upper portion of the third semiconductor substrate 300. After the layer 355 is formed, the layer 355 is bonded to the bonding layer 285 on the second semiconductor substrate 200. Here, forming the switching elements 310 and 312 and the third information storage elements 342 and 344 on the third semiconductor substrate 300, as shown in FIG. 21, the second semiconductor substrate 200. ) May be substantially the same as forming the switching elements 110, 112 and the second information storage elements 210, 212, 214.

Referring to FIG. 26, a portion of the rear surface of the third semiconductor substrate 300 is removed to form fourth information storage elements 362 and 364 electrically connected to the switching elements 310 and 312.

That is, a contact plug for a storage node connected to the drain region 314 of the transistor is formed in the third semiconductor substrate 300. Thereafter, capacitors 362 and 364 are formed on the contact plug for the storage node. Accordingly, third information storage elements 342 and 344 are formed under the switching elements 310 and 312, and fourth information storage elements 362 and 364 on the switching elements 310 and 312. ) May be formed.

Referring to FIG. 27, bit lines 324, contact plugs 372 and 374 and conductive lines 378 respectively connected to the bit line 324, the gate electrode 310 are formed on the third semiconductor substrate 300. In addition, the contact plugs 378 and the conductive line 378 connected to the lower logic elements 110, 112, and 122 are formed together. Thereafter, the final metal wiring 384 is formed on the contact plug 378 connected to the logic devices 110, 112, and 122.

As such, the semiconductor substrate on which the logic element is formed and the semiconductor substrate on which the switching element and the information storage elements are formed may be bonded to each other to form the switching element and the information storage elements on the logic element. In addition, the semiconductor substrate on which the switching elements and the information storage elements are formed may be repeatedly bonded to the upper portion of the logic element, thereby improving the integration degree of the semiconductor memory device.

28 to 37 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with a fourth embodiment of the present invention.

Referring to FIG. 28, a first semiconductor substrate 100 having a bonding layer 110 formed on a surface thereof is prepared. The first semiconductor substrate 100 may be a dummy semiconductor substrate on which an impurity layer or other elements are not formed.

In addition, the second semiconductor substrate 200 on which the switching elements 210, 212, and 214 and the first information storage elements 242 and 244 are formed is prepared. The second semiconductor substrate 200 includes a separation layer 205 that may serve as an etch stop layer when a part of the second semiconductor substrate 200 is removed in a subsequent process. The switching elements 210, 212, and 214 and the first information storage elements 242 and 244 are formed on the second semiconductor substrate 200 in the same manner as the method described with reference to FIG. 21. have. After forming the interlayer insulating layer 250 covering the first information storage elements 242 and 244, the bonding layer 255 is formed on the interlayer insulating layer 250.

Thereafter, the bonding layers 110 and 255 are bonded to each other so that the bonding layers 110 and 255 formed on the first and second semiconductor substrates 100 and 200 face each other. Accordingly, the second semiconductor substrate 200 may be positioned on the first semiconductor substrate 100 and the rear surface of the second semiconductor substrate 200 may be exposed.

Referring to FIG. 29, the information storage elements 242 and 244 and the switching elements 210 and 212 may be sequentially disposed on the first semiconductor substrate 100. Then, a part of the rear surface of the second semiconductor substrate 200 positioned at the uppermost portion is removed. Accordingly, the separation layer 205 formed in the second semiconductor substrate 200 may be removed.

Referring to FIG. 30, second information storage elements 262 and 264 are formed on the rear surface of the second semiconductor substrate 200. That is, the storage node contact plug 208 in contact with the drain region 214 is formed in the second semiconductor substrate 200. Thereafter, capacitors 242 and 244 are formed on the storage node contact plug 208. Subsequently, contact plugs 208 and wires 278 connected to the bit line 224 and the gate electrode 210 may be formed.

Referring to FIG. 31, a contact plug 120 connected from the first semiconductor substrate 100 to the wirings 278 is formed to connect to logic elements to be bonded through a subsequent process. Subsequently, a bonding layer 130 is formed on the rear surface of the first semiconductor substrate 100. Accordingly, the first semiconductor device 10 may be prepared.

Referring to FIG. 32, a second semiconductor device 20 having bonding layers 130 and 290 formed on a rear surface and an uppermost layer of the first semiconductor substrate 100 is prepared. Preparing the second semiconductor element 20 is substantially the same as preparing the first semiconductor element 10 as described with reference to FIGS. 28 to 31. However, in the case of the second semiconductor device 20, an upper portion of the first information storage elements 242 and 244, that is, a rear surface of the dummy semiconductor substrate 100 and the first information storage elements 262 and 264 may be formed. Bonding layers 130 and 290 may be formed thereon.

Referring to FIG. 33, a third semiconductor substrate 300 on which logic elements 310, 312, and 322 are formed is prepared. Transistors 310 and 312 and wirings 322 connected to the transistors 310 and 312 may be formed on the third semiconductor substrate 300.

34, a contact plug 340 is formed from the rear surface of the third semiconductor substrate 300 to the wiring 3322 on the third semiconductor substrate 300. In this case, the contact plug 340 may be formed through the third semiconductor substrate 300. In addition, a wiring 350 may be formed on the rear surface of the third semiconductor substrate 300 to be electrically connected to the logic elements 310 and 312.

Referring to FIG. 35, a bonding layer 360 for bonding other semiconductor devices 10 and 20 of FIG. 31 is formed on the uppermost layer of the third semiconductor substrate 300 on which the logic devices 310 and 312 are formed. . Here, the bonding layer 360 may be formed of a conductive material, and the logic elements 310 and 312 may be electrically connected to other semiconductor devices (10 and 20 of FIG. 31) through the bonding layer 360. . Accordingly, the third semiconductor device 30 including the logic devices 310 and 312 is prepared.

Referring to FIG. 36, on the third semiconductor device 30 including the logic devices 310 and 312, the third and fourth information storage devices 242, 244, 262, and 264 and the switching devices ( The second semiconductor device 20 including the 210, 212, and 214 is bonded to each other. The first semiconductor device 10 including the first and second information storage devices 242, 244, 262, and 264 and the switching devices 210 and 212 are bonded to the second semiconductor device 20. do.

Referring to FIG. 37, a semiconductor memory device in which information storage elements and switching elements are repeatedly formed on logic elements 310 and 312 is completed. The first to third semiconductor devices 10, 20, and 30 may be electrically connected to each other through bonding layers 130 and 290 formed of a conductive material.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the invention is indicated by the following claims rather than the above description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents are included in the scope of the invention. Should be.

1 to 11 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention.

12 to 19 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

20 to 27 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with a third embodiment of the present invention.

28 to 37 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with a fourth embodiment of the present invention.

Claims (38)

Forming first information storage elements on the first semiconductor substrate, Forming switching elements on the first information storage elements, Forming second information storage elements on the switching elements; And forming logic elements electrically connected to the switching elements under the first information storage elements. delete The method of claim 1, Forming the first or second information storage elements, Forming a first electrode connected to the switching element, a dielectric layer on the first electrode, and a second electrode on the dielectric layer. The method of claim 3, wherein And the first and second information storage elements are formed of a dielectric film, a ferroelectric film, or a phase change film. The method of claim 3, wherein Forming the first and second information storage elements, Forming a first electrode having a pillar shape connected to the switching element, Forming a dielectric layer conformally on the surface of the first electrode, And forming a second electrode conformally along the surface of the dielectric layer. The method of claim 3, wherein Forming the first and second information storage elements, Forming a first electrode having a cylindrical shape connected to the switching element, Forming a dielectric layer conformally on the surface of the first electrode, Forming a second electrode on the surface of the dielectric layer to fill the inside of the second electrode. The method of claim 1, Forming the switching elements, And bonding a second semiconductor substrate on the first information storage elements, and forming the switching elements on the second semiconductor substrate. The method of claim 7, wherein Before forming the switching elements, Forming an insulating layer covering the first information storage elements, And manufacturing the second semiconductor substrate on the insulating layer. The method of claim 8, Bonding the second semiconductor substrate, Providing a single crystal semiconductor substrate, Forming a plurality of impurity layers doped with impurities uniformly from an upper surface of the single crystal semiconductor substrate to a predetermined depth, Bonding the single crystal semiconductor substrate to the upper surface of the insulating layer and the impurity layer; Removing a portion of the single crystal semiconductor substrate until the impurity layer surface is exposed. The method of claim 9, After forming the plurality of impurity layers, And forming a separation layer in the single crystal semiconductor substrate at a depth in contact with the impurity layer. 11. The method of claim 10, The method for manufacturing a semiconductor memory device, wherein the separating layer is formed of a bubble layer. The method of claim 9, The forming of the plurality of impurity layers includes forming a p-type, n-type, or p-type impurity layer or an n-type, p-type, or n-type impurity layer from an upper surface of the single crystal semiconductor substrate. The method of claim 9, After bonding the second semiconductor substrate, Patterning the plurality of impurity layers to form impurity layer patterns, And forming the second information storage elements on the upper surfaces of the impurity layer patterns. The method of claim 13, The plurality of impurity layer patterns may include a channel region and source and drain regions above and below the channel region. The method of claim 14, After forming the impurity layer patterns, And forming a gate electrode surrounding the channel region to complete the switching elements. The method of claim 8, Bonding the second semiconductor substrate, Providing a single crystal semiconductor substrate including an impurity layer doped with impurities uniformly from an upper surface to a predetermined depth, Bonding the single crystal semiconductor substrate to the upper surface of the insulating layer and the impurity layer; Removing a portion of the single crystal semiconductor substrate until the impurity layer surface is exposed. The method of claim 16, Providing the single crystal semiconductor substrate, And a separation layer formed at a depth in contact with the impurity layer in the single crystal semiconductor substrate. The method of claim 16, Forming the switching elements, Forming gate electrodes on the second semiconductor substrate, and forming impurity regions on both sides of the gate electrodes. The method of claim 18, Forming the first information storage elements, A method of manufacturing a semiconductor memory device comprising forming a wiring layer formed of a metal material or a refractory metal material. The method of claim 19, The wiring layer may be formed of cobalt (Co), titanium (Ti), tungsten (W), nickel (Ni), platinum (Pt), hafnium (Hf), molybdenum (Mo), palladium (Pd), or titanium nitride film ( A method for manufacturing a semiconductor device, formed by any one selected from the group consisting of alloys consisting of TiN), tantalum nitride film (TaN), zirconium nitride film (ZrN), tungsten nitride film (WN), and combinations thereof. The method of claim 18, After forming the switching elements, And forming a contact plug penetrating the second semiconductor substrate to electrically connect the impurity region and the first information storage element. The method of claim 1, After forming the second information storage elements, Forming third information storage elements on the second information storage elements, Forming other switching elements on the third information storage elements, And forming fourth information storage elements on the other switching elements. Forming switching elements on the front surface of the first semiconductor substrate, Forming first information storage elements on the switching elements, the first information storage elements being electrically connected to the switching elements, On the rear surface of the first semiconductor substrate, forming second information storage elements electrically connected to the switching elements, And the first semiconductor substrate is a single crystal semiconductor substrate including an impurity layer doped with impurities uniformly from an upper surface to a predetermined depth and a separation layer at a depth in contact with the impurity layer. The method of claim 23, wherein Forming the first or second information storage elements, Forming a first electrode connected to the switching element, a dielectric layer on the first electrode, and a second electrode on the dielectric layer. 25. The method of claim 24, And the first and second information storage elements are formed of a dielectric film, a ferroelectric film, or a phase change film. The method of claim 23, wherein Forming the switching elements, Forming gate electrodes on the first semiconductor substrate, and forming impurity regions on both sides of the gate electrodes. The method of claim 26, Forming the first information storage elements, A method of manufacturing a semiconductor memory device comprising forming a wiring layer formed of a metal material or a refractory metal material. 28. The method of claim 27, The wiring layer may be formed of cobalt (Co), titanium (Ti), tungsten (W), nickel (Ni), platinum (Pt), hafnium (Hf), molybdenum (Mo), palladium (Pd), or titanium nitride film ( A method for manufacturing a semiconductor device, formed by any one selected from the group consisting of alloys consisting of TiN), tantalum nitride film (TaN), zirconium nitride film (ZrN), tungsten nitride film (WN), and combinations thereof. The method of claim 26, After forming the switching elements, And forming a contact plug penetrating the second semiconductor substrate to electrically connect the impurity region and the second information storage element. 25. The method of claim 24, Forming the first and second information storage elements, Forming a first electrode having a pillar shape connected to the switching element, Forming a dielectric layer conformally on the surface of the first electrode, And forming a second electrode conformally along the surface of the dielectric layer. 25. The method of claim 24, Forming the first and second information storage elements, Forming a first electrode having a cylindrical shape connected to the switching element, Forming a dielectric layer conformally on the surface of the first electrode, Forming a second electrode on the surface of the dielectric layer to fill the inside of the second electrode. delete The method of claim 23, wherein Before forming the second information storage elements, And removing a portion of the first semiconductor substrate until the impurity layer is exposed from a rear surface of the first semiconductor substrate. The method of claim 23, wherein Preparing a second semiconductor substrate under the first or second information storage elements; Forming logic elements on the second semiconductor substrate, the logic elements being electrically connected to the switching elements. The method of claim 23, wherein Forming the first information storage elements, and then forming a first insulating layer covering the first information storage elements, Forming the second information storage elements, and then forming a second insulating layer covering the second information storage elements. 36. The method of claim 35, And bonding a dummy semiconductor substrate on the first or second insulating layer. 37. The method of claim 36, Forming a bonding layer on the dummy semiconductor substrate. 36. The method of claim 35, Forming third information storage elements on the second insulating layer, Forming other switching elements on the third information storage elements, And forming fourth information storage elements on the other switching elements.

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