KR20100014308A - Solder bump interconnect for improved mechanical and thermo mechanical performance - Google Patents

Abstract

An apparatus and method for a semiconductor package including a bump on input-output (IO) structure are disclosed involving a device pad, an under bump metai pad (UBM), a polymer, and a passivation layer. The shortest distance from the center of the device pad to its outer edge, and the shortest distance from the center of the UBM to its outer edge are in a ratio from 0.5:1 to 0.95:1. Also, the shortest distance from the center of the polymer to its outer edge, and the shortest distance from the center of the UBM to its outer edge are in a ratio from 0.35:1 to 0.85:1. Additionally, the shortest distance from the center of the passivation layer to its outer edge, and the shortest distance from the center of the UBM to its outer edge are in a ratio from 0.35:1 to 0.80:1.

Description

SOLDER BUMP INTERCONNECT FOR IMPROVED MECHANICAL AND THERMO MECHANICAL PERFORMANCE

Related Applications

This application claims priority to US Provisional Application No. 60 / 913,337, filed April 23, 2007 and US Non-Provisional Application No. 12 / 107,009, filed April 21, 2008, all of which are incorporated by reference in their entirety. Included herein. US Provisional Application No. 60 / 913,337 relates to PCT Patent Application No. PCT / US05 / 39008, filed Oct. 28, 2005, which PCT application is also incorporated herein by reference in its entirety. PCT Patent Application PCT / US05 / 39008 relates to and claims priority in US Provisional Application No. 60 / 623,200, filed Oct. 28, 2004, and US Provisional Application No. 60 / 623,200, which is also incorporated by reference in its entirety herein. Included in

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Field

TECHNICAL FIELD This disclosure relates to the field of electronic wafer level chip scale packaging and flip chip packaging and assembly, and more particularly, to provide a solder bump interconnect structure with improved mechanical strength and impact resistance.

Typically, wire bonding has been used to provide electrical connections between semiconductor devices and external circuits. The semiconductor device is diced from the wafer on which it is manufactured and placed in a face-up form in a package. Next, small wires, typically made of gold or copper, are welded between the bond pads present on the semiconductor device and the external leads on the package.

Flip chip technology derives its name from the placement of semiconductor devices in a face down form in a package. By reflowing the conductive solder bumps on the surface of the semiconductor device, an electrical connection is made between the semiconductor device and the external leads of the package.

Flip chip technology allows a large number of electrical connections to be made, since the entire area of the semiconductor device can be used to form a bond pad, while bond pads are typically formed around the semiconductor device in wire bonding. do. Flip chip technology also facilitates fast electrical connections between semiconductor devices and external circuits by removing the resistance and capacitance associated with wire bonding.

Wafer-level chip-scale package ("WLCSP", Wafer-level chip-scale package) or wafer level package ("WLP", wafer level package) forms an electrical connection directly on the semiconductor device during fabrication of the semiconductor device. Thereby advances the concept of flip chips. This allows the semiconductor device to be mounted directly to a printed circuit board (“PCB”), thereby eliminating the need for a separate package. The resulting packaged device is scaled similarly to a bare semiconductor device. The WLCSP implementation benefits from further increases in electrical performance as well as smaller package sizes. The industrial transition from solder with lead metallurgy for WLCSP to non-lead metallurgy has resulted in increased sensitivity to the effects of thermo cycling and sudden mechanical shock for high reliability chip packaging. .

Redistribution layer ("RDL") technology allows older semiconductor device designs using bond pads to be positioned around the device using WLCSP. The RDL creates an electrical path between the bond pads on the semiconductor device and the solder bumps, allowing the solder bumps to be evenly distributed across the entire area of the semiconductor device.

FIG. 1 shows prior art bumps on the IO structure on the device pads prior to solder bumps, and FIG. 2A shows prior art bumps on the IO structure of FIG. 1 after solder bumps 106 have been applied. The device consists of a substrate 101, a device pad 102, and a passivation layer 103. Device pad 102 is typically a metallic material that includes aluminum, copper, or a combination of both materials. Device pad 102 may be formed using any of several methods commonly known in the art. The substrate 101 may include a material such as silicon, gallium arsenide, lithium tantalate, silicon germanium, or the like. For clarity, the substrate material will be generally referred to herein as silicon, but the use of this term should not be interpreted as intended to limit the present disclosure to silicon based substrates only.

Device passivation layer 103 typically includes silicon nitride, oxide nitride, and the like. The passivation layer 103 defines an opening free of passivation material, which is not continuous on the device pad, but rather referred to individually as a passivation opening. The passivation opening is shown in more detail in FIG. 2 showing the upper surface of the bumps on the IO structure of FIG. 1. The passivation opening is usually circular and is on the center of the device pad 102. The passivation opening defines the area where subsequent metals will be deposited during WLCSP processing or flip chip packaging processing for connection and attachment to the device pads.

Prior art for placing underlying bumps on IO structures, such as those shown in FIGS. 1 and 2, uses bumped metal pads ("") using standard metal deposition methods such as metal plating, metal sputtering, and the like. UBM ", under bump metal pad) 105. UBM 105 includes Ti (W) / Cu; Al / Electroless Ni / Immersion Au; Al / Electroless Ni / PdlAu; A1Cu / Electroless Ni / Immersion Au; AlCuSi / Electroless Ni / Immersion Au; And a large number of well known materials, including AlSi / Electroless Ni / Immersion Au. Because of the technology and materials used, UBM 105 may be attached to passivation material 103 and device pad 102, typically forming a layer of about 1.0 micron or greater. The top surface of the UBM 105 provides a place for solder bump placement and facilitates attachment of the solder bumps. 1 and 2, the UBM solder bump locations are defined by openings in the polymer 104.

Conventional prior art processes utilize polymeric materials composed of polyimide, benzocyclobutene ("BCB", benzocyclobutene), and the like. The thickness of the polymer 104 is typically 10 microns or less. The polymer 104 is typically photodefined to create an opening that is usually circular and on the center of the UBM 105. In this example, and in most of the prior art solder bumping structures, the diameter of the device pad 102 is greater than or equal to the diameter of the UBM 105, that is to say a ratio of 1: 1 or greater as a result. . In such prior art solder bumping structures, the diameter of the openings of the polymer 204 is typically smaller than the diameter of the UBM 105 at a rate of 0.86: 1 or less.

3 and 4 show cross-sectional and top views, respectively, of an alternative prior art bump on an IO structure. In this version of the prior art, the diameter of the device pad 302 is smaller than the diameter of the UBM 305 at a typical ratio of 0.43: 1. The diameter of the polymer openings is smaller than the diameter of the UBM 305 at a typical ratio of 0.32: 1. Prior art for disposing an underlying structure such as that shown in FIGS. 3 and 4 includes a polymer 304 such as polyimide, benzocyclobutene, polybenzoxazole, polybenzoxazole derivatives, or the like. And an opening in the device passivation layer 303 and on the device pad 302. The thickness of the polymer 304 is typically 10 microns or less. The polymer 304 is then defined as light to create an opening, usually circular, on the center of the device passivation opening and open to the surface of the device pad 302.

At this point in the process, the polymer 304 defines an area that is connected to the device passivation layer 303, which is in the opening of the device passivation layer 303. The open area of the polymer 304 is known as the polymer opening. Once the polymer openings are defined, the UBM 305 will be deposited via standard methods such as metal plating, metal sputtering, and the like. This process involves the bottom surface of the UBM 305 attached to the polymer 304, any exposed passivation portion of the device passivation layer 303 between the polymer 304 and the device pad 302, and the device pad 302 itself. If possible, the UBM 305 is formed. The upper side of the UBM 305 is a surface defined for solder bump placement and attachment.

In such structures, and in most of the lower solder bumping structures, the diameter of the device pad 302 is smaller than the diameter of the UBM 305, and typically has a ratio of 0.43: 1. This causes a significant overlap of the UBM 305 onto the device pad 302. In addition, the diameter of the opening of the polymer 304 is typically smaller than the diameter of the UBM 305, and typically has a ratio of 0.32: 1.

5 and 6 are cross-sectional views illustrating exemplary prior art redistribution layer (“RDL”) substructures prior to solder bumping. 6A is a cross-sectional view illustrating an exemplary prior art RDL substructure after solder bumps 507 have been applied. 7 is a plan view of the structure shown in FIGS. 5 and 6. RDL trace 505 is formed using standard metal deposition methods well known in the art. The RDL trace may be a single metal layer or a stacked metal layer such as titanium / aluminum / titanium or copper or aluminum or nickel copper or chromium / copper / chrome or the like. At the end of RDL trace 505, metal is typically formed in a circular pattern, resulting in landing pad 505a. Landing pad 505a provides a connection point for subsequent WLCSP or flip chip packaging processes. The landing pad may be a single metal layer or a stacked metal layer such as aluminum, aluminum / nickel / copper, titanium / aluminum / titanium or copper or nickel / gold / copper. Once trace 505 and landing pad 505a are formed, photodefineable polymer 2 material 506 is deposited over trace 505 and landing pad 505a. Next, an opening located in the central region of the landing pad 505a and exposing a portion of the landing pad 505a is defined in Polymer 2 material 506. All Polymer 2 material 506 outside the center of the landing pad remains intact and covers the trace 505. The thickness of the polymer 2 material 506 is typically 20 microns or less. UBM 507 is formed over Polymer 2 material 506 and on landing pad 505a to create an electrical connection between UBM 507 and landing pad 505a.

Typically, landing pad 505a has a diameter greater than or equal to the diameter of UBM 507. The ratio of conventional pad diameter to UBM diameter is 1: 1 or larger. The ratio of polymer 2 opening diameter to UBM diameter is typically 0.9: 1 or greater. 6A shows a typical solder bump on the RDL.

A popular trend in the semiconductor industry is to move to process technologies that use smaller feature sizes, which allow semiconductor devices to show more functionality. System-on-a-Chip ("SoC") devices are an example of a class of semiconductor devices made possible by smaller feature sizes and are simplified by the structures shown in FIGS. 3 and 4. Smaller feature sizes combined with greater functionality resulted in reduced input-output (“IO”) pad sizes, as shown in FIGS. 1 and 2 compared to FIGS. 3 and 4. The final IO pad geometry of the WLCSP application is significantly smaller than the required solder bumps, which allows for the creation of narrow neck structures between the solder bumps and the final IO pad geometry. Narrow connections cause instability and inconsistency with the solder bumps, further increasing the solder bump's sensitivity to temperature cycling and sudden mechanical shock.

Accordingly, mechanical drop tests, mechanical shock or vibration tests, mechanical shear tests, temperature cycling, temperature shock tests, or other tests used in semiconductor package testing, especially when rigid solder composites other than leaded solder composites are used for solder bumps. It would be desirable to obtain an improved semiconductor package that provides enhanced mechanical and thermomechanical performance in reliability tests, such as. This disclosure is directed to solder bump interconnect structures that substantially eliminate one or more problems due to the limitations and disadvantages of the related art.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the present disclosure, or may be taught by practice of the invention. The objects and other advantages of the invention will be realized and attained by the structure particularly pointed out in this written description, including any claims and appended drawings, which are incorporated herein.

In some embodiments, a redistribution chip scale package is provided having a final metal pad and a substrate having a final metal pad size. The device passivation layer deposited over the final metal pad has a passivation opening, where the device passivation layer is locally removed to expose the bottom final metal pad. The polymer layer deposited over the passivation layer has a polymer opening, where the polymer opening is locally removed to expose the lower final metal pad. The conductive layer deposited over the polymer layer is patterned to provide traces and landing pads, which landing pads have a landing pad length. The polymer layer deposited over the conductive layer with the polymer layer openings is locally removed to expose the lower landing pads. The bump bottom metal layer deposited over the polymer layer has a final bump bottom metal size and bump bottom metal overhang. The ratio of polymer opening diameter to final bump bottom metal diameter is in the range of about 0.35: 1 to about 0.85: 1. The ratio of landing pad diameter to final bump bottom metal diameter is in the range of about 0.5: 1 to about 0.95: 1. In embodiments where the bump bottom metal and other regions have an approximately circular geometry, the defined lengths correspond to their diameters.

In some embodiments, a solder bump on IO chip scale package having a final metal pad and a substrate having a final metal pad size is provided. The device passivation layer deposited over the final metal pad has a passivation opening, where the device passivation layer is locally removed to expose the bottom final metal pad. The polymer layer deposited over the passivation layer has a polymer opening, where the polymer opening is locally removed to expose the lower final metal pad. The bump bottom metal layer deposited over the polymer layer has a final bump bottom metal size. The ratio of polymer opening to final bump bottom metal size is in the range of about 0.35: 1 to about 0.85: 1. The ratio of final metal pad size to final bump bottom metal size is in the range of about 0.5: 1 to about 0.95: 1. The ratio of passivation opening to final bump bottom metal size is in the range of about 0.35: 1 to about 0.80: 1. In embodiments where the bump bottom metal and other regions have an approximately circular geometry, the defined lengths correspond to their diameters.

The foregoing general description and the following detailed description are both illustrative and illustrative, and further description of the disclosed solder bump interconnect structures with improved thermomechanical strength and drop test performance will be provided.

The accompanying drawings, which are incorporated in and constitute a part of this specification, to provide a further understanding of the disclosed solder bump interconnect structures with improved thermomechanical strength and drop test performance, illustrate exemplary embodiments. Together with the description and description, it is provided to illustrate the principles of at least one embodiment of the disclosed solder bump interconnect structure with improved thermomechanical strength and drop test performance.

1 shows a prior art bump on an IO structure on a device pad prior to solder bumping.

FIG. 2 is a plan view of bumps on the IO structure of FIG. 1. FIG.

2A illustrates a conventional prior art process for creating bumps on an IO structure on a device pad, including the generation of solder bumps.

3 shows an alternative prior art bump on the IO structure on the device pad prior to solder bumping.

4 is a plan view of bumps on the IO structure of FIG.

5 is a cross-sectional view of an exemplary prior art redistribution layer structure.

FIG. 6 is a detailed view of a portion of the redistribution layer structure shown in FIG. 5.

6A is a cross-sectional view of an exemplary prior art bump on an RDL structure, including solder bumps.

FIG. 7 is a plan view of the redistribution layer structure illustrated in FIG. 5.

8 is a cross-sectional view of an exemplary bump on an IO structure, according to one embodiment.

9 is a top view of an exemplary bump on the IO structure shown in FIG. 8.

10 is a cross-sectional view of an exemplary redistribution layer structure, according to one embodiment.

FIG. 11 is a detailed view of a portion of the redistribution layer shown in FIG. 10.

12 is a top view of the example redistribution layer structure shown in FIG. 10.

The following description and drawings illustrate specific embodiments that enable those skilled in the art to fully implement the systems and methods described herein. Other embodiments may incorporate structural, logical, process, and other changes and are intended to be within the scope of this disclosure. Examples are merely typical of the possible variants.

Elements implementing various embodiments of the present systems and methods are described below. Many elements can be constructed using well known structures. It should also be understood that the techniques of the present systems and methods may be implemented using various techniques.

The disclosure of certain embodiments of a solder bump interconnect structure with improved thermomechanical strength and drop test performance is now presented below. Semiconductor device packages are typically implemented as, for example, chip scale packages or wafer level packages as used for chip-on-board assembly applications, or as standard flip chip packages used in flip chip package applications. do. Examples of such implementations are described in US Pat. No. 6,441,487 (named Chip Scale Package Using Large Ductile Solder Balls, inventor: Elenius et al., Published August 27, 2002), US Pat. No. 5,844,304 (named Process) for Manufacturing Semiconductor Device and Semiconductor Wafer, inventor: Kata et al., published December 1, 1998; US Pat. No. 5,547,740, entitled Solderable Contacts for Flip Chip Integrated Circuit Devices, inventor: Higdon et al., August 1996 20), US Patent No. 6,251,501 (name of invention: Surface Mount Circuit Device and Solder Bumping Method Therefor, inventor: Higdon et al., Published June 26, 2001), and PCT Patent Application No. PCT / US05 / 39008 ( Title: Invention: Semiconductor Device Package with Bump Overlying a Polymer Layer, Inventor: Vrtis et al., Filed Oct. 28, 2005, each of which contains at least their own descriptions of packaging applications, structures, and fabrication methods. By reference to which is incorporated herein by reference.

An advantage of the disclosed interconnect structures is that they can take advantage of conventional fabrication techniques to achieve the desired increase in thermomechanical strength and drop test performance. The optimal substructure is disclosed to define the diameter of the UBM, the diameter of the polymer opening, the diameter of the device passivation opening, and the diameter of the device pad. Although described herein using circular geometries for UBMs, polymer openings, device passivation openings, and / or device pads, alternative geometries may be used instead without departing from the spirit or scope of the present disclosure. For example, in one embodiment, one or more of the structures may be defined using, but not limited to, a square geometry. In such embodiments, the length of one side of the structure may replace the corresponding diameter.

8 and 9 show example bumps on an IO structure, using the ratios described herein. 8 and 9, the ratio of the diameter of the device pad 802 to the diameter of the UBM 805 ranges from 0.5: 1 to a maximum of 0.95: 1. The ratio of the diameter of the opening of the polymer 804 to the diameter of the UBM 805 is in the range from 0.35: 1 to a maximum of 0.85: 1. The ratio of the diameter of the opening of the device passivation layer 803 to the diameter of the UBM 805 ranges from 0.35: 1 to a maximum of 0.80: 1. By using ratios of this size, the present bumps on the IO structure allow the forces associated with thermal and mechanical stress to be more evenly distributed throughout the bumps on the IO structure, thereby making the structure under adverse conditions as further described below. Improves the overall performance.

10, 11, and 12 illustrate exemplary RDL substructures. 10-12, the ratio of the diameter of the landing pad 1005a to the diameter of the UBM 1007 ranges from 0.5: 1 to a maximum of 0.95: 1. The ratio of the diameter of the opening of the second layer of polymer 1006 to the diameter of the UBM 1007 ranges from 0.35: 1 to a maximum of 0.85: 1. By using ratios of these sizes, the RDL substructure allows the forces associated with thermal and mechanical stress to be more evenly distributed throughout the RDL substructure, thereby further reducing the overall performance of the structure under adverse conditions, as described further below. To improve.

Joint Electron Device Engineering Council (JEDEC) The JESD22-B111 standard provides a way to evaluate the ability of a flip chip or the ability of a WLCSP to withstand the mechanical impact that semiconductor devices in dropped portable devices will experience. . The previous WLCSP failed before 100 drops. Various embodiments of the present invention as described herein have enhanced the drop test performance of the WLCSP to values greater than approximately 200%, and the WLCSP can now withstand more than 100 drops.

Through the implementation of the component geometries described herein, the new bump structures improve the ability of the entire structure to provide increased thermomechanical stability and to absorb shocks from sudden drops. As an example, with regard to thermomechanical stability, a temperature cycle test (TCT) with a failure rate of 5% to 95% confidence can be improved by more than 100% (in some cases exceeding 600 cycles). JEDEC drop test performance can be improved by more than 100%. In a second level test of TCT with Bump's JESDA104B on the IO implementation, the new structure generally showed the first failure at over 600 cycles. Similarly, drop tests of bumps on IO using the JESD22-B111 standard were passed without failure up to 800 drops. The redistribution bump structures survived the second level test results for TCT using JESDA104B for up to 1000 cycles, and the redistribution bump structures survived the JESD22-B111 standard drop test of up to 800 drops.

Although specific example apparatus and methods have been described above, those skilled in the art will recognize that many of the above steps may be rearranged and / or omitted in other embodiments. The above description of specific embodiments fully demonstrates the general nature of the present disclosure that those skilled in the art can readily modify and / or adapt the present invention for various applications without departing from the generic concept by applying current technology. . For example, additional polymer layers and redistribution traces may be used to form a plurality of metal layers (eg, up to five layers) over a semiconductor wafer. Accordingly, such adaptations and modifications are within the meaning and range of equivalents of the disclosed embodiments. The terms or expressions used herein are for the purpose of description and not of limitation.

Claims (18)

A semiconductor package comprising a bump on an input-output (IO) structure, the semiconductor package comprising: Device pads; Under bump metal pads (UBMs); Polymers; And Passivation layer Including, Wherein the ratio of the shortest distance from the center of the device pad to the outer edge of the device pad to the shortest distance from the center of the UBM to the outer edge of the UBM is in the range from 0.5: 1 to a maximum of 0.95: 1, Semiconductor package. The method of claim 1, wherein the ratio of the shortest distance from the center of the polymer to the outer edge of the polymer to the shortest distance from the center of the UBM to the outer edge of the UBM is within a range from 0.35: 1 to a maximum of 0.85: 1. That is, a semiconductor package. The method of claim 1, wherein the ratio of the shortest distance from the center of the passivation layer to the outer edge of the passivation layer to the shortest distance from the center of the UBM to the outer edge of the UBM ranges from 0.35: 1 to a maximum of 0.80: 1. A semiconductor package, which is in range. The method of claim 1, The ratio of the shortest distance from the center of the polymer to the outer edge of the polymer to the shortest distance from the center of the UBM to the outer edge of the UBM ranges from 0.35: 1 to a maximum of 0.85: 1, Wherein the ratio of the shortest distance from the center of the passivation layer to the outer edge of the passivation layer to the shortest distance from the center of the UBM to the outer edge of the UBM is in the range of 0.35: 1 to a maximum of 0.80: 1, Semiconductor package. The semiconductor package of claim 1, wherein forces associated with thermal and mechanical stress are more evenly distributed throughout the bumps on the IO structure. The semiconductor package of claim 1, wherein the device pad, the UBM, the polymer, and the passivation layer use a circular geometry. The semiconductor package of claim 1, wherein the device pad, the UBM, the polymer, and the passivation layer use a square geometry. The semiconductor package of claim 1, wherein the polymer is polyimide. The semiconductor package of claim 1, wherein the polymer is benzocyclobutene (“BCB”, benzocyclobutene). The semiconductor package of claim 1, wherein the polymer is polybenzoxazole. A semiconductor package comprising a redistribution layer (RDL) substructure, Landing pads; Bump bottom metal pad (UBM); And Polymer Including, Wherein the ratio of the shortest distance from the center of the landing pad to the outer edge of the landing pad to the shortest distance from the center of the UBM to the outer edge of the UBM is in the range from 0.5: 1 up to 0.95: 1, Semiconductor package. The method of claim 11, wherein the ratio of the shortest distance from the center of the polymer to the outer edge of the polymer to the shortest distance from the center of the UBM to the outer edge of the UBM is within a range from 0.35: 1 to a maximum of 0.85: 1. That is, a semiconductor package. The semiconductor package of claim 11, wherein forces associated with thermal and mechanical stress are more evenly distributed throughout the RDL substructure. The semiconductor package of claim 11, wherein the landing pad, the UBM, and the polymer use a circular geometry. The semiconductor package of claim 11, wherein the landing pad, the UBM, and the polymer use a square geometry. The semiconductor package of claim 11, wherein the polymer is polyimide. The semiconductor package of claim 11, wherein the polymer is benzocyclobutene (BCB). The semiconductor package of claim 11, wherein the polymer is polybenzoxazole.

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