TWI785867B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes a substrate, a plurality of pads, a passivation layer, a dielectric layer, and a plurality of conductive bumps. The pads are disposed on the substrate. The passivation layer is disposed on the substrate, and the passivation layer exposes the plurality of pads. The dielectric layer covers a part of the passivation layer and includes a plurality of dielectric openings to expose the pads. The dielectric layer includes organic material. The conductive bumps are disposed in the dielectric openings and connect the pads respectively. A gap between the conductive bumps substantially equal to or smaller than 20μm.

Description

Semiconductor device and manufacturing method thereof

The present disclosure relates to a semiconductor device and a manufacturing method thereof.

Reducing the size of semiconductor devices and improving the integration of semiconductor devices are two major trends in semiconductor device manufacturing. As a result of these trends, the density of cells forming semiconductor devices is increasing. The shrinking of semiconductor components to sub-micron dimensions requires that routine fabrication of semiconductor component units also take place on the sub-micron scale.

Typically, wafers are made using many thin film layers. Each of these layers can be formed using a mask (such as a photoresist) that determines the pattern of that layer. The accuracy of this pattern is critical in fabricating the wafer. As the spacing between the conductive bumps of the chip becomes smaller and smaller, the aspect ratio of the photoresist used to form the small-pitch conductive bumps will also become larger, that is, to define the conductive bumps The thickness of the photoresist wall will become thinner and more fragile, so in the subsequent electroplating process, it is easy to cause photoresist peeling due to thermal stress. In this way, since the integrity of the photoresist cannot be maintained during the subsequent process (such as the electroplating process), the accuracy of key patterns in semiconductor device manufacturing is adversely affected, thereby affecting the process yield.

The invention provides a semiconductor device and a manufacturing method thereof, which can reduce the problem of photoresist stripping and improve the process yield.

An embodiment of the present invention provides a semiconductor device, which includes a substrate, a plurality of pads, a passivation layer, a dielectric layer, and a plurality of conductive bumps. The pads are disposed on the substrate. The passivation layer is disposed on the substrate, and the passivation layer exposes the pads. The dielectric layer covers part of the passivation layer and includes a plurality of openings in the dielectric layer to expose the pads, wherein the material of the dielectric layer includes organic materials. The conductive bumps are disposed in the opening of the dielectric layer and connected to the pads, wherein the distance between the conductive bumps is substantially equal to or less than 20 microns.

Another embodiment of the present invention provides a method of manufacturing a semiconductor device, which includes the following steps. forming a plurality of first contact pads on a substrate; forming a passivation layer on the substrate, wherein the passivation layer exposes the plurality of contact pads; forming a dielectric layer on the passivation layer, wherein the dielectric layer includes a plurality of dielectric layer openings to expose A plurality of contact pads; a photoresist layer is arranged on the dielectric layer, wherein the photoresist layer includes a plurality of photoresist openings corresponding to the plurality of dielectric layer openings; an electroplating process is performed to form a plurality of conductive bumps on the plurality of photoresist openings and the corresponding plurality of dielectric layer openings; and removing the photoresist layer.

Based on the above, by adding a dielectric layer between the passivation layer and the photoresist layer, the semiconductor device and its manufacturing method of the present disclosure can greatly reduce the thickness of the photoresist layer used to form the conductive bumps, thereby reducing the thickness of the photoresist layer. The aspect ratio can reduce the problem of insufficient structural strength caused by the excessive aspect ratio of the photoresist layer. Therefore, the semiconductor device disclosed in this disclosure can effectively reduce the thermal stress of the photoresist layer in the subsequent thermal process (such as electroplating process). The phenomenon of photoresist stripping occurs, thereby improving the process yield.

The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed descriptions of the embodiments with reference to the drawings. The directional terms mentioned in the following embodiments, such as "upper", "lower", "front", "rear", "left", "right", etc., are only referring to the directions of the attached drawings. Accordingly, the directional terms used are illustrative, not limiting, of the invention. Also, in the following embodiments, the same or similar components will be given the same or similar symbols.

1 to 6 are schematic cross-sectional views of a manufacturing process of a semiconductor device according to an embodiment of the present invention. In this embodiment, the manufacturing method of the semiconductor device 100 (as shown in FIG. 6 ) may include the following steps. Referring to FIG. 1 first, a plurality of pads 120 can be formed on the substrate 110 . For the sake of brevity, the components on the substrate 110 are omitted in FIGS. 1-6 , but those skilled in the art should understand that the substrate 110 may further include components such as one or more active devices and reconfiguration circuit layers. In one embodiment, the pads 120 may include a plurality of first pads 120a and a plurality of second pads 120b, wherein the pitch P1 between the first pads 120a is smaller than the pitch between the second pads 120b ( Refer to the pitch P2 in FIG. 7 ). In other words, the substrate 110 may include a first region R1 where the first pads 120a are formed and a second region R2 where the second pads 120b are formed, wherein the distance between the first pads 120a in the first region R1 is P1 is smaller, and the pitch P2 of the second pads 120b located in the second region R2 is larger. In this embodiment, the pitch P1 between two adjacent first pads 120a may be substantially equal to or smaller than 20 micrometers.

Next, a passivation layer 130 is formed on the substrate 110 , wherein the passivation layer 130 may include a plurality of passivation layer openings 132 for exposing the pads 120 respectively. In this embodiment, the passivation layer 130 covers the first region R1 and the second region R2 and exposes the first pad 120 a and the second pad 120 b through the passivation layer opening 132 . In detail, the passivation layer 130 may surround and cover peripheral portions of the first pad 120a and the second pad 120b, and include passivation layer openings 132 exposing the first pad 120a and the second pad 120b respectively. The material of the passivation layer 130 may include silicon nitride, silicon oxynitride, silicon dioxide, titanium dioxide or other suitable (inorganic) dielectric materials. In this embodiment, the passivation layer 130 can be deposited by chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), atomic layer deposition (Atomic layer deposition, ALD) or other suitable formed by the process. In this embodiment, the thickness of the passivation layer 130 is less than about 1 micron (µm). For example, the passivation layer 130 may have a thickness between about 0.4 μm and about 0.8 μm, but not limited thereto.

FIG. 7 is a schematic top view of a semiconductor device according to an embodiment of the present invention. Referring to FIG. 2 and FIG. 7 , a dielectric layer 140 is formed on the passivation layer 130 , wherein the dielectric layer 140 includes a plurality of dielectric layer openings 142 to expose the first pads 120a. In some embodiments, the dielectric layer 140 may cover the first region R1 formed with the first pads 120a, and respectively expose the first pads 120a through the dielectric layer openings 142 . Therefore, the dielectric layer 140 covers at least a part of the passivation layer 130 between the first pads 120a, and the dielectric layer openings 142 may respectively correspond to the passivation layer openings 132 exposing the first pads 120a. In this embodiment, as shown in FIG. 2 , the dielectric layer 140 does not cover (that is, expose) the second region R2 where the second pad 120b is formed, that is, the dielectric layer 140 will expose A portion of the passivation layer 130 between the pads 120b. In an alternative embodiment, the dielectric layer 140 may also cover the first region R1 and the second region R2 at the same time, and include a plurality of dielectric layer openings 142 respectively exposing the first pad 120a and the second pad 120b . In one embodiment, the material of the dielectric layer 140 includes organic materials that can be formed by suitable fabrication techniques (such as spin coating, etc.), such as polyimide (Polyimide, PI), benzocyclobutene (Benzocyclobutene, BCB ), polybenzoxazole (Polybenzoxazole, PBO) or other suitable organic dielectric materials. Since the dielectric layer 140 includes organic materials with relatively large molecules, the thickness T2 of the dielectric layer 140 may be substantially greater than the thickness T1 of the passivation layer 130 . For example, the dielectric layer 140 may have a thickness between about 3 µm and about 15 µm. Therefore, disposing the dielectric layer 140 in the first region R1 where the pitch P1 of the contact pads 120a is small can reduce the thickness of the photoresist layer 160 to be formed subsequently, thereby reducing the aspect ratio of the photoresist layer 160 , Further, the structural strength of the photoresist layer 160 is enhanced.

After that, referring to FIG. 3 , an under bump metallization layer (Under Bump Metallization) 150 is formed on the dielectric layer 140 and the pads 120 exposed by the dielectric layer 140 . In this embodiment, the UBM layer 150 first covers the upper surface of the structure shown in FIG. 130 and the contact pads 120 a , 120 b exposed by the dielectric layer 140 and the passivation layer 130 , and the under bump metallization layer 150 may cover the sidewalls of the dielectric layer opening and the passivation layer opening. The UBM layer 150 can be formed, for example, by sputtering or electroplating. In this embodiment, the UBM layer 150 can be a single metal layer or a composite metal layer, that is, composed of multiple metal layers, and the present disclosure is not limited thereto.

Referring to FIG. 4 , a photoresist layer 160 is formed on the dielectric layer 140 , wherein the photoresist layer 160 may include a plurality of photoresist openings 162 corresponding to the openings of the dielectric layer. In detail, the photoresist layer 160 can fully cover the upper surface of the structure shown in FIG. A plurality of photoresist openings 162 are formed, and the photoresist openings 162 can expose the UBM layer 150 on the pads 120a, 120b. In this embodiment, the sidewalls of the photoresist opening 162 can be aligned with the sidewalls of the dielectric layer opening 142 . That is to say, at least in the first region R1 , the opening for forming the conductive bump (the conductive bump 170 shown in FIG. 5 ) is jointly defined by the photoresist opening 162 and the dielectric layer opening 142 . In this way, since the dielectric layer 140 is added between the passivation layer 130 and the photoresist layer 160, the thickness D1 of the photoresist layer 160 can be reduced, thereby reducing the aspect ratio of the photoresist layer 160 and improving the thickness of the photoresist layer 160. Structural strength. For example, the distance W1 between two adjacent photoresist openings 162 in the first region R1 may be between about 6 micrometers and about 20 micrometers, and, at least in the first region R1, the photoresist layer 160 A ratio of the thickness to the distance W1 between two adjacent photoresist openings 162 is substantially equal to or less than one.

Please refer to FIG. 5 , and then perform an implantation metal process, which for example forms a plurality of conductive bumps 170 in the photoresist opening 162 of the photoresist layer 160 and the corresponding dielectric layer opening 142 by electroplating, and the conductive bumps 170 Covering the under bump metal layer 150 . That is to say, the UBM layer 150 is located between the pads 120 a , 120 b and the conductive bump 170 , and the conductive bump 170 is connected to the pads 120 a , 120 b through the UBM layer 150 . In this embodiment, the conductive bump 170 includes a first conductive bump 170a located in the first region R1 connected to the first pad 120a and a second conductive bump located in the second region R2 connected to the second pad 120b 170b, and the spacing between the second conductive bumps 170b is greater than the spacing between the first conductive bumps 170a. In this embodiment, the first conductive bump 170a located in the first region R1 is surrounded by the dielectric layer 140, and the second conductive bump 170b located in the second region R2 is disposed on the passivation layer 130 and is not surrounded by the dielectric layer 140. surrounded by a dielectric layer 140 . Certainly, in the embodiment where the dielectric layer 140 is disposed in the first region R1 and the second region R2 at the same time, the second conductive bump 170 b can also be surrounded by the dielectric layer 140 . In particular, the conductive bump 170 can be made of the following materials, such as gold, silver, copper, copper/nickel/gold or other suitable conductive materials.

Next, referring to FIG. 6 and FIG. 7 , a photoresist removal process is performed to remove the photoresist layer 160 . Afterwards, a process of removing the UBM layer 150 is performed, for example, removing a portion of the UBM layer 150 exposed by the conductive bumps 170a and 170b by etching. In this way, the remaining UBM layer 150 is located under the conductive bumps 170a, 170b, and can expose the passivation layer 130 and the dielectric layer 140 below. So far, the semiconductor device 100 of this embodiment can be roughly formed. In terms of structure, the shortest distance W2 between the first conductive bumps 170a is substantially equal to or smaller than 20 micrometers. Further, the shortest distance W2 between the first conductive bumps 170a is substantially between about 6 microns and about 20 microns. Here, the shortest distance W2 between the first conductive bumps 170a refers to the distance between the outer surfaces of two adjacent first conductive bumps 170a that are closest to each other. In this embodiment, the thickness T3 of the conductive bump 170 is substantially between about 5 microns and about 20 microns, and the thickness T2 of the dielectric layer 140 is substantially between about 3 microns and about 15 microns. The thickness T3 of the conductive bump 170 minus the thickness T2 of the dielectric layer 140 is the distance D2 from the top surface of the first conductive bump 170a to the top surface of the dielectric layer 140. In this embodiment, this distance D2 is the same as A ratio of the shortest distance W2 between two adjacent first conductive bumps 170 a is substantially equal to or less than one.

In summary, the disclosed semiconductor device and its manufacturing method can greatly reduce the thickness of the photoresist layer used to form the conductive bumps by adding a dielectric layer between the passivation layer and the photoresist layer, thereby reducing the photoresist The aspect ratio of the layer reduces the problem of insufficient structural strength caused by the excessively large aspect ratio of the photoresist layer. The phenomenon of photoresist peeling due to thermal stress can improve the process yield.

In addition, since the problem of too large aspect ratio of the photoresist layer is more serious in the area where the pitch of the conductive bumps is smaller, the present disclosure can only arrange the dielectric layer in the area of the smaller pitch of the conductive bumps to reduce the The thickness of the photoresist layer in the area where the distance between the conductive bumps is small makes the aspect ratio of the photoresist layer relatively similar among the regions of the semiconductor device, thereby improving the process yield.

100: Semiconductor device 110: Substrate 120: Pad 120a: first pad, pad 120b: second pad, pad 130: passivation layer 132: Passivation layer opening 140: dielectric layer 142: dielectric layer opening 150: Under bump metal layer 160: photoresist layer 162: photoresist layer opening 170: Conductive bump 170a: first conductive bump, conductive bump 170b: second conductive bump, conductive bump D1, D2: distance R1: Region 1 R2: second area T1, T2, T3: Thickness W1, W2: Spacing

1 to 6 are schematic cross-sectional views of a manufacturing process of a semiconductor device according to an embodiment of the present invention. FIG. 7 is a schematic top view of a semiconductor device according to an embodiment of the present invention.

110: Substrate

120a: first pad, pad

120b: second pad, pad

130: passivation layer

140: dielectric layer

142: dielectric layer opening

150: Under bump metal layer

160: photoresist layer

162: photoresist layer opening

D1: distance

R1: Region 1

R2: second area

W1: Spacing

Claims (14)

A semiconductor device, comprising: a substrate; a plurality of first pads disposed on the substrate; a passivation layer disposed on the substrate, and the passivation layer exposes the plurality of first pads; a dielectric layer, Covering part of the passivation layer and including a plurality of dielectric layer openings to expose the plurality of first pads, wherein the material of the dielectric layer includes an organic material; and a plurality of first conductive bumps disposed on the plurality of dielectric layers Layer openings and connected to the plurality of first pads, wherein the distance between the plurality of first conductive bumps is substantially equal to or less than 20 microns, a plurality of second pads, disposed on the substrate, wherein the passivation layer exposing the plurality of second pads; and a plurality of second conductive bumps disposed on the passivation layer and connected to the plurality of second pads, wherein the distance between the plurality of second conductive bumps is greater than the The distance between the plurality of first conductive bumps. The semiconductor device as claimed in claim 1, wherein the thickness of the dielectric layer is substantially greater than the thickness of the passivation layer. The semiconductor device as claimed in claim 1, further comprising an under-bump metal layer disposed between the plurality of first pads and the plurality of first conductive bumps, and covering the openings of the plurality of dielectric layers side wall. The semiconductor device as claimed in claim 1, wherein the distance between the top surface of each of the plurality of first conductive bumps and the top surface of the dielectric layer is equal to the distance between the plurality of first conductive bumps The ratio is substantially equal to or less than one. The semiconductor device as claimed in claim 1, wherein the thickness of the dielectric layer is substantially between 3 microns and 15 microns. The semiconductor device as claimed in claim 1, wherein the material of the dielectric layer includes polyimide (Polyimide, PI), benzocyclobutene (Benzocyclobutene, BCB) or polybenzoxazole (Polybenzoxazole, PBO). The semiconductor device as claimed in claim 1, wherein the passivation layer surrounds and covers peripheral portions of the plurality of first pads and includes a plurality of passivation layer openings exposing the plurality of first pads, the plurality of dielectric The layer openings respectively correspond to the plurality of passivation layer openings. The semiconductor device according to claim 1, wherein the dielectric layer covers at least part of the passivation layer between the plurality of first pads. The semiconductor device according to claim 1, wherein the dielectric layer exposes a portion of the passivation layer between the plurality of second pads. A method of manufacturing a semiconductor device, comprising: forming a plurality of contact pads on a substrate, wherein the plurality of contact pads include a plurality of first contact pads and a plurality of second contact pads; forming a passivation layer on the substrate, wherein The passivation layer exposes the plurality of contact pads; forming a dielectric layer on the passivation layer, wherein the dielectric layer includes a plurality of dielectric layer openings to expose the plurality of contact pads; disposing a photoresist layer on the dielectric layer layer, wherein the photoresist layer includes corresponding to the multiple A plurality of photoresist openings in the dielectric layer openings; performing an electroplating process to form a plurality of conductive bumps in the plurality of photoresist openings and the corresponding plurality of dielectric layer openings, wherein the plurality of conductive bumps include multiple a first conductive bump and a plurality of second conductive bumps, the plurality of first conductive bumps are connected to the plurality of first pads, the plurality of second conductive bumps are arranged on the passivation layer and connected to the plurality of conductive bumps a second pad, the distance between the plurality of second conductive bumps is greater than the distance between the plurality of first conductive bumps; and removing the photoresist layer. The method of manufacturing a semiconductor device as claimed in claim 10, wherein a ratio of the thickness of the photoresist layer to the distance between the plurality of photoresist openings is substantially equal to or less than 1. The method of manufacturing a semiconductor device as claimed in claim 10, wherein the distance between the plurality of conductive bumps is substantially equal to or smaller than 20 microns. The method for manufacturing a semiconductor device according to claim 10, further comprising: before disposing the photoresist layer on the dielectric layer, forming an under bump metal layer on the dielectric layer and exposed by the dielectric layer on the multiple pads. The method of manufacturing a semiconductor device as claimed in claim 13 further includes: after removing the photoresist layer, removing the portion of the under-bump metal layer exposed by the plurality of conductive bumps.

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