CN105977177A - Semiconductor structure avoiding semiconductor test failure and semiconductor test method - Google Patents
Semiconductor structure avoiding semiconductor test failure and semiconductor test method Download PDFInfo
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- CN105977177A CN105977177A CN201610307798.3A CN201610307798A CN105977177A CN 105977177 A CN105977177 A CN 105977177A CN 201610307798 A CN201610307798 A CN 201610307798A CN 105977177 A CN105977177 A CN 105977177A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention provides a semiconductor structure avoiding semiconductor test failure and a semiconductor test method. The semiconductor which avoids the semiconductor test failure caused by cracks of a passivation layer comprises a metal layer arranged on a wafer, the passivation layer arranged on the metal layer, a polyamide layer formed in the top and sidewalls of the passivation layer, an intermediate layer covering part of the metal layer and at least part of the polyamide layer, and a connecting layer arranged on the intermediate layer.
Description
Technical field
The present invention relates to semiconductor manufacturing and field tests, it is more particularly related to a kind of solve by
Cause the semiconductor structure that semiconductor test is failed in passivation layer crack, and invention relates further specifically to one
Plant corresponding semiconductor test method.
Background technology
The whole flow process of the manufacture of semiconductor chip is mainly by several main portions such as design, wafer manufacture, tests
It is grouped into.After semi-conductor silicon chip completes all making technologies, can carry out respectively for the various structures on silicon chip
Plant testing electrical property.By the analysis to test data, it appeared that the problem in manufacture of semiconductor technique, side
Making technology is helped to be adjusted.
For some power devices, some particular clients often require that and carry out the automobile product for temperature cycles
Reliability quality test；And under this test, test temperature is typically in the range of-55 DEG C to 150 DEG C.
In the prior art, when carrying out the automobile product reliability quality test for temperature cycles, often
There will be the situation of test crash.
For this reason it would be desirable to a kind of reliability that can be efficiently modified the specialities for temperature cycles can be provided
The technical scheme of the rate that is successfully tested of quality test.
Summary of the invention
The technical problem to be solved is for there is drawbacks described above in prior art, it is provided that Yi Zhongneng
Enough it is efficiently modified the quasiconductor of the rate that is successfully tested of the reliability quality test of the specialities for temperature cycles
Structure and semiconductor test method.
In order to realize above-mentioned technical purpose, according to the first aspect of the invention, it is provided that a kind of solution quasiconductor
The semiconductor structure of test crash, causes semiconductor test failure for solution due to passivation layer crack, wraps
Include: be arranged in the metal level of wafer, arrange passivation layer on the metal layer, at the top of passivation layer and sidewall
The aramid layer of upper formation, cover metal level a part and cover aramid layer at least one of in
Interbed and arrange articulamentum on the intermediate layer.
Preferably, passivation layer is made up of the teos layer stacked from bottom to top and silicon nitride layer.
In the semiconductor structure that solution semiconductor test according to the first aspect of the invention is failed, by increasing
Add the aramid layer that passivation layer is completely covered, be effectively prevented or alleviate owing to passivation layer ruptures shape
The crack that becomes and the failure of the reliability quality test of the specialities for temperature cycles that causes.
Additionally, in order to realize above-mentioned technical purpose, according to the second aspect of the invention, it is provided that a kind of solution
The semiconductor structure that semiconductor test is failed, causes semiconductor test to lose for solution due to passivation layer crack
Lose, including: it is arranged in the metal level of wafer, the aramid layer being directly arranged on metal level, covers metal
Layer a part and cover aramid layer at least one of intermediate layer and arrange connect on the intermediate layer
Connect layer.
Preferably, described metal level is top-level metallic interconnection layer, and intermediate layer is by titanium coating and nickel metal
Layer composition.
In the semiconductor structure that solution semiconductor test according to a second aspect of the present invention is failed, by using
Aramid layer replaces passivation layer, is effectively prevented or alleviates owing to passivation layer ruptures splitting of formation
The failure of the reliability quality test of the specialities for temperature cycles stitched and cause.
Additionally, in order to realize above-mentioned technical purpose, according to the third aspect of the invention we, it is provided that one is partly led
Body examination method for testing, including: forming predetermined semiconductor structure, wherein said predetermined semiconductor structure includes: cloth
Put wafer metal level, arrange passivation layer on the metal layer, formed on the top and sidewall of passivation layer
Aramid layer, cover metal level a part and cover aramid layer at least one of intermediate layer,
And arrange articulamentum on the intermediate layer；Described predetermined semiconductor structure is performed semiconductor test program.
Same, the aramid layer of passivation layer is completely covered by increase, be effectively prevented or alleviate by
The crack of formation is ruptured and the reliability quality of the specialities for temperature cycles that causes in passivation layer
The failure of test.
Preferably, described semiconductor test method is for the test of power device.
Preferably, described semiconductor test method is for the semiconductor test relevant with temperature.
Additionally, in order to realize above-mentioned technical purpose, according to the fourth aspect of the invention, it is provided that one is partly led
Body examination method for testing, including: forming predetermined semiconductor structure, wherein said predetermined semiconductor structure includes: cloth
Put at the metal level of wafer, the aramid layer being directly arranged on metal level, cover a part for metal level also
And cover at least one of intermediate layer of aramid layer and arrange articulamentum on the intermediate layer；To described
Predetermined semiconductor structure performs semiconductor test program.
Preferably, described semiconductor test method is for the test of power device.
Preferably, described semiconductor test method is for the semiconductor test relevant with temperature.
Same, by using aramid layer to replace passivation layer, it is effectively prevented or alleviates due to blunt
Change layer and rupture the crack of formation and the reliability quality test of the specialities for temperature cycles that causes
Failure.
Accompanying drawing explanation
In conjunction with accompanying drawing, and by with reference to detailed description below, it will more easily the present invention is had more complete
Understand and its adjoint advantage and feature is more easily understood, wherein:
Fig. 1 schematically shows the microscopic view of the passivation layer rift defect that prior art exists.
Fig. 2 schematically shows the sectional view of the semiconductor structure according to prior art.
Fig. 3 schematically shows the solution semiconductor test failure according to first preferred embodiment of the invention
The sectional view of the first example of semiconductor structure.
Fig. 4 schematically shows the solution semiconductor test failure according to first preferred embodiment of the invention
The sectional view of the second example of semiconductor structure.
Fig. 5 schematically shows the flow process of the semiconductor test method according to second preferred embodiment of the invention
Figure.
It should be noted that accompanying drawing is used for illustrating the present invention, and the unrestricted present invention.Note, represent structure
Accompanying drawing may be not necessarily drawn to scale.Further, in accompanying drawing, same or like element indicate identical or
The label that person is similar to.
Detailed description of the invention
In order to make present disclosure more clear and understandable, below in conjunction with specific embodiments and the drawings to this
Bright content is described in detail.
For the ease of understanding the principle of the present invention, first problem of the prior art it is further analyzed and says
Bright.
Inventors herein have recognized that, in prior art, the automobile product reliability quality for temperature cycles is surveyed
Why examination can lose efficacy, and its main cause is that passivation layer there occurs and ruptures thus form crack (Fig. 1 is schematic
Show the microscopic view of passivation layer rift defect that prior art exists), just because of the crack of passivation layer
Result in the failure of the reliability quality test of the specialities for temperature cycles.
Based on above-mentioned discovery, inventor proposes the following concrete scheme of the present invention.
The semiconductor structure according to prior art is briefly described referring initially to Fig. 2.As in figure 2 it is shown, prior art
Semiconductor structure include: be arranged in wafer 100 metal level 10, be arranged on metal level 10 by under
And tetraethyl orthosilicate (TEOS) layer 21 of upper stacking and the passivation layer of silicon nitride layer 22 composition, cover metal
The part of layer 10 and cover at least one of intermediate layer 30 of silicon nitride layer 22 (intermediate layer 30 is general
Be made up of titanium coating and nickel metal layer), be arranged on intermediate layer 30 articulamentum 40 (articulamentum 40 typically by
Silver is formed).
But, as previously described, this structure easily owing to passivation layer ruptures thus forms crack, is entered
And result in the failure of the reliability quality test of the specialities for temperature cycles.
Describe below according to a particular embodiment of the invention.
<the first example of semiconductor structure>
Fig. 3 schematically shows the solution semiconductor test failure according to first preferred embodiment of the invention
The sectional view of the first example of semiconductor structure.
Specifically, as it is shown on figure 3, lose according to the solution semiconductor test of first preferred embodiment of the invention
First example of the semiconductor structure lost includes: be arranged in metal level 10 (such as, the described gold of wafer 100
Belong to layer 10 be probably top-level metallic interconnection layer), be arranged on metal level 10 by the positive silicon stacked from bottom to top
Ethyl acetate layer 21 and the passivation layer of silicon nitride layer 22 composition, formed on the top and sidewall of passivation layer poly-
Amide layer 50 (that is, aramid layer 50 is completely covered passivation layer), cover the part of metal level 10 and cover
At least one of intermediate layer 30 of lid aramid layer 50 (such as, intermediate layer 30 typically by titanium coating and
Nickel metal layer form), be arranged in articulamentum 40 (such as, articulamentum 40 is typically formed) on intermediate layer 30 by silver.
Preferably, the thickness of aramid layer 50 is about 7um.
The first of the failed semiconductor structure of semiconductor test is being solved according to first preferred embodiment of the invention
In example, the aramid layer of passivation layer is completely covered by increase, is effectively prevented or alleviates due to blunt
Change layer and rupture the crack of formation and the reliability quality test of the specialities for temperature cycles that causes
Failure.
<the second example of semiconductor structure>
Fig. 4 schematically shows the solution semiconductor test failure according to first preferred embodiment of the invention
The sectional view of the second example of semiconductor structure.
Specifically, as shown in Figure 4, lose according to the solution semiconductor test of first preferred embodiment of the invention
Second example of the semiconductor structure lost includes: be arranged in metal level 10 (such as, the described gold of wafer 100
Belong to layer 10 and be probably top-level metallic interconnection layer), the aramid layer 50 that is directly arranged on metal level 10, cover
The part of metal level 10 and cover at least one of intermediate layer 30 of aramid layer 50 (in such as,
Interbed 30 is typically made up of titanium coating and nickel metal layer), be arranged on intermediate layer 30 articulamentum 40 (such as,
Articulamentum 40 is typically formed by silver).
Preferably, the thickness of aramid layer 50 is about 7um.
The first of the failed semiconductor structure of semiconductor test is being solved according to second preferred embodiment of the invention
In example, by using aramid layer to replace passivation layer, it is effectively prevented or alleviates due to passivation layer
The mistake of the reliability quality test of the specialities for temperature cycles rupturing the crack of formation and cause
Lose.
<semiconductor test method>
Fig. 5 schematically shows the flow process of the semiconductor test method according to second preferred embodiment of the invention
Figure.
Specifically, as it is shown in figure 5, according to the semiconductor test method bag of second preferred embodiment of the invention
Include:
First step S1: form predetermined semiconductor structure, before wherein said predetermined semiconductor structure can be
The semiconductor structure described with reference to Fig. 3, it is also possible to be the semiconductor structure of earlier in respect of figures 4 description.
Second step S2: described predetermined semiconductor structure is performed semiconductor test program.Such as, quasiconductor
Test program is the test program for power device, and such as, semiconductor test program be for temperature
Spend relevant test program.
In other words, described semiconductor test method may be advantageously used with the test of power device, and, institute
State semiconductor test method and may be advantageously used with the semiconductor test relevant with temperature.
Furthermore, it is necessary to explanation, unless stated otherwise or point out, otherwise the term in description " first ",
" second ", " the 3rd " etc. describe be used only for distinguishing in description each assembly, element, step etc., and not
It is intended to indicate that the logical relation between each assembly, element, step or ordering relation etc..
Although it is understood that the present invention discloses as above with preferred embodiment, but above-described embodiment is also
It is not used to limit the present invention.For any those of ordinary skill in the art, without departing from skill of the present invention
In the case of art aspects, technical solution of the present invention is made many by the technology contents that all may utilize the disclosure above
Possible variation and modification, or it is revised as the Equivalent embodiments of equivalent variations.Therefore, every without departing from this
The content of bright technical scheme, according to the present invention technical spirit to any simple modification made for any of the above embodiments,
Equivalent variations and modification, all still fall within the range of technical solution of the present invention protection.
Claims (10)
1. solve the semiconductor structure that semiconductor test is failed, lead due to passivation layer crack for solution
Induced semiconductor test crash, it is characterised in that including: be arranged in the metal level of wafer, arrange on the metal layer
Passivation layer, on the top and sidewall of passivation layer formed aramid layer, cover metal level a part also
And cover at least one of intermediate layer of aramid layer and arrange articulamentum on the intermediate layer.
The semiconductor structure that solution semiconductor test the most according to claim 1 is failed, it is characterised in that
Passivation layer is made up of the teos layer stacked from bottom to top and silicon nitride layer.
3. solve the semiconductor structure that semiconductor test is failed, lead due to passivation layer crack for solution
Induced semiconductor test crash, it is characterised in that including: be arranged in the metal level of wafer, be directly arranged at metal
Aramid layer on layer, cover a part for metal level and cover at least one of centre of aramid layer
Layer and arrange articulamentum on the intermediate layer.
4. according to the semiconductor structure that the solution semiconductor test described in claim 1 or 3 is failed, its feature
Being, described metal level is top-level metallic interconnection layer, and intermediate layer is made up of titanium coating and nickel metal layer.
5. a semiconductor test method, it is characterised in that including:
Forming predetermined semiconductor structure, wherein said predetermined semiconductor structure includes: be arranged in the metal of wafer
Layer, arrange passivation layer on the metal layer, the aramid layer formed on the top and sidewall of passivation layer, cover
The part of lid metal level and cover at least one of intermediate layer of aramid layer and be arranged in centre
Articulamentum on layer；
Described predetermined semiconductor structure is performed semiconductor test program.
Semiconductor test method the most according to claim 5, it is characterised in that described semiconductor test
Method is for the test of power device.
7. according to the semiconductor test method described in claim 5 or 6, it is characterised in that described quasiconductor
Method of testing is for the semiconductor test relevant with temperature.
8. a semiconductor test method, it is characterised in that including:
Forming predetermined semiconductor structure, wherein said predetermined semiconductor structure includes: be arranged in the metal of wafer
Layer, the aramid layer being directly arranged on metal level, cover the part of metal level and cover aramid layer
At least one of intermediate layer and arrange articulamentum on the intermediate layer；
Described predetermined semiconductor structure is performed semiconductor test program.
9. want the semiconductor test method described in 8 according to right, it is characterised in that described semiconductor test side
Method is for the test of power device.
Semiconductor test method the most according to claim 8 or claim 9, it is characterised in that described partly lead
Body examination method for testing is for the semiconductor test relevant with temperature.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610307798.3A CN105977177A (en) | 2016-05-11 | 2016-05-11 | Semiconductor structure avoiding semiconductor test failure and semiconductor test method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610307798.3A CN105977177A (en) | 2016-05-11 | 2016-05-11 | Semiconductor structure avoiding semiconductor test failure and semiconductor test method |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050048755A1 (en) * | 2003-08-26 | 2005-03-03 | Roche Thomas S. | Method of forming a bond pad |
| CN101636831A (en) * | 2007-04-23 | 2010-01-27 | 弗利普芯片国际有限公司 | Solder bump interconnect for improved mechanical and thermo mechanical performance |
| CN102142413A (en) * | 2010-02-01 | 2011-08-03 | 台湾积体电路制造股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN102376638A (en) * | 2010-08-12 | 2012-03-14 | 台湾积体电路制造股份有限公司 | Process for making conductive post with footing profile |
-
2016
- 2016-05-11 CN CN201610307798.3A patent/CN105977177A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050048755A1 (en) * | 2003-08-26 | 2005-03-03 | Roche Thomas S. | Method of forming a bond pad |
| CN101636831A (en) * | 2007-04-23 | 2010-01-27 | 弗利普芯片国际有限公司 | Solder bump interconnect for improved mechanical and thermo mechanical performance |
| CN102142413A (en) * | 2010-02-01 | 2011-08-03 | 台湾积体电路制造股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN102376638A (en) * | 2010-08-12 | 2012-03-14 | 台湾积体电路制造股份有限公司 | Process for making conductive post with footing profile |
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Application publication date: 20160928 |