CN103208472B - There is the compound semiconductor integrated circuit of three-D elements - Google Patents
There is the compound semiconductor integrated circuit of three-D elements Download PDFInfo
- Publication number
- CN103208472B CN103208472B CN201210008722.2A CN201210008722A CN103208472B CN 103208472 B CN103208472 B CN 103208472B CN 201210008722 A CN201210008722 A CN 201210008722A CN 103208472 B CN103208472 B CN 103208472B
- Authority
- CN
- China
- Prior art keywords
- compound semiconductor
- semiconductor integrated
- electronic component
- integrated circuit
- elements according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention is about a kind of compound semiconductor integrated circuit with three-D elements, as a kind of weld pad or inductance is arranged in three dimensions the compound semiconductor integrated circuit above electronic component.At weld pad or its thickness of dielectric layer of inserting between inductance and electronic component between 10 to 30 microns, the impact that this structure causes element function therefore effectively can be reduced.Can arrange a protective layer is covered in avoid being subject to the pollution of the metal material being formed weld pad or inductance above electronic component, and more cheap copper just can be used thus as the material of weld pad and inductance.This three-dimensional weld pad can be applicable in wire bonding technologies or bump bond technology.
Description
Technical field
The present invention is about a kind of compound semiconductor integrated circuit with three-D elements, espespecially a kind of above electronic component three-dimensional weld pad or inductance are set, and in inserting the compound semiconductor integrated circuit of a dielectric layer between the two.
Background technology
Along with the development of Mobile Communications industry, high integration, demand that is high-effect, the simple monocrystalline microwave integrated circuit (monolithicmicrowaveintegratedcircuits, MMIC) of fabrication schedule are also increased day by day.Traditionally, the assembly of monocrystalline microwave integrated circuit as transistor, electric capacity, resistance, inductance, signal I/o pad and between link be arrange in a two-dimensional manner, but weld pad need occupy the very large area of plane usually, the integration of chip cannot be promoted and increase the size of chip.For saving the area of plane shared by weld pad, so developed a kind of monocrystalline microwave integrated circuit of three-dimensional, normally weld pad is moved to above electronic component in this kind of circuit, and between weld pad and electronic component, insert a dielectric layer as electrical isolation, this dielectric layer can manufacture the pipeline that guide hole (viahole) links as the electrode of weld pad and electronic component.Thus, the three dimensional constitution that the element in monocrystalline microwave integrated circuit transfers to utilizing vertical space to replace plane space is arranged, and therefore can contribute to the reduction of chip size.
But, the monocrystalline microwave integrated circuit element so arranged in three dimensions may make the metal level in metal pad and electronic component respond to and produce electric capacity, in monocrystalline microwave integrated circuit, this inductance capacitance may be coupled with radio-frequency (RF) signal, and therefore reduces the usefulness of electronic component and the reliability of integrated circuit.
Except weld pad, inductance is also extremely space consuming element in monocrystalline microwave integrated circuit.For saving the area of plane shared by inductance, also inductance three dimensional constitution can be arranged at above electronic component, and in wherein inserting a dielectric layer.But, inductance is placed in the inductance capacitance caused above electronic component to be coupled with radio-frequency (RF) signal and also significantly can to reduce the usefulness of electronic component, particularly can cause the reduction of Q value, therefore arrange in the integrated circuit with element in three dimensions one, reduction inductance capacitance and the coupling of other radio-frequency (RF) signal are important topics on the impact of electronic component usefulness.
Traditionally, in the monocrystalline microwave integrated circuit of GaAs series, gold links material the most general for weld pad and interelement.Recently, because its comparatively low resistance and lower cost, copper becomes preferred material.But using copper to be that copper atom easily diffuses in dielectric layer as the shortcoming of the metal material of weld pad, the active area even diffusing to electronic component causes component wear.Especially, in some compound semiconductor, as GaAs series, copper system runs after fame with carrier killer; Enter the compound semiconductor region of electronic component once copper atom, namely can diffuse in semiconductor and also significantly change its characteristic electron.Therefore, for utilizing the advantage of copper pad, a reliable protective layer must be designed in this three-D elements, to avoid reducing or the problem of even component wear because copper atom spreads the element efficiency that causes.
Summary of the invention
Main purpose of the present invention is to provide a kind of compound semiconductor integrated circuit with three-D elements, wherein that a weld pad is placed in above electronic component, and in inserting a dielectric layer to provide electronic component and isolation enough between weld pad above it between the two, thus, while reducing chip size, also can reduce the impact that coupling capacitance causes electronic component usefulness.
For reaching above-mentioned purpose, the invention provides a kind of compound semiconductor integrated circuit, it sequentially comprises at least one electronic component, one first dielectric layer and a weld pad, and wherein this first dielectric layer is between this weld pad and this electronic component, and its thickness is between 10 to 30 microns.
Another object of the present invention is to provide a kind of compound semiconductor integrated circuit with three-D elements, wherein that an inductance is placed in above electronic component, and in inserting one first dielectric layer to provide electronic component and isolation enough between weld pad above it between the two, to fall the attenuation degree of low reactance-resistance ratio.
For reaching above-mentioned purpose, the present invention is to provide a kind of compound semiconductor integrated circuit, and sequentially comprise at least one electronic component, one first dielectric layer and an inductance, wherein this first dielectric layer is between this inductance and electronic component.
Another object of the present invention is to provide a kind of compound semiconductor integrated circuit with three-D elements; wherein that weld pad or inductance are placed in above electronic component; and weld pad and inductance are made up of copper; in weld pad or insert a dielectric layer between inductance and electronic component; and comprise a protective layer further and be covered in the upper of electronic component, to avoid the diffuse pollution from the copper in upper element.
In time implementing, this first dielectric layer can be made up of dielectric material polyphenyl oxazole (Polybenzoxazole, PBO).
In time implementing, this electronic component can be the stacking of a High Electron Mobility Transistor, a heteroj unction bipolar transistor, a film resistor, a diode, a metal-insulating layer-metal capacitor or a metal-insulating layer-metal capacitor.
In time implementing, the material forming this weld pad can be copper.
In time implementing, the material forming this protective layer can be silicon nitride (SiN).
In time implementing, on this weld pad, can form a metal column further, in bump bond technology, and the material forming this metal column can be copper.
In time implementing, the material forming this inductance can be copper.
For having a better understanding for feature of the present invention and interaction energy, after now coordinating graphic being specified in by embodiment.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view with the compound semiconductor integrated circuit of three-dimensional weld pad of the present invention.
Fig. 2 is the cross-sectional view with another structure of the combined type semiconductor integrated circuit of three-dimensional weld pad and metal column of the present invention.
Fig. 3 A, 3B and 3C are plan structure and the cross-sectional view with the combined type semiconductor integrated circuit of three-dimensional inductance of the present invention.
Fig. 4 is that isolation when being placed in above High Electron Mobility Transistor by a weld pad is to the analog result figure of input power.
Fig. 5 is that isolation degree of decay when being placed in above High Electron Mobility Transistor by a weld pad is to the analog result figure inserting medium thickness.
Fig. 6 inserts below the simulation Q value of medium thickness and inductance without analog result comparison diagram when any element difference for an inductance being placed in a metal-insulating layer-metal capacitor (MIM), stacking, the heteroj unction bipolar transistor power amplifier (HBTpowercell) of a metal-insulating layer-metal capacitor or a film resistor (TFR) top.
Fig. 7 A and 7B be three radio frequency pads of a SPDT switch to be placed in before above High Electron Mobility Transistor and after overlook schematic wiring diagram.
Description of reference numerals: 11-electronic component; 12-weld pad; 13-first dielectric layer; 14-metal level; 15-protective layer; 16-seed metal layer; 21-metal column; 22-second dielectric layer; 31-inductance; 312-inductance contact area one; 313-inductance contact area two; 32-metal-insulating layer-metal capacitor; 321-metal-insulating layer-metal capacitor the first metal layer; 322-metal-insulating layer-metal capacitor second metal level; 33-first dielectric layer; 30-substrate; 351-links metal level; 352-links metal level; 361-first silicon nitride layer; 362-second silicon nitride layer; 363-silicon nitride layer.
Embodiment
Fig. 1 is the cross-sectional view of combined type semiconductor integrated circuit of the present invention, and it comprises at least one electronic component 11, weld pad 12 and is positioned at above electronic component 11 and in one first dielectric layer 13 inserted between the two as electrical isolation.This electronic component 11 is formed on a compound semiconductor substrate, is wherein better with half insulation GaAs substrate.This electronic component 11 can be the stacking of a High Electron Mobility Transistor (HEMT), a heteroj unction bipolar transistor (HBT), a film resistor (TFR), a diode, a metal-insulating layer-metal capacitor (MIM) or a metal-insulating layer-metal capacitor.
The thickness of the first dielectric layer 13 between this electronic component 11 and this weld pad 12 is between 10 to 30 microns.Be enough to effectively reduce the coupling capacitance between this electronic component 11 and this weld pad 12 at the thickness of this scope, therefore can reduce the impact that coupling capacitance causes electronic component usefulness.
For carrying out qualitative estimation, try the conductive layer of weld pad 12, first dielectric layer 13 and below electronic component 11 thereof to be considered as a parallel plate capacitor, its capacitance C
paddetermined by following equation:
C
pad=ε S/d, equation (1)
Wherein S is the area area of weld pad (or under extreme case) of parallel plate capacitor, and d is the thickness of the first dielectric layer 13, and ε is the dielectric constant of dielectric medium.Suppose that pad area is common pad area, size is about 80 × 80 square microns, dielectric constant is that common dielectric medium is (as benzocyclobutene (Benzocyclobutene, and polyphenyl oxazole (Polybenzoxazole BCB), PBO)) DIELECTRIC CONSTANT ε=3.0, the capacitance C calculated
padto different dielectric layer thickness d listed by table one
| D (micron) | C pad(fF) |
| 3 | 56.7 |
| 5 | 34.0 |
| 7 | 24.3 |
| 10 | 17.0 |
| 15 | 11.3 |
| 20 | 8.5 |
| 25 | 6.8 |
| 30 | 5.7 |
Table one
For the inductance capacitance in single-pole double-throw switch (SPDT) (SPDTswitch), Fig. 7 A and 7B be prior art and single-pole double-throw switch (SPDT) of the present invention overlook schematic wiring diagram.The left element of figure by two be linked in sequence, bigrid High Electron Mobility Transistor (dual-gateHEMTs) that grid width is 2.625 millimeters formed, the element on the figure right side by two be linked in sequence, three grid High Electron Mobility Transistor (triple-gateHEMTs) that grid width is 3.375 millimeters are formed.In a traditional circuit, radio frequency pad 71 is arranged at High Electron Mobility Transistor periphery, as shown in Figure 7 A.And having in the circuit of three-D elements of the present invention, these three radio frequency pads 71 are the tops being arranged at High Electron Mobility Transistor, as shown in Figure 7 B.Carry out breadboardin when on the left side element is set to unlatching, right elements is set to closedown, the voltage that control circuit opens and cuts out is 0.5 volt and-3 volts respectively, and basic signal frequencies carries out radio-frequency performance under being set to the condition of 0.9 hertz be simulation.Consider worst condition, that is the simulation when weld pad electric capacity is between the source electrode of High Electron Mobility Transistor and drain electrode, its result display weld pad electric capacity C
padthe insertion loss of radio frequency usefulness and non-linearly have great impact.But, (the weld pad electric capacity C when medium thickness is 3 microns
pad=56.7fF), the isolation of SPDT switch compared with the non-existent situation of weld pad electric capacity under reduce 1.7 decibels.The result of simulation as shown in Figure 4, wherein lines A be medium thickness 3 microns and top has a weld pad time result, with top comparing (lines B) without result during weld pad.This simulation further shows the degree of decay of SPDT switch isolation along with medium thickness monotone decreasing, as shown in Figure 5.When medium thickness is for being greater than 10 microns, this decay is reduced to and is less than 0.6 decibel, and when medium thickness is for being greater than 20 microns, this decay is even reduced to and is less than 0.3 decibel.
This first dielectric layer 13 can be a spin-on dielectric matter, is formed on electronic component 11 via traditional rotary coating mode and program curing.For making the medium thickness of coating can reach 10 ~ 30 microns, dielectric layer material is better with polyphenyl oxazole (polybenzoxazole, PBO).At rotary rpm lower than below 1500rpm, the thickness after this material cured still can reach more than 10 microns.In addition, PBO dielectric medium is the photosensitive material that can manufacture various three-dimensional structure eurymeric photoresist layer on electronic component.Such as groove (trench) or guide hole (viahole) structure can be formed, as standard step such as exposure, development, solidifications with standard photolithography technique above element.
This weld pad 12 is electrically connected at one by the guide hole being arranged in the first dielectric layer 13 and is positioned at metal level 14 near electronic component 11, and this metal level 14 can further with arbitrary electrode of electronic component 11 or be positioned at neighbouring electronic component with other and be connected.
Gold is for being generally usually used in the material of integrated circuit, but the copper of low cost is better selection.But copper easily diffuses in other materials, cause the pollution of electronic component and substrate.As shown in Figure 1, the present invention can comprise a protective layer 15 further between electronic component 11 and the first dielectric layer 13, and this protective layer 15 can be used as the diffusion energy barrier of copper atom, and polluter therefore can be avoided to enter the diffusion of electronic component.This protective layer 15 is formed at the upper of the metal level 14 that the superiors are formed by gold usually, as shown in Figure 1.The material forming this protective layer 15 is better with silicon nitride.According to fabrication schedule of the present invention, copper weld pad be in all front-end process until the formation of silicon nitride protective layer complete after backend process in formed, so can avoid the diffuse pollution that copper occurs in front-end process, to safeguard the reliability of chip.One metal seed layer 16 can be used for copper-plating technique.The material forming this metal seed layer 16 is better with palladium, copper/titanium or copper/titanium tungsten.This metal seed layer 16 also can be used as the diffusion energy barrier of copper atom.
Fig. 2 is the cross-sectional view of another embodiment of the present invention, wherein on weld pad 12, comprises a metal column 21 further, and provides one second dielectric layer 22 to be covered in the use of conduct surface isolation on this weld pad 12.The material forming this metal column 21 is better with copper.This second dielectric layer 22 material is better with polyphenyl oxazole (PBO) dielectric material.The embodiment with metal column structures can be used for the bump bond technique in flip-chip type package technology.
Except three-dimensional weld pad, inductance can also be arranged on electronic component by three dimensional constitution, and in inserting a dielectric layer between the two.Wherein, this electronic component can be the stacking of a High Electron Mobility Transistor (HEMT), a heteroj unction bipolar transistor (HBT), a heteroj unction bipolar transistor power amplifier (HBTpowercell), a film resistor (TFR), a diode, a metal-insulating layer-metal capacitor (MIM) or a metal-insulating layer-metal capacitor.
Fig. 3 A be another embodiment of the present invention be positioned at the schematic top plan view that one on GaAs substrate 30 has the compound semiconductor integrated circuit of three-D elements, comprising an inductance 31, is the top being positioned at a metal-insulating layer-metal capacitor 32.Fig. 3 B is the cross-sectional view of AA ' line in Fig. 3 A.Inductance 31 is formed on one first dielectric layer 33; One second dielectric layer 34 is covered in the use as surface isolation on this inductance 31; Inductance 31 comprises two contact areas 312 and 313 further in its two ends; Contact area 312 and 313 by guide hole further be positioned at the first dielectric layer 33 under link metal level 351 and 352 contact.In application-specific example, this link metal level 351 and 352 can link (not being shown in Fig. 3) with other electronic components further.Fig. 3 C is the cross-sectional view through the BB ' line of this metal-insulating layer-metal capacitor 32 in Fig. 3 A.This metal-insulating layer-metal capacitor 32 is the belows being formed at this inductance 31 and this first dielectric layer 33.This metal-insulating layer-metal capacitor 32 comprises the first metal layer 321 and one second metal level 322 usually.For providing electrical isolation, one first silicon nitride layer 361 is formed on this GaAs substrate 30; This first metal layer 321 is formed at the upper of this first silicon nitride layer 361 and is covered by one second silicon nitride layer 362; This second metal level 322 is formed at the upper last of this second silicon nitride layer 362 and is covered by a silicon nitride layer 363.
This first dielectric layer 33 and this second dielectric layer 34 can be a spin-on dielectric matter, and it is formed via traditional rotary coating mode and program curing.This spin-on dielectric matter is better with polyphenyl oxazole (PBO), and when careful control rotary rpm, the thickness after this material cured can reach more than 10 microns.
The thickness of the first dielectric layer 33 between inductance and below electronic component thereof can affect the Q value of this integrated circuit.Fig. 6 is Q value when being placed in by an inductance above a metal-insulating layer-metal capacitor, stacking, the heteroj unction bipolar transistor power amplifier of a metal-insulating layer-metal capacitor or a film resistor and comparing without analog result when any element below inductance.As can be seen from Figure when PBO medium thickness increase and decrease hour, Q value also with decay.When PBO medium thickness is more than 10 microns, the fade of Q value is in a tolerable scope.Therefore, in a three-dimensional monocrystalline microwave integrated circuit, the dielectric medium optimum thickness between inductance and electronic component is an important consideration.
In sum, the compound semiconductor integrated circuit with three-D elements provided by the invention can reach the object of expection really, the function of the dielectric layer in integrated circuit of the present invention improves really, make while reducing chip size, also can reduce the impact that three-dimensional weld pad and induction structure cause electronic component usefulness.The value that its true tool industry utilizes, proposes patent application in accordance with the law.
Again above-mentioned explanation and graphic be only that embodiments of the invention are described, all ripe in the personage of this industry skill, still can do equivalence localized variation and modification, its do not depart from technology of the present invention with spirit.
Claims (18)
1. there is a compound semiconductor integrated circuit for three-D elements, it is characterized in that, comprising:
One electronic component, this electronic component is configured to a switch;
One weld pad, to be arranged at above this electronic component and overlapping with this electronic component at least partly in three dimensions;
One first dielectric layer is between this weld pad and this electronic component, and this first dielectric layer is configured to make the coupling capacitance between this electronic component and this weld pad be below 17fF, to reduce the isolation of this switch;
One guide hole is formed at this first dielectric layer using the use as electric connection; And
One metal level is the bottom being formed at this guide hole.
2. the compound semiconductor integrated circuit with three-D elements according to claim 1, is characterized in that, the dielectric material forming this first dielectric layer is polyphenyl oxazole.
3. the compound semiconductor integrated circuit with three-D elements according to claim 1, it is characterized in that, this electronic component comprises at least one electrode further.
4. the compound semiconductor integrated circuit with three-D elements according to claim 3, is characterized in that, the electrode of this electronic component comprises a contact area be connected with other elements further.
5. the compound semiconductor integrated circuit with three-D elements according to claim 3, is characterized in that, this electronic component with at least one electrode is a High Electron Mobility Transistor.
6. the compound semiconductor integrated circuit with three-D elements according to claim 3, is characterized in that, this electronic component with at least one electrode is heteroj unction bipolar transistor.
7. the compound semiconductor integrated circuit with three-D elements according to claim 1, is characterized in that, the material forming this weld pad is copper.
8. the compound semiconductor integrated circuit with three-D elements according to claim 1, is characterized in that, between this first dielectric layer and this electronic component, comprise a protective layer further.
9. the compound semiconductor integrated circuit with three-D elements according to claim 8, it is characterized in that, this protective layer is covered in this metal level at least partly.
10. the compound semiconductor integrated circuit with three-D elements according to claim 8 or claim 9, it is characterized in that, the material forming this protective layer is silicon nitride.
The 11. compound semiconductor integrated circuits with three-D elements according to claim 7, is characterized in that, between this first dielectric layer and this weld pad, comprise a metal seed layer further.
The 12. compound semiconductor integrated circuits with three-D elements according to claim 11, is characterized in that, the material forming this metal seed layer is palladium, copper/titanium or copper/titanium tungsten.
The 13. compound semiconductor integrated circuits with three-D elements according to claim 1, is characterized in that, on this weld pad, comprise a metal column further, in bump bond technology.
The 14. compound semiconductor integrated circuits with three-D elements according to claim 13, is characterized in that, cover one second dielectric layer further, for the protection of its understructure on this weld pad.
The 15. compound semiconductor integrated circuits with three-D elements according to claim 14, is characterized in that, the dielectric material forming this second dielectric layer is polyphenyl oxazole.
The 16. compound semiconductor integrated circuits with three-D elements according to claim 13, is characterized in that, the material forming this metal column is copper.
The 17. compound semiconductor integrated circuits with three-D elements according to claim 1, it is characterized in that, the thickness of this first dielectric layer is between 10 to 30 microns.
The 18. compound semiconductor integrated circuits with three-D elements according to claim 1, is characterized in that, this electronic component is a High Electron Mobility Transistor switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210008722.2A CN103208472B (en) | 2012-01-12 | 2012-01-12 | There is the compound semiconductor integrated circuit of three-D elements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210008722.2A CN103208472B (en) | 2012-01-12 | 2012-01-12 | There is the compound semiconductor integrated circuit of three-D elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103208472A CN103208472A (en) | 2013-07-17 |
| CN103208472B true CN103208472B (en) | 2016-03-02 |
Family
ID=48755647
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210008722.2A Expired - Fee Related CN103208472B (en) | 2012-01-12 | 2012-01-12 | There is the compound semiconductor integrated circuit of three-D elements |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103208472B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170040266A1 (en) | 2015-05-05 | 2017-02-09 | Mediatek Inc. | Fan-out package structure including antenna |
| FR3049761B1 (en) * | 2016-03-31 | 2018-10-05 | Soitec | METHOD FOR MANUFACTURING A STRUCTURE FOR FORMING A THREE DIMENSIONAL MONOLITHIC INTEGRATED CIRCUIT |
| CN111081675B (en) * | 2018-10-18 | 2024-04-12 | 源芯半导体股份有限公司 | Integrated circuit device with insulating capacitor and method of manufacturing the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW559874B (en) * | 2001-09-28 | 2003-11-01 | Kobe Steel Ltd | Method of forming aerial metal wiring on semiconductor substrate |
| US7939948B2 (en) * | 2005-01-10 | 2011-05-10 | Micron Technology, Inc. | Interconnect structures with bond-pads and methods of forming bump sites on bond-pads |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI245402B (en) * | 2002-01-07 | 2005-12-11 | Megic Corp | Rod soldering structure and manufacturing process thereof |
| KR100870178B1 (en) * | 2005-08-10 | 2008-11-25 | 삼성전자주식회사 | Semiconducotr devices having a metal-insulator-metal capacitor and methods of fabricating the same |
| US7973418B2 (en) * | 2007-04-23 | 2011-07-05 | Flipchip International, Llc | Solder bump interconnect for improved mechanical and thermo-mechanical performance |
-
2012
- 2012-01-12 CN CN201210008722.2A patent/CN103208472B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW559874B (en) * | 2001-09-28 | 2003-11-01 | Kobe Steel Ltd | Method of forming aerial metal wiring on semiconductor substrate |
| US7939948B2 (en) * | 2005-01-10 | 2011-05-10 | Micron Technology, Inc. | Interconnect structures with bond-pads and methods of forming bump sites on bond-pads |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103208472A (en) | 2013-07-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3969745A (en) | Interconnection in multi element planar structures | |
| US7265433B2 (en) | On-pad broadband matching network | |
| US7304859B2 (en) | Chip carrier and fabrication method | |
| CN102157487A (en) | Inductors and methods for integrated circuits | |
| CN103972226A (en) | Semiconductor integrated circuit | |
| CN103151338A (en) | Integrated circuit ground shielding structure | |
| WO1986002490A1 (en) | Wafer-scale-integrated assembly | |
| CN105826304A (en) | Chip Package | |
| CN104253095A (en) | Semiconductor package having wire bond wall to reduce coupling | |
| EP2741326B1 (en) | Shielding silicon from external RF interference | |
| US9768135B2 (en) | Semiconductor device having conductive bump with improved reliability | |
| CN103208472B (en) | There is the compound semiconductor integrated circuit of three-D elements | |
| US20080116541A1 (en) | Structure for integrating an rf shield structure in a carrier substrate | |
| Joseph et al. | Through-silicon vias enable next-generation SiGe power amplifiers for wireless communications | |
| KR20020079381A (en) | Inductance element and semiconductor device | |
| US20150279832A1 (en) | Compound semiconductor integrated circuit with three-dimensionally formed components | |
| CN108376679B (en) | Embedded harmonic terminal of high power RF transistor | |
| JP2005531143A (en) | Integrated circuit structures for mixed signal RF applications and circuits | |
| KR100621502B1 (en) | Manufacturing method of compound semiconductor device | |
| KR101212794B1 (en) | Semiconductor pacakge and method of manufacturing the same | |
| US20240138129A1 (en) | On-chip shielded device | |
| US20230317635A1 (en) | Rf chip, structure and method for rf chip guard-ring arrangement | |
| US20240096817A1 (en) | On-chip hybrid electromagnetic interference (emi) shielding with thermal mitigation | |
| WO2005067043A1 (en) | Monolithically integrated circuit for radio frequency applications | |
| KR101225193B1 (en) | Semiconductor pacakge and method of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160302 Termination date: 20200112 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |