CN103208472A - Composite semi-conductor integrated circuit with three-dimensional element - Google Patents
Composite semi-conductor integrated circuit with three-dimensional element Download PDFInfo
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- CN103208472A CN103208472A CN2012100087222A CN201210008722A CN103208472A CN 103208472 A CN103208472 A CN 103208472A CN 2012100087222 A CN2012100087222 A CN 2012100087222A CN 201210008722 A CN201210008722 A CN 201210008722A CN 103208472 A CN103208472 A CN 103208472A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
Abstract
The invention relates to a composite semi-conductor integrated circuit with a three-dimensional element. In the composite semi-conductor integrated circuit, a welding pad or an inductor is arranged above an electronic element in a three-dimensional mode. The thickness of a dielectric layer inserted between the welding pad or the inductor and the electronic element ranges from 10 microns to 30 microns, so that influence on the performance of the element caused by the structure is effectively reduced. A protective layer can be coated on the electronic element to prevent pollution from metal materials making the welding pad or the inductor, and therefore, relatively cheap copper can be used for making the welding pad and the inductor. The three-dimensional welding pad can be applied to a wire bonding technology or a lug bonding technology.
Description
Technical field
The present invention is relevant a kind of compound semiconductor integrated circuit with three-D elements, refers to especially a kind ofly in electronic component top three-dimensional weld pad or inductance are set, and in the compound semiconductor integrated circuit that inserts a dielectric layer between the two.
Background technology
Along with the development of Mobile Communications industries, to high integration, high-effect, (monolithic microwave integrated circuits, demand MMIC) also increases the simple monocrystalline microwave integrated circuit of fabrication schedule day by day.Traditionally, the assembly of monocrystalline microwave integrated circuit such as transistor, electric capacity, resistance, inductance, signal I/o pad and between binding be that mode with two dimension arranges, yet weld pad need occupy the very big area of plane usually, makes the integration of chip can't promote and increase the size of chip.For saving the shared area of plane of weld pad, so developed a kind of monocrystalline microwave integrated circuit of three-dimensional, in this kind circuit, normally weld pad is moved to electronic component above, and between weld pad and electronic component, insert a dielectric layer as electrical isolation, on this dielectric layer, can make guide hole (via hole) as the pipeline of the electrode binding of weld pad and electronic component.Thus, the element in the monocrystalline microwave integrated circuit transfers to utilizing vertical space to replace the three dimensional constitution setting of plane space, therefore can help the reduction of chip size.
Yet, so the monocrystalline microwave integrated circuit element with the three dimensional constitution setting may make the metal level induction in metal pad and the electronic component produce electric capacity, in the monocrystalline microwave integrated circuit, this inductance capacitance may be coupled with radio-frequency (RF) signal, and therefore reduces the usefulness of electronic component and the reliability of integrated circuit.
Except weld pad, inductance also is extremely space consuming element in the monocrystalline microwave integrated circuit.For saving the shared area of plane of inductance, also the inductance three dimensional constitution can be arranged at the electronic component top, and in wherein inserting a dielectric layer.Yet, the inductance capacitance that places electronic component top to cause inductance is coupled with radio-frequency (RF) signal and also can significantly reduces the usefulness of electronic component, particularly can cause the reduction of Q value, therefore one with the integrated circuit of three dimensional constitution setting with element in, reducing the coupling of inductance capacitance and other radio-frequency (RF) signal is an important topic to the influence of electronic component usefulness.
Traditionally, in the monocrystalline microwave integrated circuit of GaAs series, gold is to link the most general material for weld pad and interelement.Recently, because it is than low resistance and lower cost, copper becomes preferred material.Yet using copper is that copper atom diffuses in the dielectric layer easily as the shortcoming of the metal material of weld pad, even the active area that diffuses to electronic component causes component wear.Especially in some compound semiconductor, as GaAs series, copper system runs after fame with the carrier killer; In case copper atom enters compound semiconductor when zone of electronic component, namely can diffuse to semi-conductive in and significantly change its characteristic electron.Therefore, for utilizing the advantage of copper pad, must in this three-D elements, design a reliable protective layer, reduce or even the problem of component wear with the element efficiency of avoiding being caused because of copper atom diffusion.
Summary of the invention
Main purpose of the present invention is to provide a kind of compound semiconductor integrated circuit with three-D elements, wherein be that a weld pad is placed the electronic component top, and in inserting a dielectric layer between the two so that isolation enough between electronic component and its top weld pad to be provided, thus, when dwindling chip size, also can reduce the influence that coupling capacitance causes electronic component usefulness.
For reaching above-mentioned purpose, the invention provides a kind of compound semiconductor integrated circuit, it comprises at least one electronic component, one first dielectric layer and a weld pad in regular turn, and wherein this first dielectric layer is between this weld pad and this electronic component, and its thickness is between 10 to 30 microns.
Another object of the present invention is to provide a kind of compound semiconductor integrated circuit with three-D elements, wherein be that an inductance is placed the electronic component top, and in inserting one first dielectric layer between the two so that isolation enough between electronic component and its top weld pad to be provided, to reduce the attenuation degree of Q value.
For reaching above-mentioned purpose, the present invention provides a kind of compound semiconductor integrated circuit, comprises at least one electronic component, one first dielectric layer and an inductance in regular turn, and wherein this first dielectric layer is between this inductance and electronic component.
Another purpose of the present invention is to provide a kind of compound semiconductor integrated circuit with three-D elements; wherein be that weld pad or inductance are placed the electronic component top; and weld pad and inductance are made of copper; between weld pad or inductance and electronic component, insert a dielectric layer; and further comprise a protective layer be covered in electronic component on, to avoid the diffuse pollution from the copper in the upper element.
When implementing, this first dielectric layer is can be by dielectric material polyphenyl oxazole (Polybenzoxazole, PBO) formation.
When implementing, this electronic component can be piling up of a High Electron Mobility Transistor, a heterojunction bipolar transistor, a film resistor, a diode, a metal-insulating layer-metal capacitor or a metal-insulating layer-metal capacitor.
When implementing, the material that constitutes this weld pad can be copper.
When implementing, the material that constitutes this protective layer can be silicon nitride (SiN).
When implementing, can on this weld pad, further form a metal column, with for the bump bond technology, and the material that constitutes this metal column can be copper.
When implementing, the material that constitutes this inductance is to can be copper.
For for characteristics of the present invention and interaction energy more deep understanding being arranged, existing cooperate graphic being specified in by embodiment after.
Description of drawings
Fig. 1 is the cross-sectional view with compound semiconductor integrated circuit of three-dimensional weld pad of the present invention.
Fig. 2 is the cross-sectional view of another structure of the combined type semiconductor integrated circuit with three-dimensional weld pad and metal column of the present invention.
Fig. 3 A, 3B and 3C are plan structure and the cross-sectional view with combined type semiconductor integrated circuit of three-dimensional inductance of the present invention.
Fig. 4 is the isolation that a weld pad the placed High Electron Mobility Transistor when top analog result figure to input power.
Fig. 5 for the isolation degree of decay that a weld pad placed High Electron Mobility Transistor when top to inserting the analog result figure of medium thickness.
Fig. 6 inserts analog result comparison diagram under the situation of no any element below the simulation Q value of medium thickness and the inductance for an inductance being placed the piling up an of metal-insulating layer-metal capacitor (MIM), a metal-insulating layer-metal capacitor, a heterojunction bipolar transistor power amplifier (HBT power cell) or a film resistor (TFR) top to difference.
Fig. 7 A and 7B for three radio frequency pads of a SPDT switch are placed the preceding of High Electron Mobility Transistor top and after overlook the wiring schematic diagram.
Description of reference numerals: 11-electronic component; The 12-weld pad; 13-first dielectric layer; The 14-metal level; The 15-protective layer; 16-seed metal layer; The 21-metal column; 22-second dielectric layer; The 31-inductance; 312-inductance contact area one; 313-inductance contact area two; The 32-metal-insulating layer-metal capacitor; 321-metal-insulating layer-metal capacitor the first metal layer; 322-metal-insulating layer-metal capacitor second metal level; 33-first dielectric layer; The 30-substrate; 351-links metal level; 352-links metal level; 361-first silicon nitride layer; 362-second silicon nitride layer; The 363-silicon nitride layer.
Embodiment
Fig. 1 is the cross-sectional view of combined type semiconductor integrated circuit of the present invention, its comprise that at least one electronic component 11, a weld pad 12 are positioned at electronic component 11 tops and in one first dielectric layer 13 that inserts between the two as electrical isolation.This electronic component 11 is to be formed on the compound semiconductor substrate, is preferable with half insulation GaAs substrate wherein.This electronic component 11 can be piling up of a High Electron Mobility Transistor (HEMT), a heterojunction bipolar transistor (HBT), a film resistor (TFR), a diode, a metal-insulating layer-metal capacitor (MIM) or a metal-insulating layer-metal capacitor.
Thickness between first dielectric layer 13 between this electronic component 11 and this weld pad 12 is between 10 to 30 microns.Be enough to effectively to reduce the coupling capacitance of 12 of this electronic component 11 and this weld pads at the thickness of this scope, therefore can reduce the influence that coupling capacitance causes electronic component usefulness.
For carrying out qualitative estimation, examination is considered as a parallel plate capacitor, its capacitance C with the conductive layer of weld pad 12, first dielectric layer 13 and below electronic component 11 thereof
PadBe to be determined by following equation:
C
Pad=ε S/d, equation (1)
Wherein S is the area area of weld pad (or under the extreme case) of parallel plate capacitor, and d is the thickness of first dielectric layer 13, and ε is the dielectric constant of dielectric medium.Suppose that pad area is common pad area, size is about 80 * 80 square microns, dielectric constant be common dielectric medium (as benzocyclobutene (Benzocyclobutene, BCB) and polyphenyl oxazole (Polybenzoxazole, PBO)) DIELECTRIC CONSTANT=3.0, the capacitance C that calculates
PadListed to different dielectric layer thickness d such as table one
| D (micron) | C pad(fF) |
| 3 | 56.7 |
| 5 | 34.0 |
| 7 | 24.3 |
| 10 | 17.0 |
| 15 | 11.3 |
| 20 | 8.5 |
| 25 | 6.8 |
| 30 | 5.7 |
Table one
Be example with the inductance capacitance in the single-pole double-throw switch (SPDT) (SPDT switch), Fig. 7 A and 7B be prior art and single-pole double-throw switch (SPDT) of the present invention overlook the wiring schematic diagram.The element on a figure left side by two be linked in sequence, grid width formed by 2.625 millimeters bigrid High Electron Mobility Transistor (dual-gate HEMTs), the element of scheming the right side by two be linked in sequence, grid width formed by 3.375 millimeters three grid High Electron Mobility Transistor (triple-gate HEMTs).In a traditional circuit, radio frequency pad 71 is to be arranged at the High Electron Mobility Transistor periphery, shown in Fig. 7 A.And in the circuit with three-D elements of the present invention, these three radio frequency pads 71 are the tops that are arranged at High Electron Mobility Transistor, shown in Fig. 7 B.The on the left side element is made as unlatching, right elements is made as and carries out breadboardin under the situation of closing, and the voltage that control circuit opens and cuts out is respectively 0.5 volt and-3 volts, and basic signal frequency is made as that to carry out radio-frequency performance under 0.9 hertz the condition be simulation.Consider worst condition, that is the simulation when weld pad electric capacity is between the source electrode of High Electron Mobility Transistor and drain electrode, its result shows the weld pad capacitor C
PadTo the insertion of radio frequency usefulness loss and non-linear great influence arranged.Yet, (weld pad capacitor C when medium thickness is 3 microns
Pad=56.7fF), the isolation of SPDT switch is compared with the non-existent situation of weld pad electric capacity has reduced by 1.7 decibels down.Simulation result as shown in Figure 4, wherein lines A is 3 microns of medium thicknesses and the top result when having weld pad, the comparison of the result when not having weld pad with the top (lines B).This simulation shows that further the degree of decay of SPDT switch isolation is along with the medium thickness monotone decreasing, as shown in Figure 5.When medium thickness is during greater than 10 microns, this decay is reduced to less than 0.6 decibel, and when medium thickness be during greater than 20 microns, this decay even reduce to less than 0.3 decibel.
This first dielectric layer 13 can be a spin-coating dielectric medium, is formed on the electronic component 11 via tradition rotation coating method and program curing.For the medium thickness that makes coating can reach 10～30 microns, (polybenzoxazole is preferable PBO) to dielectric layer material with the polyphenyl oxazole.Be lower than below the 1500rpm at the rotation rotating speed, the thickness after this material cured still can reach more than 10 microns.In addition, the PBO dielectric medium is the photosensitive material that can make various three-dimensional structure eurymeric photoresist layer at electronic component.For example groove (trench) or guide hole (viahole) structure can form with the standard light etch process in the element top, as standard step such as exposure, development, curing.
This weld pad 12 can be electrically connected at a near metal level 14 that is positioned at the electronic component 11 by the guide hole that is arranged in first dielectric layer 13, and this metal level 14 can be further be connected with arbitrary electrode of electronic component 11 or with near other is positioned at electronic component.
Gold is the material that generally is usually used in integrated circuit, but copper is better selection cheaply.Yet copper diffuses in other materials easily, causes the pollution of electronic component and substrate.As shown in Figure 1, the present invention can further comprise a protective layer 15 between electronic component 11 and first dielectric layer 13, and this protective layer 15 can be used as the diffusion energy barrier of copper atom, therefore can avoid polluter to enter the diffusion of electronic component.This protective layer 15 is formed at the superiors usually by on the formed metal level 14 of gold, as shown in Figure 1.The material that forms this protective layer 15 is preferable with silicon nitride.According to fabrication schedule of the present invention, the copper weld pad is to form in the backend process of all front-end process after the formation of silicon nitride protective layer is finished, and so can avoid taking place the diffuse pollution of copper in front-end process, to safeguard chip reliability.One metal seed layer 16 can be used for copper-plating technique.The material that constitutes this metal seed layer 16 is preferable with palladium, copper/titanium or copper/titanium tungsten.This metal seed layer 16 also can be used as the diffusion energy barrier of copper atom.
Fig. 2 is the cross-sectional view of another embodiment of the present invention, wherein further comprises a metal column 21 on weld pad 12, and provides one second dielectric layer 22 to be covered in the usefulness of conduct surface isolation on this weld pad 12.The material that forms this metal column 21 is preferable with copper.These second dielectric layer, 22 materials are preferable with polyphenyl oxazole (PBO) dielectric material.Embodiment with metal column structure can be used for the bump bond technology in the crystal covering type encapsulation technology.
Except three-dimensional weld pad, inductance can also be arranged on the electronic component by three dimensional constitution, and inserts a dielectric layer between the two.Wherein, this electronic component can be piling up of a High Electron Mobility Transistor (HEMT), a heterojunction bipolar transistor (HBT), a heterojunction bipolar transistor power amplifier (HBT powercell), a film resistor (TFR), a diode, a metal-insulating layer-metal capacitor (MIM) or a metal-insulating layer-metal capacitor.
Fig. 3 A is the schematic top plan view that one on the GaAs substrate 30 has the compound semiconductor integrated circuit of three-D elements that is positioned at of another embodiment of the present invention, comprises an inductance 31, is the top that is positioned at a metal-insulating layer-metal capacitor 32.Fig. 3 B is the cross-sectional view of AA ' line in Fig. 3 A.Inductance 31 is to be formed on one first dielectric layer 33; One second dielectric layer 34 is covered in the usefulness of conduct surface isolation on this inductance 31; Inductance 31 further comprises two contact areas 312 and 313 in its two ends; Contact area 312 and 313 by guide hole further be positioned at first dielectric layer 33 under binding metal level 351 and 352 contact.In the application-specific example, this binding metal level 351 and 352 can further link (not being shown in Fig. 3) with other electronic components.The cross-sectional view of Fig. 3 C in Fig. 3 A, passing the BB ' line of this metal-insulating layer-metal capacitor 32.This metal-insulating layer-metal capacitor 32 is the belows that are formed at this inductance 31 and this first dielectric layer 33.This metal-insulating layer-metal capacitor 32 comprises a first metal layer 321 and one second metal level 322 usually.For electrical isolation is provided, one first silicon nitride layer 361 is to be formed on this GaAs substrate 30; This first metal layer 321 is to be formed at going up and being covered by one second silicon nitride layer 362 of this first silicon nitride layer 361; This second metal level 322 is to be formed at going up at last and by a silicon nitride layer 363 of this second silicon nitride layer 362 to be covered.
This first dielectric layer 33 and this second dielectric layer 34 can be a spin-coating dielectric medium, and it is to form via tradition rotation coating method and program curing.This spin-coating dielectric medium is preferable with polyphenyl oxazole (PBO), and under the situation of careful control rotation rotating speed, the thickness after this material cured can reach more than 10 microns.
Inductance and below the thickness of first dielectric layer 33 between the electronic component can influence the Q value of this integrated circuit.Fig. 6 when an inductance being placed the piling up an of metal-insulating layer-metal capacitor, a metal-insulating layer-metal capacitor, a heterojunction bipolar transistor power amplifier or film resistor top Q value and inductance below the comparison of analog result under the situation of no any element.As can be seen from Figure when PBO medium thickness increase and decrease hour, the Q value also with decay.When the PBO medium thickness more than 10 microns, the fade of Q value is in a tolerable scope.Therefore, in a three-dimensional monocrystalline microwave integrated circuit, the dielectric medium optimum thickness between inductance and electronic component is an important consideration.
In sum, compound semiconductor integrated circuit with three-D elements provided by the invention can reach its intended purposes really, the function of the dielectric layer in the integrated circuit of the present invention improves really, make when dwindling chip size, also can reduce the influence that three-dimensional weld pad and induction structure cause electronic component usefulness.The value that its true tool industry is utilized proposes patent application in accordance with the law.
Again above-mentioned explanation and graphic only be in order to embodiments of the invention to be described, allly ripely still can do localized variation and the modification of equivalence in the personage of this industry skill, it does not break away from technology of the present invention and spirit.
Claims (30)
1. the compound semiconductor integrated circuit with three-D elements is characterized in that, comprising:
One electronic component;
One weld pad is to be positioned at this electronic component top;
One first dielectric layer is between this weld pad and this electronic component, and its thickness is between 10 to 30 microns;
One guide hole is to be formed at this first dielectric layer with the usefulness as electric connection; And
One metal level is the bottom that is formed at this guide hole.
2. the compound semiconductor integrated circuit with three-D elements according to claim 1 is characterized in that, the dielectric material that constitutes this first dielectric layer is the polyphenyl oxazole.
3. the compound semiconductor integrated circuit with three-D elements according to claim 1 is characterized in that this electronic component further comprises at least one electrode.
4. the compound semiconductor integrated circuit with three-D elements according to claim 3 is characterized in that, the electrode of this electronic component further comprises a contact area that is connected with other elements.
5. the compound semiconductor integrated circuit with three-D elements according to claim 3, it is characterized in that this electronic component with at least one electrode is piling up of a High Electron Mobility Transistor, a heterojunction bipolar transistor, a film resistor, a diode, a metal-insulating layer-metal capacitor or a metal-insulating layer-metal capacitor.
6. the compound semiconductor integrated circuit with three-D elements according to claim 1 is characterized in that, the material that constitutes this weld pad is copper.
7. the compound semiconductor integrated circuit with three-D elements according to claim 6 is characterized in that, further comprises a protective layer between this first dielectric layer and this electronic component.
8. the compound semiconductor integrated circuit with three-D elements according to claim 7 is characterized in that, at least part of this metal level that is covered in of this protective layer.
9. according to claim 7 or 8 described compound semiconductor integrated circuits with three-D elements, it is characterized in that the material that constitutes this protective layer is silicon nitride.
10. the compound semiconductor integrated circuit with three-D elements according to claim 6 is characterized in that, further comprises a metal seed layer between this first dielectric layer and this weld pad.
11. the compound semiconductor integrated circuit with three-D elements according to claim 10 is characterized in that, the material that constitutes this metal seed layer is palladium, copper/titanium or copper/titanium tungsten.
12. the compound semiconductor integrated circuit with three-D elements according to claim 1 is characterized in that, further comprises a metal column on this weld pad, is used for the bump bond technology.
13. the compound semiconductor integrated circuit with three-D elements according to claim 12 is characterized in that, further covers one second dielectric layer on this weld pad, for the protection of its understructure.
14. the compound semiconductor integrated circuit with three-D elements according to claim 13 is characterized in that the dielectric material that constitutes this second dielectric layer is the polyphenyl oxazole.
15. the compound semiconductor integrated circuit with three-D elements according to claim 12 is characterized in that the material that constitutes this metal column is copper.
16. the compound semiconductor integrated circuit with three-D elements is characterized in that, comprising:
One electronic component;
One inductance is to be positioned at this electronic component top;
One first dielectric layer is between this inductance and this electronic component;
One guide hole is to be formed at this first dielectric layer with the usefulness as electric connection; And
One metal level is the bottom that is formed at this guide hole.
17. the compound semiconductor integrated circuit with three-D elements according to claim 16 is characterized in that, the thickness of this first dielectric layer is between 10 to 30 microns.
18. the compound semiconductor integrated circuit with three-D elements according to claim 16 is characterized in that the dielectric material that constitutes this first dielectric layer is the polyphenyl oxazole.
19. the compound semiconductor integrated circuit with three-D elements according to claim 16 is characterized in that this electronic component further comprises at least one electrode.
20. the compound semiconductor integrated circuit with three-D elements according to claim 19 is characterized in that, the electrode of this electronic component further comprises a contact area that is connected with other elements.
21. the compound semiconductor integrated circuit with three-D elements according to claim 19, it is characterized in that this electronic component with at least one electrode is piling up of a High Electron Mobility Transistor, a heterojunction bipolar transistor, a film resistor, a diode, a metal-insulating layer-metal capacitor or a metal-insulating layer-metal capacitor.
22. the compound semiconductor integrated circuit with three-D elements according to claim 16 is characterized in that the material that constitutes this inductance is copper.
23. the compound semiconductor integrated circuit with three-D elements according to claim 22 is characterized in that, further comprises a protective layer between this first dielectric layer and this electronic component.
24. the compound semiconductor integrated circuit with three-D elements according to claim 23 is characterized in that, at least part of this metal level that is covered in of this protective layer.
25. according to claim 23 or 24 described compound semiconductor integrated circuits with three-D elements, it is characterized in that the material that constitutes this protective layer is silicon nitride.
26. the compound semiconductor integrated circuit with three-D elements according to claim 16 is characterized in that, further comprises a metal seed layer between this first dielectric layer and this inductance.
27. the compound semiconductor integrated circuit with three-D elements according to claim 26 is characterized in that, the material that constitutes this metal seed layer is palladium, copper/titanium or copper/titanium tungsten.
28. the compound semiconductor integrated circuit with three-D elements according to claim 16 is characterized in that, this inductance be shaped as spirality.
29. the compound semiconductor integrated circuit with three-D elements according to claim 16 is characterized in that, further covers one second dielectric layer on this inductance, for the protection of its understructure.
30. the compound semiconductor integrated circuit with three-D elements according to claim 29 is characterized in that the dielectric material that constitutes this second dielectric layer is the polyphenyl oxazole.
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| CN109075036A (en) * | 2016-03-31 | 2018-12-21 | 索泰克公司 | It is used to form the manufacturing method of the structure of three dimensional monolithic integrated circuit |
| CN111081675A (en) * | 2018-10-18 | 2020-04-28 | 力智电子股份有限公司 | Integrated circuit device with insulation capacitor and manufacturing method thereof |
| US11728292B2 (en) | 2015-05-05 | 2023-08-15 | Mediatek Inc. | Semiconductor package assembly having a conductive electromagnetic shield layer |
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| US20080308934A1 (en) * | 2007-04-23 | 2008-12-18 | Flipchip International, Llc | Solder bump interconnect for improved mechanical and thermo-mechanical performance |
| US20100224588A1 (en) * | 2005-08-10 | 2010-09-09 | Jong-Chae Kim | Methods of forming metal-insulator-metal (mim) capacitors with passivation layers on dielectric layers |
| US7939948B2 (en) * | 2005-01-10 | 2011-05-10 | Micron Technology, Inc. | Interconnect structures with bond-pads and methods of forming bump sites on bond-pads |
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| TW559874B (en) * | 2001-09-28 | 2003-11-01 | Kobe Steel Ltd | Method of forming aerial metal wiring on semiconductor substrate |
| US20030127734A1 (en) * | 2002-01-07 | 2003-07-10 | Jin-Yuan Lee | Cylindrical bonding structure and method of manufacture |
| US7939948B2 (en) * | 2005-01-10 | 2011-05-10 | Micron Technology, Inc. | Interconnect structures with bond-pads and methods of forming bump sites on bond-pads |
| US20100224588A1 (en) * | 2005-08-10 | 2010-09-09 | Jong-Chae Kim | Methods of forming metal-insulator-metal (mim) capacitors with passivation layers on dielectric layers |
| US20080308934A1 (en) * | 2007-04-23 | 2008-12-18 | Flipchip International, Llc | Solder bump interconnect for improved mechanical and thermo-mechanical performance |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US11728292B2 (en) | 2015-05-05 | 2023-08-15 | Mediatek Inc. | Semiconductor package assembly having a conductive electromagnetic shield layer |
| CN109075036A (en) * | 2016-03-31 | 2018-12-21 | 索泰克公司 | It is used to form the manufacturing method of the structure of three dimensional monolithic integrated circuit |
| CN109075036B (en) * | 2016-03-31 | 2023-07-28 | 索泰克公司 | Method for manufacturing structure for forming three-dimensional monolithic integrated circuit |
| CN111081675A (en) * | 2018-10-18 | 2020-04-28 | 力智电子股份有限公司 | Integrated circuit device with insulation capacitor and manufacturing method thereof |
| CN111081675B (en) * | 2018-10-18 | 2024-04-12 | 源芯半导体股份有限公司 | Integrated circuit device with insulating capacitor and method of manufacturing the same |
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| CN103208472B (en) | 2016-03-02 |
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