CN105826304A - Chip Package - Google Patents

Chip Package Download PDF

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Publication number
CN105826304A
CN105826304A CN201610019446.8A CN201610019446A CN105826304A CN 105826304 A CN105826304 A CN 105826304A CN 201610019446 A CN201610019446 A CN 201610019446A CN 105826304 A CN105826304 A CN 105826304A
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CN
China
Prior art keywords
chip
bare chip
bare
package
active surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610019446.8A
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Chinese (zh)
Inventor
张伯豪
张峻玮
李锦智
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MediaTek Inc
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MediaTek Inc
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Publication date
Application filed by MediaTek Inc filed Critical MediaTek Inc
Publication of CN105826304A publication Critical patent/CN105826304A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract

A chip package includes a first die encapsulated by a molding compound; a board comprising a chip mounting surface; a redistributed layer (RDL) structure on an active surface of the first die and between the die and the chip mounting surface; and a discrete passive device embedded in the molding compound and situated in close proximity to a side edge of the first die. According to the invention, the discrete passive device is embedded into chip package, when an IR drop close to the die happens, the discrete passive device is capable of rapidly compensating the unexpected IR drop, and the die is prevented against influences.

Description

Chip package
Technical field
The present invention relates to a kind of chip package, more specifically it relates to the integrated circuit of a kind of improvement (IntegratedCircuit, IC) chip package, this chip package has Embedded discrete device, it is possible to reduce the resistance drop (IRdrop) on chip.
Background technology
IC-components generally includes the IC chip (chip) or bare chip (die) being accommodated in (ishousedin) encapsulation.Described IC chip generally includes the known manufacturing technology of utilization on the thin wafer (wafer) of quasiconductor, the circuit being made up of photoengraving pattern (lithographicallypatterning) conduction and insulant.This encapsulation support also protects described IC chip, and provide the electrical connection between described circuit and the external circuit board.For example, encapsulated type known to some is used for accommodating IC chip, such as BGA (ballgridarray, BGA), pin grid array (pingridarrays, PGA), plastic packaging leaded chip carrier (plasticleadedchipcarrier, PLCC), plastic packaging flat package (plasticquadflatpack) and other.
BGA (BGA) encapsulation is a well known in the art technology.By using the conducting sphere (projection (bump)) arranged on the BGA package back side in array, rather than use lead frame, BGA package is bound to installing plate (mountingboard), and wherein, conducting sphere (projection) is as outside terminal.Owing to the whole back side of semiconductor packages may be used for being connected to this plate (board), therefore, it can dramatically increase the quantity of input/output weld pad.In order to support higher function, pin number dramatically increases.
One of which type in IC chip package is " flip-chip " (flipchip), and " flip-chip " of this type need not any bonding wire (wirebond).After wafer is cut into each chip unit (dice), " flip-chip " is arranged on base plate for packaging with being squeezed, and this base plate for packaging includes contact point and the connection matching associated external circuit.Solder backflow is with the contact (contact) of joint chip and substrate.Then, flip-chip would generally experience filling process (underfillprocess) and cover the encapsulation process of bare chip side.
Along with complexity and the speed of operation of system increase, the power consumption (powerconsumption) of integrated circuit dramatically increases.Additionally, along with super large-scale integration (VeryLargeScaleIntegration, VLSI) technology inevitably extends, IC service voltage continuous decrease.Reducing nominal service voltage can cause element to be more susceptible to the impact of power supply noise along with reducing device noise edge.Owing to frequency intrinsic in power distribution system of today relies on distributed parasitic, this noise includes exchanging dynamically (AlternatingCurrent, AC) voltage pulsation and direct current (DirectCurrent, DC) resistance drop (i.e. IR fall).
In microelectronics system, the IR fall of system can be three parts by budget: on chip, encapsulates and plate.Due to the fine-feature size of electrical network (on-diepowergrid) on chip, the resistance loss on chip is serious, and therefore, the IR fall on chip is widely studied.Generally, in order to reduce the IR fall on chip, in the metal of integrated circuit bare chip interconnects, metal-insulator-metal type (metal-insulator-metal, MIM) electric capacity is formed.But, in order to maintain enough electric capacity, on chip, the size of MIM capacitor will not reduce (shrink) along with the reduction of IC size.Therefore, the ratio of the chip area occupied by capacitor on chip is gradually increased, thus is converted into cost and increases.
Summary of the invention
In view of this, an object of the present invention is to provide the chip package of a kind of improvement, this chip package to have Embedded discrete device, it is possible to reduce the IR fall on chip.
According to an aspect of the present invention, chip package includes: the first bare chip being encapsulated in moulding compound；The rewiring Rotating fields being positioned on the active surface of the first bare chip；And the discrete device being embedded in moulding compound, in the position of the lateral edges that this discrete device is positioned close to this first bare chip.According to an embodiment, this chip package can also include a plate containing chip installed surface, and this rewiring Rotating fields is between the chip installed surface of this first bare chip and this plate.In certain embodiments, this discrete device is discrete passive component, discrete active device or a combination thereof, to reduce the IR fall on chip.
According to an embodiment, this chip package also includes the second bare chip.This first bare chip and this second bare chip are arranged side by side, and are all encapsulated in this moulding compound.This rewiring Rotating fields is also disposed on the active surface of this second bare chip.According to an embodiment, the edge-to-edge distance between this first bare chip and this second bare chip is equal to or more than 1000 microns.
According to an embodiment, this discrete device has a surface, and this surface of this discrete device substantially flushes with this active surface of this first bare chip, and this rewiring Rotating fields is also set directly on this surface of this discrete device.
According to a further aspect in the invention, chip package includes: the first bare chip being encapsulated in moulding compound；The rewiring Rotating fields being positioned on the active surface of this first bare chip；And it is embedded in the discrete device in this rewiring Rotating fields.According to an embodiment, this chip package can also include a plate containing chip installed surface, and this rewiring Rotating fields is between the chip installed surface of this first bare chip and this plate.In certain embodiments, this discrete device is discrete passive component, discrete active device or a combination thereof, to reduce the IR fall on chip.
In accordance with a further aspect of the present invention, chip package includes: semiconductor bare chip；The rewiring Rotating fields being positioned on the active surface of this semiconductor bare chip；And it is embedded in the discrete device in this rewiring Rotating fields.According to an embodiment, this chip package can also include a plate containing chip installed surface, and this rewiring Rotating fields is between the chip installed surface of this first bare chip and this plate.In certain embodiments, this discrete device is discrete passive component, discrete active device or a combination thereof, to reduce the IR fall on chip.
In said chip encapsulates, by embedding a discrete device in chip package, thus, when the IR fall near bare chip occurs, this discrete device can compensate unexpected IR fall rapidly, it is to avoid bare chip is affected.
Accompanying drawing explanation
The accompanying drawing being included in order to provide a further understanding of the present invention, and, be merged in and constitute the part of this specification.Accompanying drawing is used for embodiments of the invention are described together with the description, contributes to explaining the principle of the present invention.In the accompanying drawings:
Fig. 1 shows the cross sectional representation of a kind of chip package according to the present invention one exemplary embodiment；
Fig. 2 is the cross sectional representation according to a kind of chip package shown in another exemplary embodiment of the present invention；
Fig. 3 is the cross sectional representation according to a kind of chip package shown in further example embodiment of the present invention；
Fig. 4 is the cross sectional representation encapsulated according to a kind of FC-BGA shown in the another exemplary embodiment of the present invention.
Detailed description of the invention
It is depicted below as the preferred embodiment that the present invention implements.Following example are only used for enumerating the technical characteristic of the explaination present invention, are not used for limiting scope of the invention.Some vocabulary is employed in the middle of specification and claims to censure specific element in the whole text.One of ordinary skill in the art are it is to be appreciated that same element may be called with different nouns by manufacturer.In the way of this specification and claims book not difference by title is used as distinct elements, but it is used as the benchmark of difference with element difference functionally.The term " element ", " system " that use in the present invention can be the entities relevant to computer with " device ", and wherein, this computer can be the combination of hardware, software or hardware and software.Be described below with claims in the middle of mentioned term " comprise " and " including " is open language, therefore the meaning of " including, but are not limited to ... " should be construed to.Mean directly or indirectly to be electrically connected additionally, term " couples ".Therefore, if a device is coupled to another device described in literary composition, then represents this device and can directly be electrically connected in this another device, or be indirectly electrically connected to this another device through other device or connection means.
The embodiment of the present invention described in detail below in, with reference to accompanying drawing and illustrate, wherein, accompanying drawing constitute the embodiment of the present invention a part, and, show, by diagramatic way, the certain preferred embodiment that the present invention can implement.
These embodiments have obtained fully describing in detail, so that those skilled in the art can implement them, it should be apparent that, machinery, chemistry, change electrically and in program can be made in without departing from the spirit and scope of the present invention, thus other embodiments can be utilized.Therefore, the following detailed description is not used for limiting the present invention, and, the scope of the embodiment of the present invention is limited only by the appended claims.
The present invention is about the chip package of a kind of improvement, this chip package has at least one Embedded discrete device, this discrete device can be discrete passive (passive) device, discrete active (active) device, or a combination thereof, to reduce the IR fall on chip, additionally, also have less chip size and relatively low cost.In some instances, discrete passive component can be the devices such as electric capacity (such as decoupling capacitance), resistance, discrete active device can be power management integrated circuit (powermanagementintegratedcircuit, the device such as PMIC), it should be noted that, the type of discrete device is not done any restriction by the present invention.For convenience of describing, subsequent descriptions illustrates as a example by discrete passive component, especially, illustrates as a example by discrete decoupling capacitance.But it should explanation is, the present invention is not limited to this and illustrates, in implementing, every can be used to changes impedance to reduce the discrete device (including discrete active device and/or discrete passive component) of the IR fall on chip or the discrete active device of stabilized power source can be provided to may be used as the discrete device in chip package of the present invention.In certain embodiments, the position of the IC bare chip during discrete passive component is positioned close to this chip package.This embedded, thin (thin) passive device can reduce the IR fall on chip.
In in one aspect of the invention, this is embedded, discrete device can be used to replace MIM capacitor on expensive chip.Compared with MIM capacitor on traditional large area, chip, this is embedded, discrete device still is able to the electric capacity realizing sufficiently large size (magnitude) purpose for decoupling, and has the cost of reduction.
By embedded, discrete device being embedded in chip package, when the IR fall near chip or bare chip occurs, discrete device can compensate unexpected IR fall rapidly, therefore prevent this chip or bare chip impacted.Additionally, this is embedded, discrete device can also make this chip away from unwanted power noise.
According to one example embodiment of the present invention, chip package can be diffused wafer-level packaging (fan-outwafer-levelpackage, FO-WLP), but is not limited to this.FO-WLP encapsulates (flip-chipballgridarray (FC-BGA) package) relative to existing flip chip ball grid array and has more outstanding form factor (formfactor), number of pins and hot property.Additionally, the high Q inductance of FO-WLP can strengthen electric property, and reduce the power consumption (powerconsumption) in the application of RF circuit.
Further, FO-WLP provides one to have the thin encapsulation of greater compactness of re-wiring layer (redistributedlayer, RDL) pin.In FO-WLP, copper-connection (copperinterconnect), also referred to as interconnect (postpassivationinterconnection) after passivation, be formed on the sheet exposed on pad (on-chippads).
Should be noted that, in one example embodiment of the present invention, discrete device (such as discrete passive component) can be decoupling capacitance (decouplingcapacitor), this decoupling capacitance is implemented for the decoupling function of sufficiently large size MIM capacitor, and can quickly compensate unexpected IR fall.But, in other exemplary embodiments, discrete passive component could be for the different resistance of purpose, inductance, radio frequency (radiofrequency, RF) wave filter, diode or a combination thereof etc., and this is not done any restriction by the embodiment of the present invention.
Fig. 1 shows cross section (cross-sectional) schematic diagram of a kind of chip package according to the present invention one exemplary embodiment.As shown in Figure 1, chip package 1 can include multiple IC chip or bare chip 11 and 12 (for convenience of description, in this example as a example by two bare chips), these multiple IC chips or bare chip are molded (aremolded) in an encapsulation 2, for example, encapsulation 2 can be wafer-level packaging (WaferLevelPackage, WLP) encapsulation.It should be noted that, chip package 1 can also only include single IC chip or bare chip, thus based on the example shown in Fig. 1, can correspondingly obtain the chip package 1 including single IC chip or bare chip, for brevity, it is repeated no more by the present invention.Additionally, for convenience of describing, the encapsulation 2 in following example illustrates as a example by WLP encapsulates, but the present invention is not limited to this.
According to this exemplary embodiment, two bare chips 11 and 12 are arranged side by side (arrangedside-by-side) and are encapsulated in moulding compound (moldingcompound) 20.Active surface (activesurface) 11a of the bare chip 11 and active surface 12a of bare chip 12 is reversed (flipped) and the chip installed surface 40a towards plate (board) 40 (such as base plate for packaging or printed circuit board (PCB) etc.) assembles.
Can come out from end face (topsurface) 2a of WLP encapsulation 2 according to this exemplary embodiment, bottom surface (bottomsurface) 11b of bare chip 11 and the bottom surface 12b of bare chip 12.
According to this exemplary embodiment, multiple thin spaces (fine-pitch) junction point 110 (such as conductive welding disk or dimpling block) can be distributed on the active surface 11a of bare chip 11, and, multiple thin space junction points 120 (such as conductive welding disk or dimpling block) can be distributed on the active surface 12a of bare chip 12.
According to this exemplary embodiment, WLP encapsulation 2 can also include rewiring Rotating fields (redistributedlayer (RDL) structure) 30, and this RDL structure 30 is between the chip installed surface 40a of bare chip 11/12 and plate 40.Thin space junction point 110 and thin space junction point 120 are disperseed (or diffusion) for looser solder pad space length (padpitch) by RDL structure 30.
Interconnection structure (interconnectionscheme) 300 can be manufactured in RDL structure 30, above-mentioned multiple thin space junction points 110 and above-mentioned multiple thin space junction point 120 to be re-assigned on the bottom surface 2b of WLP encapsulation 2.Multiple projections 360 are arranged on the bottom surface 2b of WLP encapsulation 2, to electrically connect WLP encapsulation 2 and plate 40.According to this exemplary embodiment, interconnection structure 300 interconnects (copperpost-passivationinterconnection, Cu-PPI) structure after can including copper passivation.
According to this exemplary embodiment, interconnection structure 300 can include interconnecting line (trace) 302, for interconnecting bare chip on the active surface 11a of bare chip 11 bare chip to bare chip (die-to-die) the signaling point 110a active surface 12a with bare chip 12 to bare chip signaling point 120a.RDL structure 30 can also include at least one polymer insulation layer (polymericinsulatinglayer) 310, such as polyimides (polyimide) or epoxy (epoxy), but is not limited to this.
According to this exemplary embodiment, chip package 1 can also include discrete passive component (discretepassivedevice) 130, is inserted between (interposed) bare chip 11 and bare chip 12.In moulding compound 20, together with discrete passive component 130 is molded into above-mentioned two bare chip 11 and 12.If it is understood that chip package 1 includes single bare chip, then on the position of the lateral edges that this bare chip is positioned close to this first bare chip.
According to this exemplary embodiment, in order to accommodate discrete passive component 130, between above-mentioned two bare chip 11 and 12, provide a spacing (gap) with edge-to-edge distance d.For example, distance d can equal to or more than 1000 microns but be not limited to this.Discrete passive component 130 is arranged on the position of the lateral edges (sideedge) very close to (incloseproximityto) above-mentioned two bare chip 11 and 12.
Although described exemplary embodiment illustrate only a passive device 130, but it is to be understood that, in some Variant Design of this exemplary embodiment, multiple discrete passive component can be set continuously in described spacing.
According to this exemplary embodiment, discrete passive component 130 has surface 130a, wherein, surface 130a and the active surface 11a of bare chip 11, the active surface 12a substantially (substantially) of bare chip 12 flush (flush) so that RDL structure 30 can be formed directly on the 130a of surface.For example, if chip package 1 only includes single bare chip (such as bare chip 11), then surface 130a substantially flushes with the active surface 11a of bare chip 11.
According to this exemplary embodiment, discrete passive component 130 has two terminals (terminal) 131 and 132, the power supply point 120b on earth point 110b that the two terminal can be respectively electrically connected on the active surface 11a of bare chip 11 by the interconnecting line 304 and active surface 12a of bare chip 12.
For example, above-mentioned two terminal 131 and 132 can pass through ground pad (groundpad) and the power pad (powerpad) that interconnecting line 304 is respectively electrically connected to be positioned on the active surface 11a of bare chip 11.For example, said two terminal 131 and 132 can be respectively electrically connected to the ground pad on the active surface 12a of bare chip 12 and power pad by interconnecting line 304.
Fig. 2 is the cross sectional representation according to a kind of chip package shown in another exemplary embodiment of the present invention, and wherein, identical number designation represents identical region, layer or element.As shown in Figure 2, chip package 1a can include that multiple IC chip or bare chip 11 and 12 (in this example, as a example by two bare chips), the plurality of IC chip or bare chip are molded into together in encapsulation 3, for example, this encapsulation can be WLP encapsulation.For convenience of describing, the encapsulation 3 in following example illustrates as a example by WLP encapsulates, but the present invention is not limited to this.
According in this exemplary embodiment, said two bare chip 11 and 12 is arranged side by side, and is encapsulated in moulding compound 20.The active surface 11a of bare chip 11 and the active surface 12a of bare chip 12 is reversed and towards plate 40 (such as base plate for packaging or printed circuit board (PCB) etc.) chip installed surface 40a assemble.
Can come out from the end face 3a of WLP encapsulation 3 according to this exemplary embodiment, the bottom surface 11b of bare chip 11 and the bottom surface 12b of bare chip 12.
According to this exemplary embodiment, multiple thin space junction point 110 is (such as conduction i/o pads (input/output, I/O) or dimpling block) can be distributed on the active surface 11a of bare chip 11, and, multiple thin space junction points 120 (such as conductive welding disk or dimpling block) can be distributed on the active surface 12a of bare chip 12.
According to this exemplary embodiment, WLP encapsulation 3 can also include re-wiring layer (RDL) structure 30, and this RDL structure 30 is between the chip installed surface 40a of bare chip 11/12 and plate 40.Thin space junction point 110 is disperseed (or diffusion) to become looser solder pad space length by RDL structure 30 with thin space junction point 120.
Interconnection structure 300 can be manufactured in RDL structure 30, above-mentioned multiple thin space junction points 110 and above-mentioned multiple thin space junction point 120 to be re-assigned on the bottom surface 3b of WLP encapsulation 3.Multiple projections 360 are arranged on the bottom surface 3b of WLP encapsulation 3, to electrically connect WLP encapsulation 3 and plate 40.According to this exemplary embodiment, interconnection structure 300 interconnects (Cu-PPI) structure after can including copper passivation.
According to this exemplary embodiment, interconnection structure 300 can include interconnecting line 302, for interconnecting bare chip on the active surface 11a of bare chip 11 bare chip to the bare chip signaling point 110a active surface 12a with bare chip 12 to bare chip signaling point 120a.RDL structure 30 can also include at least one polymer insulation layer 310, such as polyimides or epoxy, but is not limited to this.
According to this exemplary embodiment, chip package 1a can also include discrete passive component 130, and this discrete passive component 130 embeds (embedded) in RDL structure 30.For example, in the chamber (cavity) of the bottom surface 3b that discrete passive component 130 can be installed in recessed WLP encapsulation 3, but it is not limited to this.
According to this exemplary embodiment, discrete passive component 130 has two terminals 131 and 132, the power supply point 120b on earth point 110b that the two terminal can be respectively electrically connected on the active surface 11a of bare chip 11 by the interconnecting line 304 and active surface 12a of bare chip 12.Said two terminal 131 and 132 can be electrically connected to corresponding ground connection projection 360a and power supply projection 360b by interconnecting line 306.For example, by interconnecting line 304, said two terminal 131 and 132 can be respectively electrically connected to the ground pad on the active surface 11a of bare chip 11 and power pad.For example, by interconnecting line 304, said two terminal 131 and 132 can be respectively electrically connected to the ground pad on the active surface 12a of bare chip 12 and power pad.
Fig. 3 is the cross sectional representation according to a kind of chip package shown in further example embodiment of the present invention, and wherein, identical number designation represents identical region, layer or assembly.As it is shown on figure 3, chip package 1b can include single (single) IC chip or bare chip 14, described single IC chip or bare chip are encapsulated in moulding compound 20, to form encapsulation 4, for example, this encapsulation 4 can be WLP encapsulation.It should be noted that, chip package 1b can also multiple IC chips or bare chip, thus based on the example shown in Fig. 3, can correspondingly obtain the chip package 1b including multiple IC chip or bare chip, for brevity, it is repeated no more by the present invention.Additionally, for convenience of describing, the encapsulation 4 in following example illustrates as a example by WLP encapsulates, but the present invention is not limited to this.
According in this exemplary embodiment, the active surface 14a of bare chip 14 is reversed and assembles towards the chip installed surface 40a of plate 40 (such as base plate for packaging or printed circuit board (PCB) etc.).According to this exemplary embodiment, the bottom surface 14b of bare chip 14 can come out from the end face 4a of WLP encapsulation 4.
According to this exemplary embodiment, multiple thin space junction points 140 (such as conductive welding disk or dimpling block) can be distributed on the active surface 14a of bare chip 14.Re-wiring layer (RDL) structure 30 is arranged between the chip installed surface 40a of bare chip 14 and plate 40.Thin space junction point 140 is disperseed the solder pad space length that (or extension) one-tenth is looser by this RDL structure 30, and described looser pad is positioned on the bottom surface 4b of WLP encapsulation 4.
Similarly, interconnection structure 300 can be manufactured in RDL structure 30, to be re-assigned to by above-mentioned multiple thin space junction points 140 on the bottom surface 4b of WLP encapsulation 4.Multiple projections 360 are arranged on the bottom surface 4b of WLP encapsulation 4, to electrically connect WLP encapsulation 4 and plate 40.RDL structure 30 can also include at least one polymer insulation layer 310, such as polyimides or epoxy, but is not limited to this.According to this exemplary embodiment, interconnection structure 300 can include that copper post-passivation interconnects (Cu-PPI) structure.
According to this exemplary embodiment, chip package 1b can also include discrete passive component 130, embeds (embedded) in RDL structure 30.For example, in the chamber (cavity) of the bottom surface 4b that discrete passive component 130 can be installed in recessed WLP encapsulation 4, but it is not limited to this.
According to this exemplary embodiment, discrete passive component 130 has two terminals 131 and 132, and by the interconnecting line of interconnection structure 300, the two terminal can be respectively electrically connected to the earth point on the active surface 14a of bare chip 14 and power supply point.
Fig. 4 is the cross sectional representation according to a kind of chip package shown in the another exemplary embodiment of the present invention, and wherein, identical number designation represents identical region, layer or assembly.For convenience of description, in embodiments of the present invention, this chip package is illustrated as a example by flip chip ball grid array (FC-BGA) encapsulates.As shown in Figure 4, FCBGA encapsulation 1c can include single semiconductor bare chip 15.In certain embodiments, semiconductor bare chip 15 has a bottom surface 15b, and bottom surface 15b comes out from the end face of this chip package 1c.The active surface 15a of bare chip 15 be reversed and towards plate 40 (such as base plate for packaging or printed circuit board (PCB) etc.) chip installed surface 40a assemble.In certain embodiments, semiconductor bare chip 15 can be encapsulated in (not shown) in moulding compound, to form an encapsulation.
According to this exemplary embodiment, multiple thin space junction points 150 (such as conductive welding disk or dimpling block) can be distributed on the active surface 15a of semiconductor bare chip 15.Re-wiring layer (RDL) structure 30 is arranged between the chip installed surface 40a of bare chip 15 and plate 40.Thin space junction point 150 is disperseed the solder pad space length that (or diffusion) one-tenth is looser by this RDL structure 30.
Similarly, interconnection structure 300 can be manufactured in RDL structure 30, to redistribute above-mentioned multiple thin space junction point 150.Multiple projections 360 are arranged in RDL structure 30, to electrically connect semiconductor bare chip 15 and plate 40.RDL structure 30 can also include at least one polymer insulation layer 310, such as polyimides or epoxy, but is not limited to this.According to this exemplary embodiment, interconnection structure 300 can include that copper post-passivation interconnects (Cu-PPI) structure.
According to this exemplary embodiment, FCBGA encapsulation 1c can also include discrete passive component 130, and this discrete passive component 130 is embedded in RDL structure 30.According to this exemplary embodiment, discrete passive component 130 has two terminals 131 and 132, and wherein, by the interconnecting line of interconnection structure 300, the two terminal can be respectively electrically connected to the earth point on the active surface 15a of semiconductor bare chip 15 and power supply point.
Although the embodiment of the present invention and advantage thereof being described in detail, but it is to be understood that, without departing from the spiritual of the present invention and scope as defined in the claims, the present invention can be carried out various change, replace and change.Purpose that described embodiment is merely to illustrate in all respects and be not intended to limit the present invention.Protection scope of the present invention is when being as the criterion depending on the defined person of appending claims.Those skilled in the art all do a little change and retouching in without departing from the spirit and scope of the present invention.

Claims (25)

1. a chip package, it is characterised in that including:
First bare chip, is encapsulated in moulding compound；
Rewiring Rotating fields, is positioned on the active surface of this first bare chip；And
Discrete device, is embedded in this moulding compound, and is located close to the position of the lateral edges of this first bare chip.
2. chip package as claimed in claim 1, it is characterised in that this chip package also includes the second bare chip, and this first bare chip and this second bare chip are arranged side by side, and are all encapsulated in this moulding compound.
3. chip package as claimed in claim 2, it is characterised in that this rewiring Rotating fields is additionally arranged on the active surface of this second bare chip.
4. chip package as claimed in claim 2, it is characterised in that the edge-to-edge distance between this first bare chip and this second bare chip is equal to or more than 1000 microns.
5. chip package as claimed in claim 1, it is characterised in that this discrete device has a surface, and this surface substantially flushes with this active surface of this first bare chip, and this rewiring Rotating fields is also disposed on this surface of this discrete device.
6. chip package as claimed in claim 1, it is characterized in that, this discrete device has two terminals, and these two terminals are respectively electrically connected to be positioned at the ground pad on this active surface of this first bare chip and power pad by the interconnecting line in this rewiring Rotating fields.
7. chip package as claimed in claim 1, it is characterised in that multiple thin space junction points are distributed on this active surface of this first bare chip.
8. chip package as claimed in claim 1, it is characterised in that this rewiring Rotating fields also includes at least one polymer insulation layer.
9. chip package as claimed in claim 1, it is characterised in that this chip package also includes the plate with chip installed surface, and wherein, this active surface of this first bare chip is towards this chip installed surface.
10. chip package as claimed in claim 9, it is characterised in that this rewiring Rotating fields is arranged between this first bare chip and this chip installed surface.
11. 1 kinds of chip packages, it is characterised in that this chip package includes:
First bare chip, is encapsulated in moulding compound；
Rewiring Rotating fields, is positioned on the active surface of this first bare chip；And
Discrete device, is embedded in this rewiring Rotating fields.
12. chip packages as claimed in claim 11, it is characterised in that this chip package also includes the second bare chip, this first bare chip and this second bare chip are arranged side by side, and are all encapsulated in this moulding compound.
13. chip packages as claimed in claim 11, it is characterized in that, this discrete device has two terminals, and these two terminals are respectively electrically connected to the ground pad on this active surface of this first bare chip and power pad by the interconnecting line in this rewiring Rotating fields.
14. chip packages as claimed in claim 11, it is characterised in that multiple thin space junction points are distributed on this active surface of this first bare chip.
15. chip packages as claimed in claim 11, it is characterised in that this rewiring Rotating fields also includes at least one polymer insulation layer.
16. chip packages as claimed in claim 11, it is characterised in that this chip package also includes the plate with chip installed surface, and this active surface of this first bare chip is towards this chip installed surface.
17. chip packages as claimed in claim 16, it is characterised in that this rewiring Rotating fields is arranged between this first bare chip and this chip installed surface.
18. 1 kinds of chip packages, including:
Semiconductor bare chip；
Rewiring Rotating fields, is positioned on the active surface of this semiconductor bare chip；And
Discrete device, is embedded in this rewiring Rotating fields.
19. chip packages as claimed in claim 18, it is characterised in that this semiconductor bare chip is encapsulated in moulding compound.
20. chip packages as claimed in claim 18, it is characterised in that this semiconductor bare chip has the bottom surface that the end face from this chip package comes out.
21. chip packages as claimed in claim 18, it is characterised in that this discrete device is arranged on the intracavity of the bottom surface of this chip package recessed.
22. chip packages as claimed in claim 18, it is characterized in that, this discrete device has two terminals, and these two terminals are respectively electrically connected to ground pad and the power pad being positioned on the active surface of this first bare chip by the interconnecting line in this rewiring Rotating fields.
23. chip packages as claimed in claim 18, it is characterised in that multiple thin space junction points are distributed on this active surface of this semiconductor bare chip.
24. chip packages as claimed in claim 18, it is characterised in that this chip package also includes the plate with chip installed surface, and this active surface of this semiconductor bare chip is towards this chip installed surface.
25. chip packages as claimed in claim 24, it is characterised in that this rewiring Rotating fields is arranged between this semiconductor bare chip and this chip installed surface.
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Application publication date: 20160803