KR20090128953A - Method of fabricating a microvia for chip embedded printed circuit board - Google Patents

Abstract

PURPOSE: A method for manufacturing a micro via of a chip embedded printed circuit board is provided to form a connection part with high reliability by implementing a metal combination and a chemical combination at the same time. CONSTITUTION: A structure is formed on a surface of a carrier plate. The structure is comprised of a copper foil and an insulation layer. An opening unit is formed by selectively etching an I/O pad connection part of the chip. The opening selectively exposes the copper foil. A solder bump is formed on the exposed surface of the copper foil by the solder plating or solder paste printing. The I/O pad of the chip is bonded with the solder bump by the chip bonding. A bonding sheet(250) and the copper foil are laminated on the chip. A carrier plate is removed. A copper foil circuit(280) is formed by selectively etching the copper foil of the substrate.

Description

METHOD OF FABRICATING A MICROVIA FOR CHIP EMBEDDED PRINTED CIRCUIT BOARD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed circuit board, and more particularly, to a method for forming micro vias for manufacturing a printed circuit board having a chip.

Recently, the embedded PRINTED CIRCUIT BOARD technology, which manufactures passive devices such as capacitors or inductor coils, as well as active devices such as semiconductor chips, is embedded in printed circuit boards.

Input / output (I / O) pads, which are applied to on-chip printed circuit board technology, are smaller and narrower than the pitches of I / O pads and wirings used in general printed circuit board processes. Therefore, the alignment of micro vias for connecting the input / output I / O pads of the chip and the printed circuit board is very important.

1A to 1D are cross-sectional views of products in which a chip is embedded in a substrate by connecting a pad of the chip and a substrate through a micro via according to the related art. Referring to FIG. 1A, the chip 100 is embedded in the substrate through an adhesive film 109.

At this time, the copper foil circuit of the substrate to be subsequently made and the pad 111 of the chip embedded at the wafer level are connected to each other through the micro vias 120. However, as shown in FIG. 1B or 1C, when a slight alignment error 121 occurs to the left or the right side in the process of fabricating the micro via 120, copper plating is filled through the micro via to fill the circuit and chip of the substrate. When the pad is energized, a defect such as an electrical short may appear.

Accordingly, a first object of the present invention is to provide a new method for manufacturing a substrate having reliability with sufficient tolerance to manufacturing alignment problems in the electrical connection between the board circuit and the pad of the chip by embedding the chip in the substrate. To provide.

The second object of the present invention is to provide a micro via forming method and a chip embedding technology that ensure more precise and high reliability, instead of the micro via processing method using a laser and the electrical connection method using a plating filling technique used in the prior art. have.

In order to achieve the above object, the present invention forms a solder bump by electroplating or printing process by removing the insulating layer to a small process at the position where the chip and the circuit board is connected. The chips can then be joined by heat and pressure to connect and laminated with an insulating layer to form a chip embedded core CCL (copper cladded laminate).

The microvia formation and connection technology of the chip embedded substrate according to the present invention is intended to form a perfect sphere in order to lower the surface energy of the liquid solder when the solder bump and the chip is connected, so that the exact position even if slightly misaligned during chip bonding Will self-align to. Therefore, more precise chip alignment can be achieved than the conventional method of processing a laser and plating by using a guide on a printed circuit board, and a high reliability connection is realized by simultaneously implementing a metallurgical bond and a chemical bond through a solder. Can be formed.

The present invention relates to a method of manufacturing a printed circuit board in which a chip is embedded, the method comprising: (a) forming a structure in which a copper foil and an insulating layer are laminated on a surface of a carrier plate, and according to a circuit selected for the insulating layer. Selectively exposing the copper foil by selectively etching a portion to which the I / O pad is to be connected to form an opening; (b) forming solder bumps on the exposed copper foil surface; (c) chip bonding by reflowing the solder bumps and aligning the I / O pads of the chip to be embedded with the solder bumps; (d) laminating and laminating a bonding sheet and a copper foil on the chip bonded chips and peeling and removing the carrier plate; And (e) selectively etching the double-sided copper foil of the substrate according to the selected circuit to form a copper foil circuit.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, FIGS. 2A to 2I. Referring to FIG. 2A, the present invention starts from a structure in which a copper foil 210 and an insulating layer 220 are stacked on a carrier plate 200.

As a preferred embodiment of the present invention, a carrier plate having a metal layer may be used on the upper surface of the carrier plate 200. Since the carrier plate 200 is difficult to process because the thickness of the copper foil 210 is very thin, such as 3 to 5 μm, to form a fine pattern, a copper foil having a thickness of 30 μm or more may be used as a carrier plate. If the thickness of the substrate is more than a certain thickness later in the plating or lamination process, the carrier plate, which served as a support, should be removed, and a metal layer is used to facilitate peeling of the carrier plate.

According to a preferred embodiment of the present invention, it is preferable that the metal layer (not shown) and the carrier plate 200 are adhered with an adhesive and then peeled off if necessary. In addition, the metal layer (not shown) remaining after peeling the carrier plate 200 may be removed by etching by a chemical etching method. As a preferred embodiment of the present invention, the metal layer may be made of any one of nickel, titanium, chromium, aluminum, and solder, and the solder may use Pb-Sn, Sn-Ag-Cu, Sn-Cu, Sn-Bi, or the like. have.

Subsequently, in order to form solder at a portion to which an I / O pad of a chip to be embedded is to be connected, a dry film (not shown) is closely adhered to the insulating layer 220 and an image process such as photo / development / etch is performed to selectively Mask pattern is formed. When the insulating layer 220 is etched away using the patterned dry film as a mask, an opening is formed, and as shown in FIG. 2B, solder plating or solder paste printing is performed on the opening to selectively correspond to a portion where the I / O pad is to be placed. Thus, solder 230 is formed on the surface of the copper foil 210 exposed by the opening.

Subsequently, when the reflow proceeds as shown in FIG. 2C, the solder is made convex by the surface tension of the liquid phase. Referring to FIG. 2D, chip bonding is performed by aligning a chip on which an I / O pad 240 is formed with a solder 230 formed on a substrate (FIG. 2E). Subsequently, the bonding sheet 250 and the copper foil 260 are laminated, heated and pressed to laminate them (FIG. 2F). Then, the carrier plate 200 is removed and the image operation is performed with the dry film 270 to form the copper foil circuit 280 on the outer layer of the substrate (FIG. 2i).

The foregoing has somewhat broadly improved the features and technical advantages of the present invention to better understand the claims that follow. Additional features and advantages that make up the claims of the present invention will be described below. It should be appreciated by those skilled in the art that the conception and specific embodiments of the invention disclosed may be readily used as a basis for designing or modifying other structures for carrying out similar purposes to the invention.

In addition, the inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. In addition, such modifications or altered equivalent structures by those skilled in the art may be variously evolved, substituted and changed without departing from the spirit or scope of the invention described in the claims.

As described above, according to the present invention, by forming a micro-via, the insulating layer is processed to be removed at a position where the chip and the circuit board are connected to each other, and the solder bump is removed by electroplating or printing to connect the chip to the I / O pad. It is easy to align and it is possible to form a highly reliable joint.

1A-1D illustrate a manufacturing technique for connecting a pad of a chip and a substrate through micro vias according to the prior art;

2A to 2I illustrate a method of forming micro vias for manufacturing a printed circuit board having a chip according to the present invention.

<Explanation of symbols for the main parts of the drawings>

     100: chip

     109: adhesive

     111: Via

     120: pad

     200: carrier plate

210, 260: copper foil

     220: insulation layer

     230: solder

     240: I / O pad

     250: bonding sheet

     270: dry film

Claims (2)

In the method of manufacturing a printed circuit board with a chip, (a) forming a structure in which a copper foil and an insulating layer are laminated on the surface of the carrier plate, and selectively opening portions by selectively etching portions to which I / O pads of the chip are connected according to a circuit selected for the insulating layer. Selectively exposing copper foil; (b) forming solder bumps on the exposed copper foil surface; (c) chip bonding by reflowing the solder bumps and aligning the I / O pads of the chip to be embedded with the solder bumps; (d) laminating and laminating a bonding sheet and a copper foil on the chip bonded chips and peeling and removing the carrier plate; And (e) selectively etching the double-sided copper foil of the substrate according to a selected circuit to form a copper foil circuit Chip embedded substrate manufacturing method comprising a. The method of claim 1, wherein the solder bumps of step (b) are formed by solder plating or solder paste printing.

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