KR20090118375A - Method of manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A manufacturing method of a semiconductor device is provided to prevent resistance reduction of a gate line by forming a metal film through a damascene method after a gate pattering process. CONSTITUTION: A gate insulation film(102) and gate lines are formed on a top part of a semiconductor substrate(100). An insulation film(112) is formed between the gate lines. A groove is formed by lowering a height of the gate lines. A metal film is filled inside the groove. The gate lines comprise a first conductive film, a dielectric film, and a second conductive film.

Description

Method of manufacturing semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for preventing surface damage to an etching process or an ion implantation process of a gate line.

The semiconductor device includes a memory cell in which data is stored and a switch transistor for transferring a driving voltage. An example of a flash device is as follows.

The flash device includes a cell area in which data is stored and a peripheral circuit area in which a driving voltage is transferred. The cell region consists of a plurality of strings, each string including a memory cell and a select transistor. The peripheral circuit area includes a plurality of switching transistors. The memory cell is electrically connected to the word line, and the select transistor is electrically connected to the select line. In addition, the transistors in the peripheral circuit region are electrically connected to the high voltage or low voltage gate lines according to the level of the driving voltage.

Generally, flash devices can be manufactured in the following order.

The stacked layers for the gate line are formed on the semiconductor substrate. For example, the stacked films may be formed by stacking a gate insulating film, a first conductive film for a floating gate, a dielectric film, a capping film, a second conductive film for a control gate, and a metal film. Subsequently, the word line, the select line, and the high voltage (or low voltage gate line) may be formed by patterning according to the pattern of the gate line, and then an ion implantation process may be performed to form the junction region.

Meanwhile, in the manufacturing method as described above, the area of the metal film formed on the gate line may be increased in proportion to the area exposed to the etching process or the ion implantation process. Accordingly, the resistance of the gate lines (word lines, select lines, and high voltage (or low voltage) gate lines) may increase, thereby lowering electrical characteristics of the semiconductor device and lowering reliability.

The problem to be solved by the present invention, by forming a metal film formed on the gate line by a damascene method after the gate patterning process, it is possible to prevent the reduction of the resistance of the gate line.

In the method of manufacturing a semiconductor device according to an embodiment of the present disclosure, a gate insulating layer and gate lines are formed on the semiconductor substrate. An insulating film is formed between the gate lines. The height of the gate lines is lowered to form grooves. It is made of a semiconductor device manufacturing method comprising the step of filling a metal film inside the groove.

The gate lines are formed of the first conductive film, the dielectric film, and the second conductive film, and the second conductive film is formed thicker by the thickness of the metal film to be subsequently formed.

The method may further include forming a junction region in the semiconductor substrate between the gate lines.

After filling the metal film, the insulating film is etched to leave spacers on the sidewall of the gate line.

Performing an etching process for remaining as a spacer, and performing an ion implantation process.

In a method of manufacturing a semiconductor device according to another embodiment of the present invention, a gate pattern in which a gate insulating film, a first conductive film, a dielectric film, and a second conductive film are stacked is formed on a semiconductor substrate. The second conductive film, the dielectric film, and the first conductive film are sequentially patterned to form a second conductive pattern, a dielectric pattern, and a first conductive pattern. An insulating film is formed on the exposed gate insulating film. The height of the second conductive pattern is lowered to form grooves. It is made of a semiconductor device manufacturing method comprising the step of filling a metal film inside the groove.

The second conductive film is formed thicker than the thickness of the metal film in the thickness of the control gate to be finally formed.

The forming of the insulating film may include filling the gap between the first conductive pattern, the dielectric pattern, and the second conductive pattern, forming the insulating film to cover the second conductive pattern, and performing a planarization process to expose the second conductive pattern. Include.

After forming the second conductive pattern, the dielectric pattern, and the first conductive pattern, the method may further include forming a junction region on the semiconductor substrate by performing an ion implantation process.

After the filling of the metal film, a protective film is formed on the metal film and the insulating film. The insulating layer is etched to form spacers on the sidewalls of the gate pattern. And forming an etch stop layer along surfaces of the spacers, the exposed metal film, and the exposed gate insulating film. The protective film is formed of an oxide film.

Prior to forming the etch stop layer, the method may further include performing an ion implantation process to improve electrical characteristics of the junction region, and further comprising forming a capping layer between the dielectric layer and the second conductive layer.

According to the present invention, the metal film formed on the gate line is formed by the damascene method after the gate patterning process, thereby reducing the etching damage and the surface damage of the ion implantation process. As a result, a decrease in resistance of the gate line included in the semiconductor device can be prevented, thereby improving the reliability of the semiconductor device.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 1A, a flash device is described as follows.

A stack film for a gate line is formed on the semiconductor substrate 100 on which wells are formed. For example, a gate insulating film 102 and a floating conductive first conductive film 104 are formed on the semiconductor substrate 100. The gate insulating film 102 may be formed of an oxide film, and the first conductive film 104 may be formed of a polysilicon film. Although not shown in the cross-sectional view of the drawing, after forming the device isolation mask pattern (not shown) on the upper portion of the first conductive film 104, the semiconductor substrate 100 by performing an etching process in accordance with the device isolation mask pattern (not shown) To form a trench. An isolation layer (not shown) is filled in the trench.

Subsequently, the dielectric film 106 and the capping film 108 are formed along the surfaces of the first conductive film 104 and the device isolation film (not shown). Alternatively, the process of forming the capping film 108 may be omitted. In the drawing, the capping film 108 will be described as an example. A hard mask pattern (not shown) for forming a dielectric film contact hole (ONC) is formed on the capping film 108, and the capping film 108 and the dielectric film 106 are formed according to the hard mask pattern (not shown). Is etched to form a dielectric film contact hole ONC exposing the first conductive film 104. The hard mask pattern (not shown) is removed. In this case, the dielectric film contact hole ONC is formed in the region where the select line and the high voltage (or low voltage) gate line are to be formed.

Subsequently, the second conductive layer 110 for the control gate is formed on the capping layer 108 and the exposed first conductive layer 104. The second conductive film 110 may be formed of a polysilicon film. In particular, the second conductive layer 110 is preferably formed thicker than the thickness T1 of the control gate to be finally formed for the damascene process to be performed later. For example, the second conductive film 110 may be formed to be thicker than the thickness T1 of the gate line metal film to be formed subsequently to the thickness T1 to be finally formed.

Referring to FIG. 1B, a photoresist pattern (not shown) having gate line patterns WL, SSL, DSL, and HVN is formed on the second conductive layer 110 (in FIG. 1A). An etching process is performed according to the photoresist pattern (not shown) to form the second conductive pattern 110a, the capping pattern 108a, the dielectric pattern 106a, and the second conductive pattern 104a. As a result, patterns for the word line WL, the source select line SSL, the drain select line DSL, and the high voltage gate line HVN can be formed.

Subsequently, an ion implantation process is performed on the semiconductor substrate 100 exposed between the pattern for the word line WL, the source select line SSL, the drain select line DSL, and the high voltage gate line HVN in the cell region and the peripheral circuit region. Is performed to form the junction region 100a. Specifically, the junction region 100a is formed on the word line WL, the source select line SSL, the drain select line DSL, the high voltage gate line HVN, and the exposed gate insulating layer 102. An exposed mask pattern (not shown) is formed. An ion implantation process is performed according to a mask pattern (not shown) to form the junction region 100a. The mask pattern (not shown) is removed. In this case, the gate insulating layer 102 that is not patterned and exposed may reduce stress that the semiconductor substrate 100 receives during the ion implantation process.

Referring to FIG. 1C, an interlayer insulating layer 112 is formed on the gate insulating layer 102. The interlayer insulating film 112 may be formed of an oxide film. The interlayer insulating layer 112 has an upper portion of the second conductive pattern 110a so as to sufficiently fill the space between the word line WL, the source select line SSL, the drain select line DSL, and the high voltage gate line HVN. It is preferable to form so that it may cover all.

Next, a planarization process is performed to expose the second conductive pattern 110a. The planarization process may be performed by a chemical mechanical polishing (CMP) process.

Referring to FIG. 1D, an etching process for lowering the height of the second conductive pattern 110a exposed by the damascene method is performed. The etching process may be performed by a dry etching process. For example, the etching process may be performed under the condition that the etching rate of the second conductive pattern 110a is higher than that of the interlayer insulating layer 112. The etching process may be performed by a front surface etching process or by using a mask pattern for gate patterning. An etching process is performed to form grooves (or trenches H) for forming subsequent metal films. As a result, the remaining thickness T1 of the second conductive pattern 110a becomes the thickness of the final control gate, and the depth T2 of the groove H becomes the thickness of the metal film to be subsequently formed.

Referring to FIG. 1E, the gate line metal film 114 is filled in the groove H. Specifically, it is preferable that the metal film 114 is formed to cover the upper portion of the interlayer insulating film 112 so as to fill the inside of the groove H sufficiently. Next, a planarization process is performed to expose the interlayer insulating film 112. As such, since the metal film 114 is formed by the damascene method, since the metal film 114 is not directly patterned, surface damage of the metal film 114 can be reduced.

Referring to FIG. 1F, a passivation layer 116 for protecting the metal layer 114 may be formed on the metal layer 114 and the interlayer insulating layer 112. Alternatively, the step of forming the passivation layer 116 may be omitted, but it is preferable to perform the passivation layer 116 to protect the passivation layer 116 during the etching process for forming the subsequent interlayer insulating layer 112 as a spacer.

Referring to FIG. 1G, an etching process for forming the interlayer insulating film 112 of FIG. 1F as the spacer 112a is performed. Specifically, it is preferable to perform the etching process by a dry etching process. At this time, the interval between the word line WL and the interval between the word line WL and the neighboring source (or drain) select line SSL or DSL are narrow due to the increase in the degree of integration. Etching speed is slow. On the other hand, since the gap between the drain select line DSL and the high voltage (or low voltage) gate line HVN is wider than the gap between the word lines WL, the etching speed is faster. A portion of the interlayer insulating film 112 of FIG. 1F remains on the sidewall of the drain (or source) select line DSL or SSL and the sidewall of the high voltage (or low voltage) gate line HVN to form a spacer 112a. After the spacer 112a is formed, an ion implantation process may be further performed to improve the electrical characteristics of the junction region 100a in the cell region or the peripheral circuit region.

Subsequently, an etch stop layer 118 is formed along the surfaces of the spacer 112a, the metal layer 114, and the gate insulating layer 102 to be used in a subsequent process of forming a contact hole. The etch stop layer 118 may be formed of a nitride layer.

As described above, since the patterning process of the metal film can be omitted by forming the metal film by the damascene method, the surface damage of the metal film can be reduced to prevent the increase in resistance. In addition, since damage caused by plasma can be suppressed in a subsequent ion implantation process, the electrical characteristics of the word line WL, the source select line SSL, the drain select line DSL, and the high voltage gate line HVN are prevented. can do. As a result, the reliability of the semiconductor device can be improved.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 102 gate insulating film

104: first conductive film 106: dielectric film

108: capping film 110: second conductive film

112: interlayer insulating film 112a: spacer

114: metal film 116: protective film

118: etching stop film

Claims (13)

Forming a gate insulating film and gate lines on the semiconductor substrate; Forming an insulating film between the gate lines; Lowering the height of the gate lines to form grooves; And The method of manufacturing a semiconductor device comprising the step of filling a metal film inside the groove. The method of claim 1, The gate lines are formed of a first conductive film, a dielectric film and a second conductive film. The method of claim 2, And the second conductive film is formed thicker by the thickness of the metal film to be subsequently formed. The method of claim 1, And forming a junction region in the semiconductor substrate between the gate lines. The method of claim 1, wherein after the filling of the metal film, Etching the insulating film to leave spacers on sidewalls of the gate line; And A method of manufacturing a semiconductor device further comprising the step of performing an ion implantation process. Forming a gate pattern on which a gate insulating film, a first conductive film, a dielectric film, and a second conductive film are stacked on a semiconductor substrate; Sequentially patterning the second conductive film, the dielectric film, and the first conductive film to form a second conductive pattern, a dielectric pattern, and a first conductive pattern; Forming an insulating film on the exposed gate insulating film; Lowering the height of the second conductive pattern to form a groove; And The method of manufacturing a semiconductor device comprising the step of filling a metal film inside the groove. The method of claim 6, And the second conductive film is formed to be thicker than the thickness of the metal film in a thickness of a control gate to be finally formed. The method of claim 6, wherein the forming of the insulating film, Forming the insulating layer between the first conductive pattern, the dielectric pattern, and the second conductive pattern to cover the second conductive pattern; And And performing a planarization process so that the second conductive pattern is exposed. The method of claim 6, After forming the second conductive pattern, the dielectric pattern and the first conductive pattern, And forming a junction region on the semiconductor substrate by performing an ion implantation process. The method of claim 6, wherein after the filling of the metal film, Forming a protective film on the metal film and the interlayer insulating film; Etching the insulating layer to form a spacer on sidewalls of the gate pattern; And And forming an etch stop layer along surfaces of the spacers, the exposed metal layer, and the exposed gate insulating layer. The method of claim 10, The protective film is a semiconductor device manufacturing method of forming an oxide film. The method of claim 10, Prior to forming the etch stop layer, further comprising the step of performing an ion implantation process for improving the electrical characteristics of the junction region. The method of claim 6, And forming a capping film between the dielectric film and the second conductive film.

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