KR20090088683A - Thyristor and method for manufacturing the same - Google Patents

Abstract

A thyristor and a manufacturing method thereof are provided to reduce a dimension of a semiconductor device and to simplify a manufacturing process by using a thyristor manufactured by a P+ poly gate DRAM cell process. A plurality of isolation films(106) is formed on a top part of a P-type sub substrate(102), and defines an N-type well(104), an anode region, and a cathode region. A P-type polysilicon(114) and a gate material layer are successively deposited and etched on a whole surface of the cathode region. A gate(120) in which one side of the P-type polysilicon is exposed is formed. An ion layer is formed on a top part of the anode region. A spacer film(122) is deposited and etched on a whole surface of the ion layer and the gate of the cathode region. An N-type polysilicon(130) is connected to the exposed P-type polysilicon and the exposed gate material layer.

Description

Thyristor and its manufacturing method {THYRISTOR AND METHOD FOR MANUFACTURING THE SAME}

The present invention relates to a thyristor and a method of manufacturing the same, and more particularly, using a thyristor for applying a high voltage or a high current when blowing an electrical fuse, by using a P + poly gate DRAM cell process to form a thyristor to simplify the manufacturing process and the semiconductor It relates to a technique for minimizing the area of the device.

In general, fabrication of a semiconductor device is a FABrication (FAB) process of forming cells having integrated circuits by repeatedly forming circuit patterns set on a silicon substrate. A packaging process includes packaging the substrate on which the cells are formed, in a chip unit. In addition, between the fabrication process and the packaging process, electrical die sorting (hereinafter referred to as EDS) for detecting defective cells is performed by inspecting electrical characteristics of the cells formed on the substrate.

The EDS process is a process of determining whether the cells formed on the substrate have an electrically good state or a bad state. The EDS process eliminates bad cells before performing the packaging process, reducing the effort and cost of the packaging process. Then, the cells having a bad state are found early and reproduced through the repair.

In other words, if a defective cell is found, a repair method is used to restore the entire memory by replacing an extra memory cell (hereinafter, referred to as a redundancy cell) previously formed in the memory with a defective cell during the manufacturing process. do.

One such repair method is an electrical fuse blowing method. An electrical fuse blowing method is to blow a fuse by an electrical stress by applying a high voltage or a high current. Thus, for the electrical fuse blowing, a separate circuit for applying a high voltage or a high current has to be configured, but the circuit configuration is complicated and the area consumption is large. Accordingly, a thyristor may be used to control high voltage or high current.

Such a thyristor is a power semiconductor device used for controlling current and voltage, and is also called a silicon controlled rectifier (SCR).

As shown in FIG. 1A, the thyristor is composed of three terminals of an anode, a cathode, and a gate. At this time, when a signal is applied to the gate, the current is maintained until a reverse current is applied to the main circuit or the current falls below a holding current without supplying a continuous gate current.

Referring to FIG. 1B, the thyristor has a p-n-p-n four-layer structure, and as shown in FIG. 1C, two bipolar transistors are connected to a cathode, an anode, and a gate.

However, in the related art, there is an inconvenience in that the process is complicated by manufacturing the thyristors through a separate process for electrical fuse blowing, and even if manufactured, the thyristors having the structure as shown in FIG. 1B have a large area consumption.

The present invention has been made to solve the above problems, an object of the present invention is to use a thyristor for applying a high voltage or a high current when blowing the electrical fuse, the thyristor is a P + poly gate DRAM (DRAM) cell process The purpose of the present invention is to simplify the process and to reduce the area of the semiconductor device by forming the material by utilization.

A method of manufacturing a thyristor according to the present invention for achieving the above object is to form a plurality of device isolation film defining an N-type well and an anode region and a cathode region on the P-type sub-substrate and the front surface of the cathode region Sequentially depositing and etching a P-type polysilicon and a gate material layer to form a gate in which one side of the P-type polysilicon is exposed, an ion layer is formed on the anode region, and the gate of the cathode region is formed. And depositing a spacer layer on the entire surface of the ion layer and etching to expose one side of the P-type polysilicon and the gate material layer, and an N-type poly connected to the exposed P-type polysilicon and the exposed gate material layer. Forming silicon, and firstly connected to the N-type polysilicon and the ion layer, respectively And it characterized by including the step of forming the second wiring.

The forming of the gate may include forming the N type well on the P type sub substrate, spaced apart the plurality of device isolation layers on the entire surface of the N type well, Depositing gate polysilicon on the plurality of device isolation layers, forming a photoresist pattern on the gate polysilicon, etching the gate polysilicon according to the photoresist pattern, and etching the gate polysilicon Etching a portion of the N-type well using a gate polysilicon as a hard mask.

In some embodiments, the etching of the portion of the N-type well may include etching the N-type well between the device isolation layers.

In addition, exposing the P-type polysilicon and one side of the gate material layer may form the ion layer by implanting P + ions.

In addition, exposing the P-type polysilicon and one side of the gate material layer may include depositing a first interlayer dielectric layer on the spacer layer, forming a photoresist pattern on the first interlayer dielectric layer, And etching a portion of the first interlayer dielectric layer and the spacer layer according to the photoresist pattern.

The forming of the first wiring and the second wiring may include depositing a second interlayer insulating film on the first interlayer insulating film and the N-type polysilicon, and the second interlayer insulating film and the first interlayer insulating film. Etching a portion to form a first contact plug connected to the ion layer and a second contact plug connected to the N-type polysilicon; and forming the first contact plug and the second contact plug on the second interlayer insulating layer. And forming a first wiring and a second wiring respectively connected to each other.

In the forming of the first wiring and the second wiring, the first wiring may be formed as an anode, and the second wiring may be formed as a cathode.

Also, a plurality of device isolation layers spaced apart in an N type well on an P type sub substrate to define an anode region and a cathode region, an ion layer formed on an N type well of the anode region, and the cathode region A gate formed on one side of an upper portion of the P-type polysilicon provided in the gate, an N-type polysilicon formed on the upper and sidewalls of the gate and connected to the P-type polysilicon, and a spacer layer separating the N-type polysilicon and the gate sidewall A first contact plug connected to the ion layer, a second contact plug connected to the N-type polysilicon, a first wiring connected to the first contact plug and a second contact plug, and a second wiring connected to each other. It is characterized by including.

In addition, the ion layer is characterized in that the P + ions are implanted.

The first wiring is an anode, and the second wiring is a cathode.

In addition, the gate is formed by sequentially depositing tungsten silicide (Wsi) and nitride material (nitride) on the P-type polysilicon.

As described above, the present invention simplifies the manufacturing process and reduces the area of the semiconductor device by controlling by using a thyristor manufactured using the P + poly gate DRAM cell process, without having to separately manufacture a circuit for controlling the electric fuse blowing. There is.

Hereinafter, a semiconductor device according to the present invention will be described in detail with reference to FIGS. 2 to 3J.

First, FIG. 2 is a cross-sectional view of a thyristor according to an embodiment of the present invention.

The thyristor according to the present invention is formed with an isolation layer 106 and an anode 136 separating the N type well 104 and the N type well 104 on the P type sub substrate 102. P-type polysilicon 114 and tungsten silicide (WSi) between the ion layer 121 implanted with P + ions between the device isolation films 114 at the bottom of the region to be implanted, and the device isolation film 106 at the bottom of the region where the cathode 138 is to be formed. 116 and a nitride layer 118 sequentially stacked, the spacer layer 122 and the gate 120 having a predetermined thickness formed on the entire surface of the gate 120, the gate 120, and the device isolation layer 106. N-type polysilicon 130 formed on the sidewall and connected to the P-type polysilicon 114, a contact plug 132 connecting the ion layer 121 and the anode 136, formed on the spacer layer 122, N The first interlayer insulating film 124 surrounding the type polysilicon 130 and the contact plug 132 is deposited on the first interlayer insulating film, A contact plug 134 is formed on the second interlayer insulating layer 131 surrounding the plugs 132 and 134, the contact plug 134 connecting the N-type polysilicon 130 and the cathode 138, and the second interlayer insulating layer 131. An anode 136 and a cathode 138 connected to 132 and 134, respectively.

Hereinafter, the thyristor manufacturing method of the present invention will be described in detail with reference to FIGS. 3A to 3J.

First, referring to FIG. 3A, an N type well 104 is formed on a P type sub substrate 102, and an isolation layer 106 is formed by a shallow trench isolation (STI) process. In this case, the device isolation layer 106 is formed to be spaced apart from the upper end of the N-type well 104 to separate the gate 120 and the ion layer 121 to be formed later.

Thereafter, referring to FIG. 3B, a gate poly material 108 for hard mask is deposited on the device isolation layer 106 and the N-type well 104, and a photoresist pattern PR 110 is formed thereon to form a gate thereon. ).

Next, referring to FIG. 3C, the gate poly material 108 is etched through the etching process, and the N type well 104 is etched using the gate poly material 108 as a hard mask. Accordingly, a portion of the N type well 104 is etched to form a P type polysilicon region 112 between the device isolation layers 106.

Thereafter, referring to FIG. 3D, the P-type polysilicon 114 is deposited on the entire structure of FIG. 3C to bury the P-type polysilicon 114 in the P-type polysilicon region 112, and the P-type polysilicon ( 114) a tungsten silicide (Wsi) 116 and a nitride film (Nitride) 118 are deposited on top.

Next, referring to FIG. 3E, the nitride film 118 over the tungsten silicide 116 is defined to form the gate 120.

Thereafter, referring to FIG. 3F, the tungsten silicide 116 and the P-type polysilicon 114 are sequentially etched using the defined nitride film 118 as a barrier to form the gate 120. In this case, the P-type polysilicon 114 may be partially left between the device isolation layers 106.

After that, referring to FIG. 3G, an ion layer 121 is formed by implanting P + ions into the N type well 104 at the bottom of the region where the anode is to be formed, and forming a spacer layer having a predetermined thickness on the entire upper surface of the structure of FIG. 3F. 122 is formed, and a first interlayer insulating film 124 is deposited on the entire upper surface thereof. A photoresist pattern 126 is then formed to define the area where the N type polysilicon will be formed.

In this case, the spacer layer 122 is formed of oxide, nitride, or a combination of oxide and nitride, and the first interlayer insulating layer 124 is deposited and planarized. Here, it is preferable to use CMP for planarization.

3H, an N-type polysilicon region 128 for defining an area where N-type polysilicon is to be formed by removing a portion of the spacer layer 122 and the first interlayer insulating layer 124 through an etching process is formed. After formation, the photoresist pattern 126 is removed. At this time, the spacer layer 122 on one side of the nitride layer 118 is removed, the spacer layer 122 on the sidewall of the gate 120 remains, and the spacer layer 122 on the side of the P-type polysilicon 114 is formed. Removed.

Thereafter, referring to FIG. 3I, by filling an N-type polysilicon material in the N-type polysilicon region 128, a PN diode to which the P-type polysilicon 114 and the N-type polysilicon 130 are connected is formed. . In this case, an N + ion implantation process may be added to the N type polysilicon 130.

3J, the second interlayer insulating layer 131 is deposited and etched on the structure of FIG. 3I to form contact plugs 132 and 134 connected to the ion layer 121 and the N-type polysilicon 130, respectively. do. In this case, the contact plug 132 may be etched to the second interlayer insulating layer 131 and the first interlayer insulating layer 124 so as to be connected to the ion layer 121.

Thereafter, an anode 136 connected to the contact plug 132 is formed on the upper portion thereof, and a cathode 138 connected to the contact plug 134 is formed.

Figure 1a is a circuit diagram of a typical thyristor.

1B is a cross-sectional view of a typical thyristor.

1C is a circuit diagram of a typical thyristor.

2 is a cross-sectional view of a thyristor according to an embodiment of the present invention.

3A to 3J are cross-sectional views of a thyristor according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

102: P type sub substrate 104: N type well

106: device isolation film 108: gate polysilicon

110 and 126 photoresist pattern 112 P-type polysilicon region

114: P-type polysilicon 116: tungsten silicide

118: nitride film 120: gate

122 spacer film 124 first interlayer insulating film

128: N type polysilicon area 130: N type polysilicon

131: second interlayer insulating film 132, 134: contact plug

136: anode 138: cathode

Claims (11)

Forming a plurality of device isolation layers defining an N type well and an anode region and a cathode region on the P type sub substrate, and sequentially depositing and etching a P type polysilicon and a gate material layer on the entire surface of the cathode region to form the P type poly Forming a gate in which one side of the silicon is exposed; Forming an ion layer on the anode region, depositing a spacer layer over the gate and the ion layer in front of the cathode region, and etching the semiconductor layer to expose one side of the P-type polysilicon and the gate material layer; Forming an N-type polysilicon in contact with the exposed P-type polysilicon and the exposed gate material layer; And Forming first wirings and second wirings respectively connected to the N-type polysilicon and the ion layer; Thyristor manufacturing method comprising a. The method of claim 1, wherein the forming of the gate comprises: Forming the N type well on the P type sub substrate; Forming a plurality of device isolation layers on the entire surface of the N-type well; Depositing a gate polysilicon on the N type well and the plurality of device isolation layers; Forming a photoresist pattern on the gate polysilicon; Etching the gate polysilicon according to the photoresist pattern; And Etching a portion of the N-type well using the etched gate polysilicon as a hard mask Thyristor manufacturing method comprising a. The method of claim 2, And etching the portion of the N-type well, wherein the N-type well between the device isolation layers is partially etched. The method of claim 1, Exposing the P-type polysilicon and one side of the gate material layer to form the ion layer by implanting P + ions. The method of claim 1, wherein exposing the P-type polysilicon and one side of the gate material layer comprises: Depositing a first interlayer dielectric layer on the spacer layer; Forming a photoresist pattern on the first interlayer insulating film; And Etching a portion of the first interlayer insulating layer and the spacer layer according to the photoresist pattern Method for producing a thyristor comprising a. The method of claim 1, wherein the forming of the first wiring and the second wiring comprises: Depositing a second interlayer dielectric layer on the first interlayer dielectric layer and the N-type polysilicon layer; Etching the second interlayer insulating film and a portion of the first interlayer insulating film to form a first contact plug connected to the ion layer and a second contact plug connected to the N-type polysilicon; And Forming first wirings and second wirings on the second interlayer insulating layer and respectively connected to the first contact plugs and the second contact plugs; Method for producing a thyristor comprising a. The method of claim 1, wherein the forming of the first wiring and the second wiring comprises: And forming the first wiring as an anode and the second wiring as a cathode. A plurality of device isolation layers spaced apart in an N-type well on the P-type sub substrate to define an anode region and a cathode region; An ion layer formed on the N type well of the anode region; A gate formed on one side of an upper portion of the P-type polysilicon provided in the cathode region; N-type polysilicon formed on the gate and sidewalls and connected to the P-type polysilicon; A spacer layer separating the N-type polysilicon and the gate sidewall; A first contact plug connected to the ion layer; A second contact plug connected with the N type polysilicon; First and second wirings connected to the first and second contact plugs, respectively. Thyristor comprising a. The method of claim 8, The ion layer is thyristor, characterized in that the implanted P + ions. The method of claim 8, The first wiring is an anode, and the second wiring is a cathode. The method of claim 8, The gate is a thyristor, characterized in that formed by sequentially depositing tungsten silicide (Wsi) and nitride material (nitride) on the P-type polysilicon.

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