CN116632003B - Preparation method of ESD protection device and ESD protection device - Google Patents
Preparation method of ESD protection device and ESD protection device Download PDFInfo
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- CN116632003B CN116632003B CN202310911903.4A CN202310911903A CN116632003B CN 116632003 B CN116632003 B CN 116632003B CN 202310911903 A CN202310911903 A CN 202310911903A CN 116632003 B CN116632003 B CN 116632003B
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- 238000002955 isolation Methods 0.000 claims abstract description 119
- 238000002347 injection Methods 0.000 claims abstract description 80
- 239000007924 injection Substances 0.000 claims abstract description 80
- 238000004519 manufacturing process Methods 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 21
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- 238000002513 implantation Methods 0.000 claims description 70
- 238000000034 method Methods 0.000 claims description 59
- 238000000137 annealing Methods 0.000 claims description 44
- 239000007943 implant Substances 0.000 claims description 25
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 238000002161 passivation Methods 0.000 claims description 8
- 238000011049 filling Methods 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
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- 239000002344 surface layer Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
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- 229910052802 copper Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The application relates to a semiconductor chip technology, and discloses a preparation method of an ESD protection device, which comprises the following steps: forming a P-epitaxial layer and an N-epitaxial layer on the P+ substrate; forming a first P+ isolation region and a second P+ isolation region longitudinally penetrating the N-epitaxial layer; forming a P well region in the N-epitaxial layer between the first P+ isolation region and the second P+ isolation region; forming a first n+ injection region and a first p+ injection region within the N-epitaxial layer between the first p+ isolation region and the P-well region, and forming a second n+ injection region at a boundary crossing between the N-epitaxial layer and the P-well region, and forming a second p+ injection region and a third n+ injection region within the P-well region; isolation trenches are formed longitudinally through the N-epitaxial layer, respectively. The application also discloses an ESD protection device. The application aims to reduce the manufacturing size of an ESD protection device on the premise of not influencing the current capacity of the ESD protection device.
Description
Technical Field
The present application relates to the field of semiconductor chip technologies, and in particular, to a method for manufacturing an ESD protection device and an ESD protection device.
Background
Integrated circuit products are extremely susceptible to ESD (Electro-Static discharge) during their production, manufacture, assembly and operation, resulting in internal damage and reduced reliability. Therefore, research into high-performance and high-reliability ESD protection devices has a crucial role in improving yield and reliability of integrated circuits. Among them, SCR (Silicon Controlled Rectifier ) devices are commonly used to fabricate ESD protection devices.
At present, under the same line width, the lateral structure of the existing low-capacitance SCR device often needs to manufacture an ESD protection device with a larger size, because the anode and the cathode of the lateral structure are both manufactured on the upper surface of the device, the sizes of the anode and the cathode cannot be reduced to be smaller than 10um under the influence of packaging, and correspondingly larger devices are needed to be manufactured. If the device size is reduced by reducing the lateral structure, the area-related current passing capability of the SCR device is reduced, that is, the current large flyback ESD protection device with the low-capacitance SCR structure is difficult to realize in smaller device package.
The foregoing is provided merely for the purpose of facilitating understanding of the technical solutions of the present application and is not intended to represent an admission that the foregoing is prior art.
Disclosure of Invention
The application mainly aims to provide a preparation method of an ESD protection device and the ESD protection device, and aims to reduce the manufacturing size of the ESD protection device on the premise of not influencing the current capacity of the ESD protection device.
In order to achieve the above object, the present application provides a method for manufacturing an ESD protection device, comprising the steps of:
providing a P+ substrate, forming a P-epitaxial layer on the P+ substrate, and forming an N-epitaxial layer on the P-epitaxial layer;
forming two P+ isolation regions which longitudinally penetrate through the N-epitaxial layer, wherein the two P+ isolation regions are a first P+ isolation region and a second P+ isolation region respectively;
forming a P well region in the N-epitaxial layer between the first P+ isolation region and the second P+ isolation region;
forming a first n+ injection region and a first p+ injection region within the N-epitaxial layer between the first p+ isolation region and the P-well region, and forming a second n+ injection region at a boundary crossing between the N-epitaxial layer and the P-well region, and forming a second p+ injection region and a third n+ injection region within the P-well region;
isolation trenches longitudinally penetrating the N-epitaxial layer are formed between the first n+ implant region and the first p+ implant region, and between the P-well region and the second p+ isolation region, respectively.
Optionally, the method for manufacturing the ESD protection device further includes:
the annealing temperature in the P+ isolation region forming process is 1200-1250 ℃, and the annealing time is 1-2 hours.
Optionally, the method for manufacturing the ESD protection device further includes:
the annealing temperature in the P well region forming process is 1000-2000 ℃ and the annealing time is 2-3 hours.
Optionally, the method for manufacturing the ESD protection device further includes:
in the process of forming the first P+ injection region and the second P+ injection region, the injected P+ dose is 1.0E15/cm & lt- & gt 1.0E16/cm;
and in the process of forming the first N+ injection region, the second N+ injection region and the third N+ injection region, the injected N+ dose is 1.0E15/cm-1.0E16/cm.
Optionally, the method for manufacturing the ESD protection device further includes:
in the process of forming a first N+ injection region, a first P+ injection region, a second N+ injection region, a second P+ injection region and a third N+ injection region, a first annealing process and a second annealing process are carried out, wherein the annealing temperature of the first annealing process is 1100-1200 ℃ and the annealing time is 10-20 seconds; the annealing temperature of the second annealing process is 800-900 ℃ and the annealing time is 30-60 minutes.
Optionally, the step of forming isolation trenches longitudinally penetrating the N-epi layer between the first n+ implantation region and the first p+ implantation region, and between the P well region and the second p+ isolation region, respectively, includes:
deep grooves longitudinally penetrating through the N-epitaxial layer are formed between the first N+ injection region and the first P+ injection region and between the P well region and the second P+ isolation region respectively;
filling isolation medium into the two deep grooves until an isolation layer with a preset thickness is formed on the N-epitaxial layer, so that the deep grooves form isolation grooves, wherein the preset thickness is 2-3.5 mu m;
and removing the isolation layer.
Optionally, after the step of forming isolation trenches longitudinally penetrating the N-epi layer between the first n+ implantation region and the first p+ implantation region, and between the P well region and the second p+ isolation region, the method further includes:
and forming an oxide layer covering the N-epitaxial layer, the first P+ isolation region, the second N+ injection region and the upper surface of the isolation groove on the N-epitaxial layer.
Optionally, after the step of forming an oxide layer on the N-epi layer to cover the N-epi layer, the first p+ isolation region, the second n+ implantation region, and the upper surface of the isolation trench, the method further includes:
forming a first metal layer on the second P+ injection region, the third N+ injection region and the second P+ isolation region so as to electrically connect the second P+ injection region, the third N+ injection region and the second P+ isolation region;
and forming a second metal layer on the first N+ implantation region and the first P+ implantation region to connect the first N+ implantation region and the first P+ implantation region.
Optionally, the method for manufacturing the ESD protection device further includes:
and forming passivation layers on the first metal layer and the second metal layer, wherein wiring points are reserved in the passivation layer above the second metal layer.
In order to achieve the above object, the present application also provides an ESD protection device manufactured using the manufacturing method of the ESD protection device as described above.
According to the manufacturing method of the ESD protection device and the ESD protection device, the ESD protection device which can use the P+ substrate as the cathode is manufactured, namely, the cathode is not required to be manufactured from the upper surface layer of the ESD protection device, so that the manufacturing size of the device can be reduced under the condition that the through-current capability of the device is maintained, the device packaging requirement of smaller volume is met, the large flyback ESD protection device with a low capacitance and a vertical structure is obtained, and when the ESD protection device is packaged, the cathode of the device is led out from the P+ substrate, the grounding wire bonding during the device packaging process can be avoided, and the packaging cost is reduced.
Drawings
Fig. 1 is a schematic diagram illustrating steps of a method for manufacturing an ESD protection device according to an embodiment of the application;
fig. 2 is a schematic diagram of an ESD protection device according to an embodiment of the application;
fig. 3 is another schematic diagram of an ESD protection device according to an embodiment of the application;
fig. 4 is a schematic diagram of an ESD protection device according to an embodiment of the application;
fig. 5 is a schematic diagram of an ESD protection device according to an embodiment of the application;
fig. 6 is a schematic diagram of an ESD protection device according to an embodiment of the application;
fig. 7 is an equivalent circuit diagram of an ESD protection device in an embodiment of the application;
fig. 8 is a schematic diagram of another structure of an ESD protection device according to an embodiment of the application.
The achievement of the objects, functional features and advantages of the present application will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below are exemplary and intended to illustrate the present application and should not be construed as limiting the application, and all other embodiments, based on the embodiments of the present application, which may be obtained by persons of ordinary skill in the art without inventive effort, are within the scope of the present application.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only (e.g., to distinguish between identical or similar elements) and is not to be construed as indicating or implying a relative importance or an implicit indication of the number of features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present application.
Referring to fig. 1, in an embodiment, the method for manufacturing the ESD protection device includes:
step S10, providing a P+ substrate, forming a P-epitaxial layer on the P+ substrate, and forming an N-epitaxial layer on the P-epitaxial layer;
s20, forming two P+ isolation regions which longitudinally penetrate through the N-epitaxial layer and the P-epitaxial layer, wherein the two P+ isolation regions are a first P+ isolation region and a second P+ isolation region respectively;
s30, forming a P well region in the N-epitaxial layer between the first P+ isolation region and the second P+ isolation region;
step S40, forming a first N+ injection region and a first P+ injection region in the N-epitaxial layer between the first P+ isolation region and the P well region, forming a second N+ injection region at a position crossing the boundary between the N-epitaxial layer and the P well region, and forming a second P+ injection region and a third N+ injection region in the P well region;
and S50, forming isolation grooves longitudinally penetrating the N-epitaxial layer between the first N+ injection region and the first P+ injection region and between the P well region and the second P+ isolation region respectively.
In this embodiment, the resistivity of the P+ substrate may be 0.0005 Ω. cm to 0.0008 Ω. cm.
As described in step S10, referring to fig. 2, a lightly doped P-epitaxial layer 101 process is completed on a pre-provided p+ substrate 100; namely, a P-epitaxial layer 101 having a resistivity of 2. Omega. Cm to 4. Omega. Cm is grown on a P+ substrate 100 by chemical vapor deposition to a thickness of 6 μm to 14. Mu.m.
Then, a lightly doped N-epi layer 102 process is completed on P-epi layer 101; an N-epitaxial layer 102 having a thickness of 6 μm to 12 μm and a resistivity of 45 Ω.cm to 55 Ω.cm (optionally 50 Ω.cm) is grown on the P-epitaxial layer 101 by chemical vapor deposition.
As described in step S20, referring to fig. 3, a left window region and a right window region are formed on the N-epi layer 102 by photolithography and etching, and the left window region and the right window region are formed to ensure that the N-epi layer 102 is penetrated longitudinally (i.e., the depth of the window region is greater than the thickness of the N-epi layer 102).
It should be noted that, here, it is only necessary to ensure that both the left and right window regions penetrate the N-epi layer 102 (this is to ensure that current can flow from the surface of the p+ isolation region formed later to the p+ substrate 100), and further, the left and right window regions may penetrate the P-epi layer 101 or may not penetrate the P-epi layer 101. Among these, it is preferable to form a p+ isolation region that penetrates the N-epitaxial layer 102 and the P-epitaxial layer 101 longitudinally (i.e., the depth of the p+ isolation region may be greater than or equal to the sum of the thicknesses of the N-epitaxial layer 102 and the P-epitaxial layer 101).
Optionally, by injecting boron into the left and right window regions, left and right P+ isolation regions can be formed; wherein the left and right p+ isolation regions are respectively marked as a first p+ isolation region 103 and a second p+ isolation region 104.
Optionally, in the process of forming the p+ isolation region, when the annealing process is completed on the p+ isolation region, the annealing temperature is 1200-1250 ℃ and the annealing time is 1-2 hours. This ensures that the P + isolation regions can extend through the N-epi layer 102 and P-epi layer 101 and further connect to the P + substrate 100.
As described in step S30, referring to fig. 3, in a partial region of the upper portion of the N-epi layer 102 between the first p+ isolation region 103 and the second p+ isolation region 104, a window region is formed by photolithography and etching, and a P-well region 105 (P-well) is formed by implanting boron in the window region. Wherein, the boron implantation dosage is determined by the trigger voltage of the pre-designed ESD protection device; for example, for a trigger voltage of 3.3V to 7.0V ESD protection device, the boron implantation dose required to form the P-well region 105 may be selected to be 4.5E15/cm to 2.0E14/cm.
Optionally, in the process of forming the P-well region 105, when the annealing process is completed on the P-well region 105, the annealing temperature is 1000 ℃ to 2000 ℃ and the annealing time is 2 hours to 3 hours, so that the junction depth of the P-well region 105 is ensured to be greater than the junction depth of the subsequently formed n+ implantation region/p+ implantation region contact.
As described in step S40, referring to fig. 4, a LOCOS (Local Oxidation of Silicon) process is adopted to form a plurality of active regions in the N-epi layer 102 and the P-well region 105 between the first p+ isolation region 103 and the P-well region 105, and n+/p+ is respectively implanted into the selection windows in each active region to form an n+ implantation region/p+ implantation region accordingly.
Optionally, a first n+ implantation region 106 and a first p+ implantation region 107 are formed in the N-epi layer 102 between the first p+ isolation region 103 and the P well region 105, wherein the first n+ implantation region 106 is disposed between the first p+ isolation region 103 and the first p+ implantation region 107, and the first p+ implantation region 107 is disposed between the first n+ implantation region 106 and the P well region 105, respectively.
Optionally, a second n+ implant region 108 is formed across the boundary between the N-epi layer 102 and the P-well region 105 (i.e., the second n+ implant region 108 spans the boundary between the N-epi layer 102 and the P-well region 105), and the second n+ implant region 108 is disposed between the first p+ implant region 107 and a subsequently formed second p+ implant region 109.
Optionally, a second p+ implantation region 109 and a third n+ implantation region 110 are formed in the P well region 105, wherein the second p+ implantation region 109 is disposed between the second n+ implantation region 108 and the third n+ implantation region 110, and the third n+ implantation region 110 is disposed between the second p+ implantation region 109 and the second p+ isolation region 104.
Thus, the n+ implant region, the p+ implant region, the P well region 105, and the N-epi layer 102 may form an SCR structure in an ESD protection device.
Optionally, in the process of forming each p+ implantation region (including the first p+ implantation region 107 and the second p+ implantation region 109), the p+ dose implanted is 1.0E15/cm to 1.0E16/cm; in the process of forming each N+ implant region (including the first N+ implant region 106, the second N+ implant region 108, and the third N+ implant region 110), the implanted N+ dose is 1.0E15/cm to 1.0E16/cm.
Optionally, in the process of forming the first n+ implantation region 106, the first p+ implantation region 107, the second n+ implantation region 108, the second p+ implantation region 109 and the third n+ implantation region 110, two annealing processes, i.e., a first annealing process and a second annealing process, are required to be completed for each n+ implantation region/p+ implantation region.
The first annealing process is a high-temperature rapid annealing process, the annealing temperature is 1100-1200 ℃, and the annealing time is 10-20 seconds. The purpose of the high temperature rapid anneal is to activate all implanted phosphorus impurities, ensure good ohmic contact, and also reduce the leakage current of the SCR structure.
After the first annealing process is completed, a second annealing process is performed. The second annealing process is a low-temperature furnace tube annealing process, the annealing temperature is 800-900 ℃, and the annealing time is 30-60 minutes. The purpose of the low temperature furnace tube annealing is to control the junction depth and breakdown voltage of the N+ injection region/P+ injection region.
As described in step S50, referring to fig. 5, a deep trench longitudinally penetrating the N-epitaxial layer 102 is formed between the first n+ implant region 106 and the first p+ implant region 107 by photolithography and etching, and a deep trench longitudinally penetrating the N-epitaxial layer 102 is formed between the P well region 105 and the second p+ isolation region 104, and two isolation trenches 111 are obtained by filling the isolation medium into the two deep trenches. The depth of the deep trench needs to be greater than the thickness of the N-epi layer 102 to ensure that the region between two isolation trenches 111 formed subsequently is not affected by each other, thereby performing isolation.
Alternatively, the depth of the deep groove may be 10 μm to 20 μm, and the width of the deep groove may be 1.5 μm to 3 μm.
The isolation medium may be polycrystalline, or may be silicon dioxide, preferably polycrystalline.
Thus, referring to fig. 6, the formed ESD protection device may be fabricated by directly using the p+ substrate 100 to fabricate a cathode GND of the ESD protection device (e.g., an electrode is led out from the p+ substrate 100 as the cathode GND of the ESD protection device), and using the first n+ injection region 106 and the first p+ injection region 107 to fabricate an anode I/O of the ESD protection device (e.g., an electrode connecting the first n+ injection region 106 and the first p+ injection region 107 is led out above the N-epitaxial layer 102 as the anode I/O of the ESD protection device), and making an electrode connecting the second p+ injection region 109, the third n+ injection region 110 and the second p+ isolation region 104 above the N-epitaxial layer 102 (the dotted line in fig. 6 represents a wire equivalent to replace the corresponding electrode, i.e., represents the corresponding wiring mode), and the equivalent circuit diagram of the resulting ESD protection device is shown in fig. 7: the P-epitaxial layer 101 and the N-epitaxial layer 102 function as a diode D, the second p+ isolation region 104 functions as a resistor R, and the first n+ implant region 106, the first p+ implant region 107, the second n+ implant region 108, the second p+ implant region 109, the third n+ implant region 110, the P well region 105, and the N-epitaxial layer 102 may together function as an SCR structure (i.e., equivalent to an SCR structure composed of the first transistor T1 and the second transistor T2).
In an embodiment, by manufacturing an ESD protection device that can use a p+ substrate as a cathode, it is not necessary to manufacture the cathode from the upper surface layer of the ESD protection device, so that the manufacturing size of the device (the allowable size can be 220 μm) can be reduced while maintaining the device current capability, the device packaging requirement of a smaller volume can be met, a large flyback ESD protection device with a vertical structure with low capacitance (which can be as low as 0.3 pF) can be obtained, and when the ESD protection device is packaged, by extracting the device cathode from the p+ substrate, grounding wire bonding during device packaging can be avoided, thereby reducing the packaging cost.
In an embodiment, based on the foregoing embodiment, the step of forming isolation trenches longitudinally penetrating the N-epi layer between the first n+ implantation region and the first p+ implantation region, and between the P well region and the second p+ isolation region, respectively, includes:
deep grooves longitudinally penetrating through the N-epitaxial layer are formed between the first N+ injection region and the first P+ injection region and between the P well region and the second P+ isolation region respectively;
filling isolation medium into the two deep grooves until an isolation layer with a preset thickness is formed on the N-epitaxial layer, so that the deep grooves form isolation grooves, wherein the preset thickness is 2-3.5 mu m;
and removing the isolation layer.
In this embodiment, after deep trenches longitudinally penetrating through the N-epi layer 102 are formed between the first n+ implantation region 106 and the first p+ implantation region 107, and between the P well region 105 and the second p+ isolation region 104, isolation medium is filled into the two deep trenches simultaneously, and overfilling of the isolation medium is performed until the isolation medium fills the two deep trenches and overflows, and the overflowed portion forms an isolation layer with a preset thickness above the N-epi layer 102, so that the isolation medium in the two obtained isolation trenches 111 can be filled tightly.
Wherein the preset thickness is 2-3.5 μm.
The spacer over N-epi layer 102 is then removed (i.e., the spacer over N-epi layer 102 is finally removed).
In an embodiment, referring to fig. 8, after the step of forming isolation trenches longitudinally penetrating the N-epi layer between the first n+ implantation region and the first p+ implantation region and between the P well region and the second p+ isolation region, the method further includes:
and forming an oxide layer covering the N-epitaxial layer, the first P+ isolation region, the second N+ injection region and the upper surface of the isolation groove on the N-epitaxial layer.
Wherein, an oxide layer 112 is formed on the N-epi layer 102 at one time, and then corresponding contact holes are formed on the oxide layer 112 above the first n+ implantation region 106, the first p+ implantation region 107, the P-well region 105, the second p+ implantation region 109, the third n+ implantation region 110 and the second p+ isolation region 104 by photolithography and etching methods, so that the formed oxide layer 112 cannot completely cover the upper surfaces of the first n+ implantation region 106, the first p+ implantation region 107, the P-well region 105, the second p+ implantation region 109, the third n+ implantation region 110 and the second p+ isolation region 104, and the remaining portions of the oxide layer 112 completely cover the upper surfaces of the N-epi layer 102, the first p+ isolation region 103, the second n+ implantation region 108 and the isolation trench 111.
In an embodiment, referring to fig. 8, after the step of forming an oxide layer on the N-epi layer to cover the N-epi layer, the first p+ isolation region, the second n+ implantation region and the upper surface of the isolation trench, the method further includes:
forming a first metal layer on the second P+ injection region, the third N+ injection region and the second P+ isolation region so as to electrically connect the second P+ injection region, the third N+ injection region and the second P+ isolation region;
and forming a second metal layer on the first N+ implantation region and the first P+ implantation region to connect the first N+ implantation region and the first P+ implantation region.
In this embodiment, in order to facilitate manufacturing of the electrode and the conductive line above the ESD protection device, a metal layer may be formed above the oxide layer 112 by evaporation or sputtering, and then divided into a first metal layer 113 and a second metal layer 114 by photolithography and etching, where the first metal layer 113 is formed to connect the second p+ implantation region 109, the third n+ implantation region 110 and the second p+ isolation region 104, so that the second p+ implantation region 109, the third n+ implantation region 110 and the second p+ isolation region 104 are electrically connected (i.e. the first metal layer 113 is used to replace the electrode for connecting the second p+ implantation region 109, the third n+ implantation region 110 and the second p+ isolation region 104); the second metal layer 114 is formed to connect the first n+ implant region 106 and the first p+ implant region 107 and serve as an anode I/O of the ESD protection device (i.e., the second metal layer 114 is used instead of the corresponding electrode).
Alternatively, the thickness of the metal layer may be greater than the thickness of the oxide layer 112.
Alternatively, the metal layer may be made of a metal having good conductivity such as aluminum or copper, and preferably aluminum is used.
Optionally, a passivation layer (not shown) is formed on the first and second metal layers 113 and 114 in order to protect the metal layers.
In order to facilitate the anodic I/O connection of the ESD protection device, a via may be fabricated in the passivation layer above the second metal layer 114 by photolithography and etching, and a pad may be formed as a reserved connection point (i.e., a contact point corresponding to the anodic I/O).
Alternatively, the passivation layer may have a thickness of 0.5 μm to 2 μm, preferably 1 μm; the passivation layer can be made of Si 3 N 4 。
In addition, based on the manufacturing and forming of the ESD protection device, the back gold thinning treatment (only the degree of reduction is ensured not to influence the normal operation of the ESD protection device) can be performed to a certain degree, so that the size of the device is further reduced.
The application further provides an ESD protection device, which is prepared by the preparation method of the ESD protection device in the embodiment; because the ESD protection device adopts all the technical solutions of all the embodiments, at least all the technical effects brought by the technical solutions of the embodiments are provided, and will not be described in detail herein.
In summary, in order to provide the manufacturing method of the ESD protection device and the ESD protection device in the embodiments of the application, by manufacturing the ESD protection device that can use the p+ substrate as the cathode, that is, without manufacturing the cathode from the upper surface layer of the ESD protection device, the manufacturing size of the device can be reduced under the condition of maintaining the current capacity of the device, the device packaging requirement of smaller volume can be satisfied, the large flyback ESD protection device with a low capacitance and a vertical structure can be obtained, and when the ESD protection device is packaged, the cathode of the device is led out from the p+ substrate, so that grounding wire bonding during packaging of the device can be avoided, thereby reducing the packaging cost.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, apparatus, article, or method. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, apparatus, article or method that comprises the element.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the scope of the application, and all equivalent structures or equivalent processes using the descriptions and drawings of the present application or direct or indirect application in other related technical fields are included in the scope of the present application.
Claims (10)
1. A method of manufacturing an ESD protection device comprising:
providing a P+ substrate, forming a P-epitaxial layer on the P+ substrate, and forming an N-epitaxial layer on the P-epitaxial layer;
forming two P+ isolation regions which longitudinally penetrate through the N-epitaxial layer, wherein the two P+ isolation regions are a first P+ isolation region and a second P+ isolation region respectively;
forming a P well region in the N-epitaxial layer between the first P+ isolation region and the second P+ isolation region;
forming a first n+ injection region and a first p+ injection region within the N-epitaxial layer between the first p+ isolation region and the P-well region, and forming a second n+ injection region at a boundary crossing between the N-epitaxial layer and the P-well region, and forming a second p+ injection region and a third n+ injection region within the P-well region; the first P+ injection region is arranged between the first N+ injection region and the P well region; the second P+ injection region is arranged between the second N+ injection region and the third N+ injection region, and the third N+ injection region is arranged between the second P+ injection region and the second P+ isolation region;
forming isolation trenches longitudinally penetrating the N-epitaxial layer between the first N+ injection region and the first P+ injection region and between the P well region and the second P+ isolation region respectively;
wherein the cathode of the ESD protection device is fabricated based on the p+ substrate.
2. The method of manufacturing an ESD protection device according to claim 1, further comprising:
the annealing temperature in the P+ isolation region forming process is 1200-1250 ℃, and the annealing time is 1-2 hours.
3. The method of manufacturing an ESD protection device according to claim 1, further comprising:
the annealing temperature in the P well region forming process is 1000-2000 ℃ and the annealing time is 2-3 hours.
4. The method of manufacturing an ESD protection device according to claim 1, further comprising:
in the process of forming the first P+ injection region and the second P+ injection region, the injected P+ dose is 1.0E15/cm & lt- & gt 1.0E16/cm;
and in the process of forming the first N+ injection region, the second N+ injection region and the third N+ injection region, the injected N+ dose is 1.0E15/cm-1.0E16/cm.
5. The method of manufacturing an ESD protection device according to claim 1 or 4, further comprising:
in the process of forming a first N+ injection region, a first P+ injection region, a second N+ injection region, a second P+ injection region and a third N+ injection region, a first annealing process and a second annealing process are carried out, wherein the annealing temperature of the first annealing process is 1100-1200 ℃ and the annealing time is 10-20 seconds; the annealing temperature of the second annealing process is 800-900 ℃ and the annealing time is 30-60 minutes.
6. The method of claim 1, wherein the step of forming isolation trenches longitudinally penetrating the N-epi layer between the first n+ implant region and the first p+ implant region, and between the P well region and the second p+ isolation region, respectively, comprises:
deep grooves longitudinally penetrating through the N-epitaxial layer are formed between the first N+ injection region and the first P+ injection region and between the P well region and the second P+ isolation region respectively;
filling isolation medium into the two deep grooves until an isolation layer with a preset thickness is formed on the N-epitaxial layer, so that the deep grooves form isolation grooves, wherein the preset thickness is 2-3.5 mu m;
and removing the isolation layer.
7. The method of manufacturing an ESD protection device according to claim 1 or 6, wherein after the step of forming isolation trenches longitudinally penetrating the N-epitaxial layer between the first n+ implantation region and the first p+ implantation region and between the P well region and the second p+ isolation region, respectively, further comprises:
and forming an oxide layer covering the N-epitaxial layer, the first P+ isolation region, the second N+ injection region and the upper surface of the isolation groove on the N-epitaxial layer.
8. The method of manufacturing an ESD protection device of claim 7, wherein after the step of forming an oxide layer on the N-epi layer covering the N-epi layer, the first p+ isolation region, the second n+ implant region, and the upper surface of the isolation trench, further comprising:
forming a first metal layer on the second P+ injection region, the third N+ injection region and the second P+ isolation region so as to electrically connect the second P+ injection region, the third N+ injection region and the second P+ isolation region;
and forming a second metal layer on the first N+ implantation region and the first P+ implantation region to connect the first N+ implantation region and the first P+ implantation region.
9. The method of manufacturing an ESD protection device of claim 8, further comprising:
and forming passivation layers on the first metal layer and the second metal layer, wherein wiring points are reserved in the passivation layer above the second metal layer.
10. An ESD protection device, characterized in that the ESD protection device is manufactured using the manufacturing method of the ESD protection device according to any one of claims 1-9.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6777721B1 (en) * | 2002-11-14 | 2004-08-17 | Altera Corporation | SCR device for ESD protection |
| KR20090088683A (en) * | 2008-02-15 | 2009-08-20 | 주식회사 하이닉스반도체 | Thyristor and method for manufacturing the same |
| CN102157519A (en) * | 2011-01-28 | 2011-08-17 | 上海宏力半导体制造有限公司 | Silicon controlled rectifier |
| CN103165600A (en) * | 2013-02-26 | 2013-06-19 | 北京时代民芯科技有限公司 | Electro-static discharge (ESD) protective circuit |
| CN109273521A (en) * | 2018-09-04 | 2019-01-25 | 深圳市福来过科技有限公司 | A kind of power device protection chip and preparation method thereof |
| CN112420691A (en) * | 2020-11-26 | 2021-02-26 | 重庆广播电视大学重庆工商职业学院 | Distributed ESD device with embedded SCR structure |
| CN113140627A (en) * | 2021-04-08 | 2021-07-20 | 上海维安半导体有限公司 | SCR device with low trigger voltage and preparation method thereof |
| CN113725810A (en) * | 2021-08-27 | 2021-11-30 | 深圳市槟城电子股份有限公司 | Protection circuit and circuit protection device |
| CN114664817A (en) * | 2022-03-07 | 2022-06-24 | 杭州士兰集昕微电子有限公司 | Transient voltage suppression device and method of manufacturing the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040207020A1 (en) * | 1999-09-14 | 2004-10-21 | Shiao-Chien Chen | CMOS silicon-control-rectifier (SCR) structure for electrostatic discharge (ESD) protection |
| EP3553822B1 (en) * | 2018-04-09 | 2021-02-24 | NXP USA, Inc. | Esd protection device, semiconductor device that includes an esd protection device, and method of manufacturing same |
| JP6937281B2 (en) * | 2018-09-14 | 2021-09-22 | 株式会社東芝 | Semiconductor device |
-
2023
- 2023-07-25 CN CN202310911903.4A patent/CN116632003B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6777721B1 (en) * | 2002-11-14 | 2004-08-17 | Altera Corporation | SCR device for ESD protection |
| KR20090088683A (en) * | 2008-02-15 | 2009-08-20 | 주식회사 하이닉스반도체 | Thyristor and method for manufacturing the same |
| CN102157519A (en) * | 2011-01-28 | 2011-08-17 | 上海宏力半导体制造有限公司 | Silicon controlled rectifier |
| CN103165600A (en) * | 2013-02-26 | 2013-06-19 | 北京时代民芯科技有限公司 | Electro-static discharge (ESD) protective circuit |
| CN109273521A (en) * | 2018-09-04 | 2019-01-25 | 深圳市福来过科技有限公司 | A kind of power device protection chip and preparation method thereof |
| CN112420691A (en) * | 2020-11-26 | 2021-02-26 | 重庆广播电视大学重庆工商职业学院 | Distributed ESD device with embedded SCR structure |
| CN113140627A (en) * | 2021-04-08 | 2021-07-20 | 上海维安半导体有限公司 | SCR device with low trigger voltage and preparation method thereof |
| CN113725810A (en) * | 2021-08-27 | 2021-11-30 | 深圳市槟城电子股份有限公司 | Protection circuit and circuit protection device |
| CN114664817A (en) * | 2022-03-07 | 2022-06-24 | 杭州士兰集昕微电子有限公司 | Transient voltage suppression device and method of manufacturing the same |
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|---|---|
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