CN220382100U - ESD protection device and chip circuit - Google Patents
ESD protection device and chip circuit Download PDFInfo
- Publication number
- CN220382100U CN220382100U CN202321955546.3U CN202321955546U CN220382100U CN 220382100 U CN220382100 U CN 220382100U CN 202321955546 U CN202321955546 U CN 202321955546U CN 220382100 U CN220382100 U CN 220382100U
- Authority
- CN
- China
- Prior art keywords
- region
- esd protection
- protection device
- isolation
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002955 isolation Methods 0.000 claims abstract description 71
- 238000002347 injection Methods 0.000 claims abstract description 66
- 239000007924 injection Substances 0.000 claims abstract description 66
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 230000000149 penetrating effect Effects 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 239000007943 implant Substances 0.000 claims description 16
- 238000002161 passivation Methods 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 63
- 238000002513 implantation Methods 0.000 description 18
- 238000004806 packaging method and process Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000000243 solution Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The utility model relates to the semiconductor chip technology, and discloses an ESD protection device and a chip circuit, comprising: a P+ substrate, wherein a P-epitaxial layer is arranged on the P+ substrate, and an N-epitaxial layer is arranged on the P-epitaxial layer; the two P+ isolation regions longitudinally penetrate through the N-epitaxial layer, namely a first P+ isolation region and a second P+ isolation region; a first N+ injection region, a first P+ injection region, a second N+ injection region and a P well region are sequentially arranged in the N-epitaxial layer between the first P+ isolation region and the second P+ isolation region, and a second P+ injection region and a third N+ injection region are sequentially arranged in the P well region, wherein the second N+ injection region spans the boundary between the N-epitaxial layer and the P well region; isolation trenches longitudinally penetrating the N-epitaxial layer are respectively arranged between the first N+ injection region and the first P+ injection region and between the P well region and the second P+ isolation region. The present utility model aims to provide an ESD protection device satisfying a small-sized package.
Description
Technical Field
The present utility model relates to the field of semiconductor chip technologies, and in particular, to an ESD protection device and a chip circuit.
Background
Integrated circuit products are extremely susceptible to ESD (Electro-Static discharge) during their production, manufacture, assembly and operation, resulting in internal damage and reduced reliability. Therefore, research into high-performance and high-reliability ESD protection devices has a crucial role in improving yield and reliability of integrated circuits. Among them, SCR (Silicon Controlled Rectifier ) devices are commonly used to fabricate ESD protection devices.
At present, under the same line width, the lateral structure of the existing low-capacitance SCR device often needs to manufacture an ESD protection device with a larger size, because the anode and the cathode of the lateral structure are both manufactured on the upper surface of the device, the sizes of the anode and the cathode cannot be reduced to be smaller than 10um under the influence of packaging, and correspondingly larger devices are needed to be manufactured. If the device size is reduced by reducing the lateral structure, the area-related current passing capability of the SCR device is reduced, that is, the current large flyback ESD protection device with the low-capacitance SCR structure is difficult to realize in smaller device package.
The foregoing is provided merely for the purpose of facilitating understanding of the technical solutions of the present utility model and is not intended to represent an admission that the foregoing is prior art.
Disclosure of Invention
The utility model provides an ESD protection device and a chip circuit, and aims to provide an ESD protection device meeting the requirement of small-size packaging.
To achieve the above object, the present utility model proposes an ESD protection device comprising:
a P+ substrate, wherein a P-epitaxial layer is arranged on the P+ substrate, and an N-epitaxial layer is arranged on the P-epitaxial layer;
the two P+ isolation regions longitudinally penetrate through the N-epitaxial layer, namely a first P+ isolation region and a second P+ isolation region;
a first N+ injection region, a first P+ injection region, a second N+ injection region and a P well region are sequentially arranged in the N-epitaxial layer between the first P+ isolation region and the second P+ isolation region, and a second P+ injection region and a third N+ injection region are sequentially arranged in the P well region, wherein the second N+ injection region spans the boundary between the N-epitaxial layer and the P well region;
isolation trenches longitudinally penetrating the N-epitaxial layer are respectively arranged between the first N+ injection region and the first P+ injection region and between the P well region and the second P+ isolation region.
Optionally, the ESD protection device further includes:
and an oxide layer covering the N-epitaxial layer, the first P+ isolation region, the second N+ injection region and the upper surface of the isolation groove is also arranged on the N-epitaxial layer.
Optionally, the ESD protection device further includes an electrode connecting the first n+ injection region and the first p+ injection region as an anode of the ESD protection device;
and the electrode led out from the P+ substrate is used as a cathode of the ESD protection device.
Optionally, a first metal layer is disposed on the second p+ injection region, the third n+ injection region and the second p+ isolation region, so that the second p+ injection region, the third n+ injection region and the second p+ isolation region are electrically connected;
and a second metal layer which connects the first N+ injection region and the first P+ injection region is arranged on the first N+ injection region and the first P+ injection region and is used as an anode of the ESD protection device.
Optionally, passivation layers are disposed on the first metal layer and the second metal layer.
Optionally, junction depths of the first n+ injection region, the first p+ injection region, the second n+ injection region, the second p+ injection region, and the third n+ injection region are smaller than junction depths of the P well region.
Optionally, the thickness of the P-epitaxial layer is 6-14 μm, and/or the thickness of the N-epitaxial layer is 6-12 μm.
Optionally, the depth of the isolation groove is 10-20 μm, and/or the width of the isolation groove is 1.5-3 μm.
The utility model further proposes a chip circuit comprising a chip, and an ESD protection device as described above; wherein the chip is grounded via the ESD protection device.
The technical scheme of the utility model has the beneficial effects that: by providing an ESD protection device using a p+ substrate as a grounded cathode without fabricating a cathode from an upper surface layer of the ESD protection device, the fabrication size of the device can be reduced while maintaining the device current capacity, the device packaging requirement of smaller volume can be satisfied, and when the ESD protection device is packaged, grounding wire bonding during device packaging can be avoided by extracting the device cathode from the p+ substrate 100, thereby reducing the packaging cost.
Drawings
Fig. 1 is a schematic structural diagram of an ESD protection device according to an embodiment of the present utility model;
fig. 2 is a schematic structural diagram of another embodiment of the ESD protection device of the present utility model;
fig. 3 is an equivalent circuit diagram of the ESD protection device of the present utility model;
fig. 4 is a schematic structural diagram of an ESD protection device according to another embodiment of the utility model;
fig. 5 is a schematic diagram of a chip circuit according to an embodiment of the utility model.
The achievement of the objects, functional features and advantages of the present utility model will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
The following description of the embodiments of the present utility model will be made more clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present utility model are merely used to explain the relative positional relationship, movement conditions, etc. between the components in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicators are correspondingly changed.
It will also be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only (e.g., to distinguish between identical or similar elements) and is not to be construed as indicating or implying a relative importance or an implicit indication of the number of features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present utility model.
The utility model proposes an ESD protection device, referring to figure 1, the ESD protection device comprises a P+ substrate 100, a P-epitaxial layer 101 is arranged on the P+ substrate 100, and an N-epitaxial layer 102 is arranged on the P-epitaxial layer 101; two P+ isolation regions penetrating the N-epitaxial layer 102 longitudinally are a first P+ isolation region 103 and a second P+ isolation region 104 respectively; a first n+ injection region 106, a first p+ injection region 107, a second n+ injection region 108 and a P-well region 105 are sequentially arranged in the N-epitaxial layer 102 between the first p+ isolation region 103 and the second p+ isolation region 104, and a second p+ injection region 109 and a third n+ injection region 110 are sequentially arranged in the P-well region 105, wherein the second n+ injection region 108 spans the boundary between the N-epitaxial layer 102 and the P-well region 105 (i.e. a second n+ injection region 108 spans the boundary between the left side of the P-well region 105 and the N-epitaxial layer 102); isolation trenches 111 penetrating the N-epitaxial layer 102 longitudinally are provided between the first n+ implant region 106 and the first p+ implant region 107, and between the P-well region 105 and the second p+ isolation region 104, respectively.
Optionally, the junction depths of the first n+ implantation region 106, the first p+ implantation region 107, the second n+ implantation region 108, the second p+ implantation region 109, and the third n+ implantation region 110 are smaller than the junction depth of the P well region 105.
Optionally, the isolation medium filled in the isolation groove 111 may be polycrystalline or silicon dioxide; preferably, the polycrystalline is filled.
In this way, the p+ substrate 100 of the ESD protection device provided by the present application can be used as a grounded cathode (in order to facilitate the wiring of the ESD protection device, the corresponding electrode can be led out of the p+ substrate 100), without manufacturing the cathode from the upper surface layer of the ESD protection device, so that the manufacturing size of the device (the allowable size can be 220 μm) can be reduced under the condition of maintaining the device current capacity, the device packaging requirement with smaller volume can be met, and when the ESD protection device is packaged, the grounded wiring during the device packaging can be avoided by leading out the device cathode from the p+ substrate 100, thereby reducing the packaging cost.
Further, the first n+ injection region 106 and the first p+ injection region 107 are used as anodes of the ESD protection device, and by extracting electrodes connecting the two above the first n+ injection region 106 and the first p+ injection region 107, wiring when the ESD protection device is used can be facilitated.
Optionally, referring to fig. 2 (dashed lines in the drawing indicate wires equivalently replacing corresponding electrodes, that is, indicate corresponding connection modes), the ESD protection device further includes an electrode connecting the first n+ injection region 106 and the first p+ injection region 107 as an anode I/O of the ESD protection device;
and an electrode led out of the p+ substrate 100 serves as a cathode GND of the ESD protection device.
In addition, corresponding electrodes may be disposed above the second p+ implantation region 109, the third n+ implantation region 110 and the second p+ isolation region 104 to connect the three, so that the second p+ implantation region 109, the third n+ implantation region 110 and the second p+ isolation region 104 are electrically connected.
Thus, the ESD protection device formed based on this has an equivalent circuit diagram as shown in fig. 3: the P-epitaxial layer 101 and the N-epitaxial layer 102 function as diodes, the second p+ isolation region 104 functions as a resistor, and the first n+ implant region 106, the first p+ implant region 107, the second n+ implant region 108, the second p+ implant region 109, the third n+ implant region 110, the P well region 105, and the N-epitaxial layer 102 may together function as an SCR structure (i.e., equivalent to an SCR structure composed of a first transistor and a second transistor).
Alternatively, the resistivity of the P+ substrate 100 is 0.0005 Ω -cm to 0.0008 Ω -cm.
Optionally, the thickness of the P-epitaxial layer 101 is 6 μm to 14 μm, and the resistivity is 2 Ω cm to 4 Ω cm.
Optionally, the thickness of the N-epitaxial layer 102 is 6 μm to 12 μm, and the resistivity is 45 Ω·cm to 55 Ω·cm, optionally 50 Ω·cm.
Optionally, the depth of the isolation trench 111 is 10 μm to 20 μm, and/or the width of the isolation trench 111 is 1.5 μm to 3 μm. Where the depth of the isolation trenches 111 is ensured to be greater than the thickness of the N-epi layer 102 (i.e., the isolation trenches 111 penetrate the N-epi layer 102 longitudinally, i.e., the regions between the isolation trenches 111 are ensured to be unaffected by each other and to perform isolation), the isolation trenches 111 may or may not further penetrate the P-epi layer 101.
In addition, the depth of the first p+ isolation region 103/second p+ isolation region 104 is greater than the thickness of the N-epitaxial layer 102. Where the depth of the first p+ isolation region 103/second p+ isolation region 104 is ensured to be greater than the thickness of the N-epitaxial layer 102 (i.e., the first p+ isolation region 103/second p+ isolation region 104 penetrates longitudinally through the N-epitaxial layer 102, the first p+ isolation region 103/second p+ isolation region 104 may or may not further penetrate the P-epitaxial layer 101.) preferably, the first p+ isolation region 103/second p+ isolation region 104 is formed to penetrate longitudinally through the N-epitaxial layer 102 and the P-epitaxial layer 101 (i.e., the depth of the first p+ isolation region 103/second p+ isolation region 104 may be greater than or equal to the sum of the thicknesses of the N-epitaxial layer 102 and the P-epitaxial layer 101).
Thus, a vertical structure large flyback ESD protection device with low capacitance (which may be as low as 0.3 pF) can be formed.
In an embodiment, referring to fig. 4, an oxide layer 112 covering the N-epi layer 102, the first p+ isolation region 103, the second n+ implantation region 108 and the upper surface of the isolation trench 111 is further provided on the N-epi layer 102 on the basis of the above embodiment.
In addition, in order to ensure that the oxide layer 112 has an oxidation isolation effect, the oxide layer 112 may also partially cover the upper surfaces of the first n+ implantation region 106, the first p+ implantation region 107, the P well region 105, the second p+ implantation region 109, the third n+ implantation region 110, and the second p+ isolation region 104.
Optionally, in order to facilitate the manufacture of an electrode above the ESD protection device, a first metal layer 113 is disposed on the second p+ injection region 109, the third n+ injection region 110 and the second p+ isolation region 104, and the first metal layer 113 is connected to the second p+ injection region 109, the third n+ injection region 110 and the second p+ isolation region 104, so that the second p+ injection region 109, the third n+ injection region 110 and the second p+ isolation region 104 are electrically connected; a second metal layer 114 is disposed on the first n+ implantation region 106 and the first p+ implantation region 107 to connect the first n+ implantation region 106 and the first p+ implantation region 107, and the wiring thereof can be used as an anode I/O of the ESD protection device.
In this way, by means of the metal layer, the corresponding electrode can be conveniently manufactured (the original first metal layer 113 and the second metal layer 114 can be integrally formed, and then the first metal layer and the second metal layer are cut through photoetching and etching).
Alternatively, the metal layer may be made of a metal having good conductivity such as aluminum or copper, and preferably aluminum is used.
Optionally, passivation layers (not shown) are provided on the first and second metal layers 113 and 114 in order to protect the metal layers. Wherein, a wiring through hole corresponding to the second metal layer 114 is disposed in the passivation layer above the second metal layer 114, and a corresponding pressure point is manufactured based on the wiring through hole to serve as a reserved anode I/O contact point.
Alternatively, the passivation layer may have a thickness of 0.5 μm to 2 μm, preferably 1 μm; the passivation layer can be made of Si 3 N 4 。
The present utility model further proposes a chip circuit, referring to fig. 5, the chip circuit includes a chip and an ESD protection device, and the specific structure of the ESD protection device refers to the above embodiment.
The chip is grounded through the ESD protection device, namely, the anode of the ESD protection device is electrically connected with the chip, and the cathode of the ESD protection device is grounded.
The chip is the chip which needs to be subjected to ESD protection.
The above description of the preferred embodiments of the present utility model should not be taken as limiting the scope of the utility model, but rather should be understood to cover all modifications, variations and adaptations of the present utility model using its general principles and the following detailed description and the accompanying drawings, or the direct/indirect application of the present utility model to other relevant arts and technologies.
Claims (9)
1. An ESD protection device, comprising:
a P+ substrate, wherein a P-epitaxial layer is arranged on the P+ substrate, and an N-epitaxial layer is arranged on the P-epitaxial layer;
the two P+ isolation regions longitudinally penetrate through the N-epitaxial layer, namely a first P+ isolation region and a second P+ isolation region;
a first N+ injection region, a first P+ injection region, a second N+ injection region and a P well region are sequentially arranged in the N-epitaxial layer between the first P+ isolation region and the second P+ isolation region, and a second P+ injection region and a third N+ injection region are sequentially arranged in the P well region, wherein the second N+ injection region spans the boundary between the N-epitaxial layer and the P well region;
isolation trenches longitudinally penetrating the N-epitaxial layer are respectively arranged between the first N+ injection region and the first P+ injection region and between the P well region and the second P+ isolation region.
2. The ESD protection device of claim 1, further comprising:
and an oxide layer covering the N-epitaxial layer, the first P+ isolation region, the second N+ injection region and the upper surface of the isolation groove is also arranged on the N-epitaxial layer.
3. The ESD protection device of claim 1 or 2, further comprising an electrode connecting the first n+ injection region and the first p+ injection region as an anode of the ESD protection device;
and the electrode led out from the P+ substrate is used as a cathode of the ESD protection device.
4. The ESD protection device of claim 3 wherein a first metal layer is disposed on the second p+ implant region, the third n+ implant region, and the second p+ isolation region to electrically connect the second p+ implant region, the third n+ implant region, and the second p+ isolation region;
and a second metal layer which connects the first N+ injection region and the first P+ injection region is arranged on the first N+ injection region and the first P+ injection region and is used as an anode of the ESD protection device.
5. The ESD protection device of claim 4, wherein a passivation layer is disposed over the first metal layer and the second metal layer.
6. The ESD protection device of claim 1, wherein junction depths of the first n+ implant region, the first p+ implant region, the second n+ implant region, the second p+ implant region, and the third n+ implant region are each less than a junction depth of the P-well region.
7. The ESD protection device of claim 1, wherein the P-epitaxial layer has a thickness of 6-14 μιη and/or the N-epitaxial layer has a thickness of 6-12 μιη.
8. The ESD protection device according to claim 1 or 7, wherein the depth of the isolation trench is 10-20 μm and/or the width of the isolation trench is 1.5-3 μm.
9. A chip circuit comprising a chip and an ESD protection device as claimed in any one of claims 1 to 8; wherein the chip is grounded via the ESD protection device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321955546.3U CN220382100U (en) | 2023-07-25 | 2023-07-25 | ESD protection device and chip circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321955546.3U CN220382100U (en) | 2023-07-25 | 2023-07-25 | ESD protection device and chip circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220382100U true CN220382100U (en) | 2024-01-23 |
Family
ID=89559566
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321955546.3U Active CN220382100U (en) | 2023-07-25 | 2023-07-25 | ESD protection device and chip circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220382100U (en) |
-
2023
- 2023-07-25 CN CN202321955546.3U patent/CN220382100U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9570603B2 (en) | Semiconductor device having trench gate structure and method for manufacturing the semiconductor device | |
| US8004036B2 (en) | MOSFET-Schottky rectifier-diode integrated circuits with trench contact structures for device shrinkage and performance improvement | |
| TWI414082B (en) | Luminous diode chip with overvoltage protection | |
| US8896108B2 (en) | Semiconductor device with parasitic bipolar transistor | |
| JP2011165860A (en) | Protective element and semiconductor device | |
| CN106158851B (en) | Bidirectional ultra-low capacitance transient voltage suppressor and manufacturing method thereof | |
| CN220382100U (en) | ESD protection device and chip circuit | |
| JP6923303B2 (en) | Diode element | |
| US11978793B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
| CN115692488A (en) | Semiconductor device and method for manufacturing the same | |
| CN105185783B (en) | Capacitive diode assembly and its manufacturing method | |
| CN108321157B (en) | SCR transient voltage suppressor with low capacitance and low clamping voltage and manufacturing method | |
| CN114121946A (en) | Semiconductor integrated chip and IGBT module | |
| CN116632003B (en) | Preparation method of ESD protection device and ESD protection device | |
| JP2892686B2 (en) | Insulated gate semiconductor device | |
| US9659888B2 (en) | Semiconductor device | |
| US7560800B1 (en) | Die seal with reduced noise coupling | |
| CN214313218U (en) | Ultra-low dynamic impedance bidirectional TVS | |
| US20220392815A1 (en) | Semiconductor device | |
| JP2664911B2 (en) | Semiconductor device | |
| JP2020013900A (en) | Semiconductor device | |
| WO2023090137A1 (en) | Semiconductor element and semiconductor device | |
| EP3958325A1 (en) | Semiconductor device | |
| CN214336713U (en) | Semiconductor device with a plurality of transistors | |
| CN106449372A (en) | Manufacturing method for MIM (metal-insulator-metal) capacitor structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |