JP4687024B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a power MISFET as a protected element and a pn-junction protective diode as an electrostatic protection element, and more particularly to a semiconductor device having a high ESD (Electro Static Discharge) resistance.

Conventionally, a pn-junction protective diode as shown in FIG. 26 is connected in parallel between the drain and source electrodes of a MISFET (Metal-Insulator-Semiconductor Field Effect Transistor) or between the gate and source electrodes, and is destroyed by an overvoltage such as an ESD surge. A method for preventing this is known (Patent Document 1, Patent Document 2).
In this case, even when a high ESD surge is applied between the drain and source or between the gate and source by connecting the protection diode 112 having a breakdown voltage lower than the drain-source breakdown voltage or the gate-source breakdown voltage of the MISFET 113. The protection diode 112 first enters the avalanche to prevent a current from flowing through the protection diode 112 to prevent a high voltage from being applied between the drain and the source or between the gate and the source, and prevents the MISFET 113 from being destroyed by the ESD surge. can do.

On the other hand, in this method, the n region 104 of FIG. 26 is formed as the cathode region of the protection diode 112. However, since the diffusion depth of the n region 104 is deep, the operating resistance increases.
FIG. 27 is a diagram illustrating IV characteristics of two protection diodes having different operating resistances. I on the vertical axis is the avalanche current, and V on the horizontal axis is the voltage applied to the protection diode.
When the protection diode is connected in parallel between the drain and source of the MISFET, the voltage applied between the cathode and the anode of the protection diode reaches the avalanche voltage V1 when the operating resistance is high IV characteristics (1). Even after the avalanche current flows, the voltage applied between the cathode and anode of the protection diode increases as the avalanche current increases. When this voltage exceeds the drain-source breakdown voltage (V2 in FIG. 27) of the MISFET, current begins to flow between the drain and source. For this reason, when the operating resistance of the protection diode is high, it becomes difficult to protect the MISFET against a high voltage ESD surge.

As a countermeasure, it is effective to lower the operating resistance of the protection diode. In the case of the IV characteristic (2) of the protection diode having a low operating resistance in FIG. 27, it can be seen that the voltage applied to the protection diode can be kept low even when the current flowing through the protection diode is the same as compared with the case where the operation resistance is high. There are two methods for reducing the operating resistance of the protection diode.
(1) Increase the active area of the protection diode.
(2) Lowering the resistance of the cathode region (n region).
The method (1) is effective in reducing the operating resistance, but it is not preferable because it increases the chip area.
In the method (2), it is effective to increase the concentration of the cathode region deeply. Further, increasing the concentration of the cathode region deeply is also effective for setting the avalanche voltage of the protection diode lower than the avalanche voltage of the MISFET.

However, when the high temperature heat treatment is performed for a long time in order to increase the concentration of the cathode region deeply, the width of the p layer formed by the p impurity exudation from the high concentration p ⁺ substrate to the p epitaxial layer increases. Since the electrical characteristics (breakdown voltage characteristics, etc.) of devices such as MISFETs formed on the surface side of the wafer are adversely affected, there is a limit to lowering the operating resistance of the cathode region.
As a method for solving this, in order to further reduce the resistance of the protection diode, a trench is dug from the surface of the p epitaxial layer, the protection diode is formed at the bottom of the trench, and a low resistance conductive film such as metal is used to form the bottom of the trench. A method of making ohmic contact with the cathode region is disclosed (Patent Document 3).
FIG. 28 is a fragmentary cross-sectional view of a conventional semiconductor device having a protective diode having a trench structure.

The protection diode 112 is formed by forming an n region 104 as a cathode region and an n ⁺ region 118 as a contact portion at the bottom of the trench 119 and making ohmic contact between the cathode region and the conductive film 115 through the n ⁺ region 118. The
In the figure, 101 is a p ⁺ substrate, 102 is a p layer diffused from the p ⁺ substrate, 103 is a p epitaxial layer, 105 is an n well region, 106 is a p well region, 107 is a LOCOS oxide film, and 108 is an n source. An n ⁺ region that becomes an n drain region, 109 is a p ⁺ region that becomes a contact region, and 111 is a back electrode.
By the way, if the ESD tolerance required for the MISFET 113 is low, the active area of the protection diode 112 may be small. However, if a high ESD tolerance is required, the area of the active portion of the protection diode 112 is increased, and It is necessary to reduce the avalanche current density to prevent destruction. In this case, the protection diode 112 is formed under the drain electrode pad for the purpose of reducing the chip area.

29A and 29B are views of a trench having a wide width and a shallow depth. FIG. 29A is a plan view of the main part, and FIG. 29B is a main part cut along the line XX of FIG. The cross-sectional view and FIG. 4C are cross-sectional views of the main part when the conductive film is formed.
When forming a protection diode having a large area, even if the width of the trench 119 is wide as shown in FIGS. 29A and 29B, if the depth of the trench 119 is as shallow as about 1 μm, FIG. As shown in FIG. 6, since the conductive film 115 for making contact can fill the trench 119 in a normal process, the protective diode 112 can be formed at the bottom of one wide trench 119.
In the case of a high breakdown voltage MISFET, the thickness of the p epitaxial layer 103 is 10 μm or more, and therefore the depth of the trench 119 is 5 μm or more. In the case of a trench having a depth as deep as 5 μm or more and a width as wide as 10 μm or more, the thickness of the conductive film 115 that can be embedded in the trench 119 is limited to about 1 μm. The surface height of the conductive film 115 filling the trench 119 cannot be increased up to the surface height of the p epitaxial layer 103. Thus, when the trench 119 is imperfectly filled with the conductive film 115, the surface height of the conductive film 115 filling the trench 119 is lower than the surface height of the p epitaxial layer 103 not forming the trench 119, A large step is formed on the wafer surface. If there is a large step, there is a possibility that the photoresist cannot be applied to the entire surface of the wafer in the subsequent process, or a resist residue may be generated in the trench 119.
JP-A-57-35374 Japanese Patent No. 3090081 Japanese Patent Laid-Open No. 8-32057

  An object of the present invention is to solve the above-described problems and provide a semiconductor device having an electrostatic protection element with high ESD resistance.

In order to achieve the above-mentioned object, a protected element and a protection diode that protects the protected element from overvoltage are connected, and a cathode of the protection diode is connected to a high potential side of the protected element, In the semiconductor device formed by connecting the anode of the protective diode to the low potential side of the protected element, a semiconductor substrate of the first conductivity type, a trench formed from the surface of the semiconductor substrate toward the inside, A first conductive region of a second conductivity type formed inside the semiconductor substrate at the bottom of the trench; and the protection diode having a pn junction formed by the semiconductor substrate and the first semiconductor region. The planar shape of the opening is a loop shape.
And a protection diode that protects the protection element from overvoltage, the cathode of the protection diode and the high potential side of the protection element are connected, and the anode of the protection diode is connected to the protection diode. In a semiconductor device formed by connecting to a low potential side of a protection element, a semiconductor substrate of a first conductivity type, a semiconductor layer formed on the semiconductor substrate via an insulating layer, and the surface of the semiconductor layer from the surface A trench reaching the semiconductor substrate through an insulating layer, a first semiconductor region of a second conductivity type formed inside the semiconductor substrate at the bottom of the trench, and the semiconductor substrate and the first semiconductor region The protection diode having a pn junction is provided, and the planar shape of the opening of the trench is a loop.

And a protection diode that protects the protection element from overvoltage, the cathode of the protection diode and the high potential side of the protection element are connected, and the anode of the protection diode is connected to the protection diode. In a semiconductor device formed by being connected to a low potential side of a protective element, a semiconductor substrate of a first conductivity type, a trench formed from the surface of the semiconductor substrate toward the inside, and the semiconductor substrate at the bottom of the trench And a protective diode having a pn junction formed by the semiconductor substrate and the second semiconductor region, and the planar shape of the opening of the trench is a loop. It is set as a structure.
And a protection diode that protects the protection element from overvoltage, the cathode of the protection diode and the high potential side of the protection element are connected, and the anode of the protection diode is connected to the protection diode. In a semiconductor device formed by connecting to a low potential side of a protection element, a semiconductor substrate of a first conductivity type, a semiconductor layer formed on the semiconductor substrate via an insulating layer, and the surface of the semiconductor layer from the surface A trench reaching the semiconductor substrate through an insulating layer, a second conductivity type second semiconductor region formed on the semiconductor substrate at the bottom of the trench, and the semiconductor substrate and the second semiconductor region The protection diode having a pn junction is provided, and the planar shape of the opening of the trench is a loop.

A plurality of the loop-shaped trenches may be formed.
Further, it is preferable the second semiconductor region is an epitaxial growth layer.
Moreover, it is good to have the said trench and the electrically conductive film which carries out the ohmic contact with the said 1st or 2nd semiconductor region formed in the said trench.
The protection diode may be formed under the electrode pad of the protected element .

According to the present invention, it is possible to provide a semiconductor device applicable even when a high ESD tolerance is required by forming a protection diode by forming a plurality of trenches and embedding a conductive film. Further, by making the trench into a continuous loop shape, electric field concentration that has been easy to occur at the bottom of the trench at the end of the trench can be suppressed, and a semiconductor device having high ESD tolerance can be formed .

  In the best mode of implementation, in order to form a plurality of trenches and improve the ESD resistance, the trench is not looped and the planar shape of the trench is looped. Also, the radius of curvature of this loop is increased. Further, by forming the protective diode in the lateral trench MISFET, the occupied area is reduced, and the ESD resistance is improved. Hereinafter, description will be made using examples.

FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment of the present invention. A p epitaxial layer 3 is formed on a high concentration p ⁺ substrate 1, and a p layer 2 formed by impurities diffused from the p ⁺ substrate 1 toward the p epitaxial layer 3 by the heat treatment in the wafer process is expressed as p ⁺ It is formed between the substrate 1 and the p epitaxial layer 3.
In this embodiment, a vertical protection diode 17 having a trench structure for protecting a lateral n-MISFET 15 having a trench structure is shown. In the n-MISFET 15, an n drain region (n ⁺ region 8 and n region 6) is formed at the bottom of the trench, an n source region (n ⁺ region 8) is formed on the wafer surface, and a gate oxide film 20 is formed on the sidewall of the trench 19. A gate electrode 21 is formed on the gate oxide film 20.
An n region 7 is formed as a cathode region of the protection diode 17 that protects the n-MISFET 15. The n region 7 is in contact with the bottom surface of the trench to make ohmic contact between the n region 7 and a metal film 23 such as tungsten embedded in the trench 19. Thus, an n ⁺ region 8 is formed. An n region 7 is formed around the n ⁺ region 8, and the n region 7 and the p layer 2 diffused from the p ⁺ substrate 1 are in contact with each other to form a pn junction of the protective diode 17.

Note that the n region 7 and the p layer 2 are not necessarily in contact with each other. Also, as shown in FIG. 1, when the n regions 7 are connected to each other in the lateral direction, the area of the cathode region (n region 7) is increased, and the operating resistance can be reduced. However, it is not always necessary to connect them.
In the protection diode 17, the n region 7 that functions as a cathode is formed at the bottom of the trench 19, and the n region 7 is connected to the metal film 23 through the n ⁺ region 8, and therefore the trench 19 is not formed. Compared with, the operating resistance can be reduced and the ESD tolerance can be increased.
FIG. 2 is an equivalent circuit diagram of the semiconductor device of FIG. The cathode K of the protection diode 17 is connected to the drain D of the n-MISFET 15, and the anode A of the protection diode 17 is connected to the source S of the n-MISFET 15. When an ESD surge is applied between the drain and source of the n-MISFET 15, the protection diode 17 having an avalanche voltage lower than that of the n-MISFET 15 enters the avalanche and causes an avalanche current to flow. Since the protection diode 17 has a low operating resistance, an increase in voltage applied between the cathode and the anode (between S and D of the n-MISFET 15) can be suppressed even if the avalanche current increases. As a result, a voltage higher than the withstand voltage is not applied to the n-MISFET 15 and the n-MISFET 15 is protected from destruction due to an ESD surge. In the figure, G is a gate.

Next, a plan view of the main part of the protection diode of FIG. 1 will be described.
FIG. 31 is a plan view of a principal part when a plurality of trenches having terminal portions are formed. In order not to form a step on the wafer surface, a plurality of elongated trenches 19 are formed. However, in the case of such a planar shape, when the depth of the trench is 5 μm or more, in the step of removing the damage formed on the trench side wall after the trench etching or in the corner of the bottom of the trench 19 at the end portion, Residue is easy to make. The outline of this state is shown in FIGS. The reason why shape abnormalities and residues are likely to occur at the corners of the bottom of the trench 19 is considered to be caused by the fact that the corners are singular points of the shape and the etching progresses later than other places at the bottom of the trench 19. In the case of a silicon substrate, the residual component is mainly silicon or silicon oxide.

If there is even one shape abnormality or residue, the pn junction between the n region 7 (cathode region) and the p epitaxial layer 3 formed at the bottom of the trench 19 is not formed in a regular shape, and an ESD surge is applied to the protective diode 17. When this is done, the electric field concentrates at that location. In a place where such an electric field is concentrated, the avalanche current of the protection diode 17 flows in a concentrated manner, so that the protection diode 17 is easily destroyed.
Even if there is no particular shape abnormality or residue as described above, the trench bottom at the end of the trench is a place where the radius of curvature of the n region 7 (cathode region) is small and electric field concentration is likely to occur.
Thus, the protection diode 17 formed in the trench 19 having the terminal portion cannot have a high ESD resistance, and cannot serve as an electrostatic protection element.
As a method for solving this, the planar shape of the trench 19 may be a loop so that the end portion of the trench 19 is not formed. Next, the case where the protection diode 17 of FIG.

3, FIG. 4, FIG. 5 and FIG. 6 are plan views of different main parts of the protection diode of FIG. The protection diode 17 shown in FIG. 1 is a cross-sectional view of a main part taken along line AA in each of the plan views of FIGS.
FIG. 3 shows a case where four trenches 19 connecting two end portions of two trenches having opposing end portions are formed, and FIG. 4 shows a case where three trenches 19 are formed concentrically. Is a case where one trench 19 is meandered, and FIG. 6 is a case where five trenches are formed in a donut shape. Since any planar shape has a loop shape and no termination (the trench is continuously formed without a break), local electric field concentration hardly occurs when an ESD surge is applied to the protective diode. It is excellent as an electrostatic protection element.
Further, the planar shape shown in FIG. 4 is characterized in that the trenches 19 are formed concentrically, and the radius of curvature at the four corners where the direction of the trench 19 changes is easier to make than in FIG. The larger the radius of curvature, the more the electric field concentration can be suppressed.

Further, the planar shape shown in FIG. 6 is only a circle, not a straight line portion and an arc portion, as shown in FIGS. The electric field concentration can be suppressed by increasing the radius of the circle. These planar shapes can be applied to each embodiment described below.
7 to 18 are views showing a method of manufacturing the semiconductor device of FIG. 1, and are cross-sectional views of main part manufacturing steps shown in the order of steps.
As the high concentration p ⁺ substrate 1, a substrate having a p-type impurity concentration of about 1 × 10 ¹⁹ cm ⁻³ is used. A p epitaxial layer 3 is formed on the p ⁺ substrate 1. The p epitaxial layer 3 has a p-type impurity (for example, boron) concentration of about 7 × 10 ¹⁵ cm ⁻³ (FIG. 7).
First, before forming the trench 19, in order to form the p offset region 5, boron ion implantation with a dose amount of about 1 × 10 ¹³ cm ⁻² is performed at a location where the n-MISFET 15 is to be formed (FIG. 8).

Next, an n-MISFET trench 19 having a depth of about 2 μm is formed using an unillustrated oxide film as a mask (FIG. 9).
Next, phosphorus (P) ion implantation having a dose amount of about 2 × 10 ¹³ cm ⁻² is formed at the bottom of the trench in order to form an n region 6 (referred to as n-body) which becomes an n drain region. Then, in order to form the n region 7 serving as the cathode region at the bottom of the trench for the protective diode, phosphorus (p) ion implantation having a dose of about 1 × 10 ¹⁵ cm ⁻² is performed. Thereafter, drive (heat treatment) is performed at 1150 ° C. for about 1 hour to form the p offset region 5, the n region 6, and the n region 7. At this time, the p layer 2 is formed between the p ⁺ substrate 1 and the p epitaxial layer 3 by the diffusion of boron from the p ⁺ substrate 1. N region 7 is in contact with p layer 2 to form a pn junction (may be formed separately). This is the pn junction of the protection diode 17 (FIG. 10).

Next, after forming the LOCOS oxide film 13, a gate oxide film is formed, and a polysilicon doped with high-concentration n-type impurities is grown thereon by 0.3 μm (FIG. 11).
Next, the polysilicon is left only on the sidewall of the trench by anisotropic etching to form the gate electrode of the n-MISFET 15 (the polysilicon in the protective diode portion is not functionally required) (FIG. 12).
Next, ions are selectively implanted into the contact portions on the wafer surface and the bottom of the trench. N-type impurities (for example, arsenic) are ion-implanted at a dose of 3 × 10 ¹⁵ cm ⁻² and p-type impurities (for example, BF ₂ ) are implanted at a dose of 3 × 10 ¹⁵ cm ⁻² . Further, annealing is performed at 900 ° C. for about 30 minutes to form the n ⁺ region 8 and the p ⁺ region 9 (FIG. 13).
Next, a CVD oxide film such as BPSG is formed as the interlayer insulating film 22 (FIG. 14).

Next, the wafer surface is planarized by CMP (FIG. 15).
Next, the interlayer insulating film 22 is etched to open the bottom of the trench 19 and the contact portion on the wafer surface (FIG. 16).
Next, tungsten 23 is embedded in the contact portion (FIG. 17).
Next, an aluminum-silicon-copper alloy is formed as the electrode 24, and an electrode 14 corresponding to the anode of the protective diode is formed on the back surface (FIG. 18). The electrode 24 formed on the protection diode 17 is used as a drain electrode pad of the MOSFET.
The above is the outline of the manufacturing flow.
In this manufacturing method, since the trench etching of the n-MISFET 15 and the trench etching of the protection diode 17 can be performed in the same process, the manufacturing cost can be reduced.

In the above-described embodiment, the MISFET is an n-channel type, but a case where this is a p-channel type will be described.
FIG. 19 is a fragmentary cross-sectional view of a semiconductor device having a p-MISFET. The protection diode is the same as in FIG.
In order to form the p-MISFET 16, the n-well region 4 is formed, and the p-MISFET 16 is formed in the n-well region 4.
Also in this case, since the trench of the protection diode 17 has a loop shape, electric field concentration hardly occurs and the ESD tolerance can be increased.
FIG. 20 is an equivalent circuit diagram of the semiconductor device of FIG. The cathode of the protection diode 17 and the source of the p-MISFET 16 are connected, and the anode of the protection diode 17 and the drain of the p-MISFET 16 are connected. When an ESD surge is applied between the source and drain of the p-MISFET 16, the protection diode 17 having an avalanche voltage lower than that of the p-MISFET 16 enters the avalanche and causes an avalanche current to flow. Since the protection diode 17 has a low operating resistance, even if the avalanche current increases, the increase in the voltage applied between the cathode and the anode can be suppressed to a low level. As a result, a voltage higher than the withstand voltage is not applied to the p-MISFET 16 and the protection diode 17 protects the p-MISFET 16 from an ESD surge.

FIG. 21 is a fragmentary cross-sectional view of the semiconductor device according to the second embodiment of the present invention. This is an example in which the trench type protection diode 17 is applied to the planar type n-MISFET 18. In this structure, since the n-MISFET 18 does not use the trench 19, trench etching for forming the trench 19 of the protection diode 17 is necessary. Since the n-MISFET is a planar gate, the trench 19 is formed after the gate electrode 12 is formed, so that the gate electrode (polysilicon) as shown in FIG. 1 is formed on the side wall of the trench 19 of the protective diode. Absent.
Also in this case, since the trench 19 has a loop shape, electric field concentration hardly occurs, and the ESD tolerance can be increased.

FIG. 22 is a fragmentary cross-sectional view of the semiconductor device according to the third embodiment of the present invention. The n-MISFET 18 that is a protected element has the same structure as that of the second embodiment, but the cross-sectional structure of the protective diode 17 is different.
In this embodiment, the protective diode trench 19 reaches the p ⁺ substrate 1. The trench 19 is formed of a silicon oxide film 22 and a metal film 23 such as tungsten inside thereof. An n ⁺ region 8 and an n region 7 are formed below the trench 19, and the metal film 23 and the n ⁺ region 8 are in ohmic contact. A pn junction of the protection diode 17 is formed at the interface between the n region 7 and the p ⁺ substrate 1. Compared to the second embodiment, since the deep trench 19 is formed and the n region 7 is formed in the p ⁺ substrate 1 having a low resistance, there is an advantage that the operating resistance of the protection diode 17 can be further reduced.

  Also in this case, since the trench 19 has a loop shape, electric field concentration hardly occurs, and the ESD tolerance can be increased.

FIG. 23 is a fragmentary cross-sectional view of the semiconductor device according to the fourth embodiment of the present invention. On the surface of the p layer 2 exposed at the bottom of the trench 19 of the protection diode 17, an n layer 30 serving as a cathode region is formed by an epitaxial growth method.
In this structure, the operating resistance can be reduced by changing the concentration distribution of the n region 30 as the cathode region freely by epitaxial growth and optimizing the concentration distribution of the n region 30.
In addition, since the n region 7 of Examples 2 and 3 can be formed by epitaxial growth at a relatively low temperature in Example 4 as compared with the case where the n region 7 is formed through processes such as ion implantation into the trench bottom and thermal diffusion, The influence of heat treatment on other devices formed on the same wafer can be reduced.

  Also in this case, since the trench 19 has a loop shape, electric field concentration hardly occurs, and the ESD tolerance can be increased.

FIG. 24 is a fragmentary cross-sectional view of the semiconductor device according to the fifth embodiment of the present invention. The difference from FIG. 21 is that an SOI substrate is used, and the trench 19 of the protection diode 17 is formed so as to penetrate the buried oxide film (BOX layer 31) and reach the p ⁺ substrate 1.
Also in this case, since the trench 19 has a loop shape, electric field concentration hardly occurs, and the ESD tolerance can be increased.

FIG. 25 is a fragmentary cross-sectional view of the semiconductor device according to the sixth embodiment of the present invention. The difference from FIG. 23 is that an SOI substrate is used and the trench 19 of the protection diode 17 reaches the p ⁺ substrate 1 through the buried oxide film (BOX layer 31).
Also in this case, since the trench 19 has a loop shape, electric field concentration hardly occurs, and the ESD tolerance can be increased.
In the embodiments described so far, the vertical protection diode 17 formed at a place different from the trench type lateral MISFET (n-MISFET 15) which is a protected element has been described. However, the vertical protection diode 17 is different from the n-MISFET 15 at a different place. If the protective diode 17 is formed on the chip, the area occupied by the chip in the region where the n-MISFET 15 and the protective diode 17 are combined increases. In order to reduce this occupied area, a case will be described in which a vertical protection diode is formed in a lateral MISFET having a trench structure.

When n-Body 6 of a conventional lateral MISFET having a trench structure is used as the cathode of protection diode 17 and p ⁺ substrate 1 is used as the anode of protection diode 17, n-Body 6 is in p epitaxial layer 3 (in contact with p layer 3). If the source of the n-MISFET 15 and the anode of the protection diode 17 are GND, and a high voltage is applied to the n-Body 6 (the drain of the n-MISFET 15 and the cathode of the protection diode 17), n Electric field concentration occurs at a curved surface at the pn junction formed in the Body 6 and the p epitaxial layer 3, and the n-MISFET is destroyed (ESD breakdown) by the avalanche due to the electric field concentration.
An embodiment will be described in which even when a vertical protection diode is formed in a lateral MISFET having a trench structure, it is possible to prevent the electric field concentration at the curved portion and improve the ESD tolerance.

FIG. 34 is a sectional view showing the principal part of the semiconductor device according to the seventh embodiment of the present invention. First, the p epitaxial layer 3 is formed on the p ⁺ substrate 1. The p layer 2 formed by the impurities diffused from the p ⁺ substrate 1 toward the p epitaxial layer 3 by the heat treatment when forming the n-MISFET 55 in the p epitaxial layer is formed between the p ⁺ substrate 1 and the p epitaxial layer 3. Formed.
A lateral n-MISFET 55 having a trench structure is formed in the p epitaxial layer 3. Forming n ⁺ regions 8 and n-Body6 a drain region at the bottom of the trench 19 to form n ⁺ regions 8 for the source region on the wafer surface, the gate electrode 21 via the gate oxide film 20 on the sidewall of the trench 19 Then, n-Body 6 is formed so that the bottom surface of n-Body 6 and p layer 2 are in contact with each other. The n ⁺ region 8 at the bottom of the trench 19 is electrically connected to a conductive film 23 such as tungsten filled in the trench 19, and a metal electrode 24 serving as a drain electrode is formed on the conductive film 23. The gate electrode 21 and the conductive film 23 are electrically insulated by the interlayer insulating film 22. A p ⁺ layer 9 is formed on the surface layer of the p epitaxial layer 3, a metal electrode 24 is formed on the p ⁺ layer 9, and a back electrode 14 serving as an anode electrode of the protective diode 57 is formed on the back surface of the p ⁺ substrate 1. The electrode 14, the metal electrode 24 serving as the source electrode, and the metal electrode 24 on the p ⁺ layer 9 are set to the GND potential.

In this structure, n ⁺ layer 8 and n-Body 6 serve as the cathode region of protection diode 57, p ⁺ substrate 1 and p layer 2 serve as the anode region of the protection diode, and metal electrode 24 serving as the drain electrode also serves as the cathode electrode. The back electrode 14 becomes an anode electrode.
The bottom surface of n-Body 6 is in contact with p layer 2, which has a higher impurity concentration than p epitaxial layer 3. Therefore, the impurity concentration at the bottom surface is higher than the impurity concentration of the pn junction on the curved surface of n-Body 6. Therefore, the extension of the depletion layer to the p layer 2 at the bottom surface is smaller than the extension of the depletion layer to the p epitaxial layer 3 at the curved surface.
Further, since the extension of the depletion layer reaching the p ⁺ substrate 1 becomes extremely small, the electric field strength at the bottom surface becomes higher than the electric field strength at the curved surface, and avalanche occurs at the bottom surface. This avalanche occurs at the pn junction of the entire flat bottom surface, and the avalanche current flows from the entire bottom surface to the anode electrode (back electrode 14). Therefore, the resistance of the protection diode is reduced, and the avalanche breakdown is prevented, so that the ESD resistance can be improved. Furthermore, since the electric field strength does not increase at the pn junction between n-Body 6 and p epitaxial layer 3, the avalanche injection phenomenon into gate oxide film 20 is suppressed, which contributes to the improvement of ESD resistance.

The avalanche current does not flow to the upper n ⁺ layer 8 which is the source region of the n-MISFET 55 but flows toward the p ⁺ substrate which is the anode region of the protection diode 57.
FIG. 35 is an equivalent circuit diagram of the semiconductor device of FIG. A protection diode 57 is connected in antiparallel between the drain (D) and the source (S) of the n-MISFET 55.
When a surge voltage such as ESD is applied between the drain and source of the n-MISFET 55, the withstand voltage (n An avalanche current flows through the protective diode 57 having a breakdown voltage determined by the pn junction between the Body 6 and the p layer 2 (avalanche voltage). By reducing the resistance of the protective diode 57, even if the avalanche current flowing through the protective diode 57 increases, the voltage applied to both ends of the protective diode 57 can be kept low, and a voltage higher than the breakdown voltage of the n-MISFET 55 is not applied. The MISFET 55 is protected.

FIG. 36 is a plan view of the main part of the trench shape of the semiconductor device of FIG. 34. FIG. 36 (a) shows the case of a trench having a terminal portion, and FIG. 36 (b) shows the case of a loop-like trench.
Since a loop-shaped trench (FIG. (B)) formed continuously without a break does not have a trench termination that is more likely to cause electric field concentration than a trench having a terminal (FIG. (A)). Concentration does not easily occur and a current can flow more uniformly, and the ESD tolerance can be improved.
37 to 46 are views showing a method of manufacturing the semiconductor device of FIG. 34, and are cross-sectional views of main part manufacturing steps shown in the order of steps.
As the p ⁺ substrate 1, for example, a substrate having a p-type impurity (for example, boron) concentration of about 1 × 10 ¹⁹ cm ⁻³ is used. In the p-epitaxial trilayer, for example, the concentration of the p-type impurity is set to about 7 × 10 ¹⁵ cm ⁻³ (FIG. 37).

Before forming the trench, in order to form the p-off 5, boron ion implantation with a dose amount of about 1 × 10 ¹³ cm ⁻² is performed on the n-MISFET 55 forming portion (FIG. 38).
Next, a trench 19 having a depth of about 2 μm is formed (FIG. 39).
Next, phosphorus (P) with a dose of about 2 × 10 ¹² cm ^{−2 is} implanted into the bottom of the trench for the n-MISFET 55 (n-Body 6), and driving at 1150 ° C. for about 1 hour is performed. , N-Body6 regions are formed. At this time, the p layer 2 is formed between the p ⁺ substrate 1 and the p epitaxial layer 3 by the diffusion of boron from the p substrate 1. n-Body 6 is in contact with p ⁺ substrate 1 or p layer 2 to form a pn junction of protective diode 57 (FIG. 40).
Next, a selective oxide film 13 is grown on the wafer surface (FIG. 41).
Next, a gate oxide film 20 is formed, and a polysilicon 21 doped with a high concentration n-type impurity is grown thereon by 0.3 μm (FIG. 42).

Next, the polysilicon is left only on the side wall of the trench 19 by anisotropic etching, which becomes the gate electrode 21 of the n-MISFET 55 (FIG. 43).
Next, ion implantation is selectively performed on the contact portions on the wafer surface and the bottom surface of the trench. N-type impurities (for example, arsenic) are ion-implanted at a dose amount of 3 × 10 ¹⁵ cm ⁻² and p-type impurities (for example, BF ₂ ) at a dose amount of 3 × 10 ¹⁵ cm ⁻² . Further, an annealing process is performed at 900 ° C. for about 30 minutes to form an n ⁺ region 8 and a p ⁺ region 9 (FIG. 44).
Next, after a CVD oxide film 22 such as BPSG is formed as an interlayer insulating film, the wafer surface is planarized by CMP. The oxide film is etched to open the trench bottom and the contact portion on the wafer surface. Tungsten 23 is embedded in the contact portion (FIG. 45).
Next, an aluminum-silicon-copper alloy is formed as a metal electrode 24 on the n ⁺ layer 8 and the p ⁺ layer 9 which become the source region, and the back electrode 14 is formed on the back surface of the wafer (FIG. 46).

FIG. 47 is a cross-sectional view of the principal part of the semiconductor device according to the eighth embodiment of the present invention. The n-MISFET 35 is different from the n-MISFET 55 of FIG. 34 in that n-off 10 having a concentration lower than that of n-Body 6 is formed on the curved surface portion of n-Body 6. The bottom surface in contact with the p layer 2 is high-concentration n-Body 6.
48 is an IV characteristic diagram of each of the protection diode 57 and the n-MISFET 35 excluding the protection diode 57 (when the p layer 2 is not provided and the n-off 10 is not in contact with the p ⁺ substrate 1).
As shown in FIG. 48, the higher the breakdown voltage of the n-MISFET 35 alone than the protection diode 57 is, the more preferable the protection of the n-MISFET 35 is. By adding n-off 10, the breakdown voltage of the n-MISFET 35 alone can be made sufficiently higher than the breakdown voltage of the protective diode 57, so that the ESD tolerance can be increased.

FIG. 49 is a fragmentary cross-sectional view of the semiconductor device according to the ninth embodiment of the present invention. The structure of the protection diode 40 at the bottom of the trench 19 is different from the n-MISFE 55 of FIG. That is, an n-type buried layer 32 is formed between the p ⁺ substrate 1 and the p epitaxial layer 3, and n-Body 6 is in contact with this buried layer 32. By setting the impurity concentration of the buried layer 32 to a predetermined value, an avalanche can be caused at the pn junction between the buried layer 32 and the p ⁺ substrate 1 at a voltage lower than the curved surface of n-Body 6. Since the pn junction between the buried layer 32 and the p ⁺ substrate is flat and has a large area, avalanche breakdown is unlikely to occur, and since the avalanche current flows in a wide area, the resistance of the protection diode 40 is reduced. Therefore, ESD tolerance can be improved.

  FIG. 50 is a fragmentary cross-sectional view of the semiconductor device according to the tenth embodiment of the present invention. The difference from FIG. 49 is that n-off 10 having a lower concentration than n-Body 6 is formed on the curved surface portion of n-Body 6 of n-MISFET 35 in FIG. By inserting this n-off 10, the concentration of n-Body 6 can be increased without reducing the breakdown voltage of the n-MISFET 35 alone excluding the protection diode 40. As a result, the resistance of the protection diode 40 can be lowered, and the ESD tolerance can be made higher than that of the semiconductor device of FIG.

FIG. 51 is a fragmentary cross-sectional view of the semiconductor device according to the eleventh embodiment of the present invention. The difference from FIG. 49 is that the buried layer 32 is a partially buried layer 32a that is selectively formed in the vicinity of the portion that contacts the bottom surface of the n-Body 6. This reduces the junction capacitance between the partially buried layer 32a and the p ⁺ substrate 1 and improves the high frequency characteristics of the n-MISFET 55.

  FIG. 52 is a fragmentary cross-sectional view of the semiconductor device according to the twelfth embodiment of the present invention. The difference from FIG. 51 is that n-off 10 having a lower concentration than n-Body 6 is formed on the curved surface portion of n-Body 6 of n-MISFET 55 in FIG. By inserting this n-off 10, the concentration of n-Body 6 can be increased without reducing the breakdown voltage of the n-MISFET 35 alone excluding the protection diode 40. Thereby, the resistance of the protection diode 40 can be lowered, and the ESD tolerance can be made higher than that of the semiconductor device of FIG.

FIG. 53 is a fragmentary cross-sectional view of the semiconductor device according to the thirteenth embodiment of the present invention. An n-MISFET 55 is formed in the p epitaxial layer 3 where the oxide film 58 is not formed by using the oxide film 58 selectively formed on the p ⁺ substrate 1 and the p epitaxial layer 3 formed thereon. To do. Between the p epitaxial layer 3 and the p ⁺ substrate 1, a p layer 2 which is a oozing layer is formed. The bottom surface of n-Body 6 of this n-MISFET 55 is brought into contact with p layer 2.
By using the SOI substrate in which the oxide film 58 is selectively buried in this way, the n-MISFET 55 and the vertical protection diode 57 can be formed.
In this case, the same effect as that in the case where the buried layer 32a is partially formed in FIG. 51 can be expected.

FIG. 54 is a fragmentary cross-sectional view of the semiconductor device according to the fourteenth embodiment of the present invention. The difference from FIG. 53 is that n-off 10 having a lower concentration than n-Body 6 is formed on the curved surface portion of n-Body 6 of n-MISFET 55 in FIG. By inserting this n-off 10, the concentration of n-Body 6 can be increased without reducing the breakdown voltage of the n-MISFET 35 alone excluding the protection diode 40. As a result, the resistance of the protection diode 57 can be lowered, and the ESD tolerance can be made higher than that of the semiconductor device of FIG. When the p-MISFET is formed by reversing the conductivity types of all the embodiments described above, p-Body is the p-drain region of the p-MISFET and the anode region of the protection diode. Of course, the n ⁺ substrate serves as the cathode region of the protective diode, and the same effect as in the above-described embodiment can be obtained.

Sectional drawing of the principal part of the semiconductor device of 1st Example of this invention. 1 is an equivalent circuit diagram of the semiconductor device of FIG. FIG. 1 is a plan view of the main part of the protection diode of FIG. Another main part top view of the protection diode of FIG. Another main part top view of the protection diode of FIG. Another main part top view of the protection diode of FIG. FIG. 3 is a cross-sectional view of a main part manufacturing process of the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. FIG. 8 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. FIG. 9 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. FIG. 10 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. FIG. 11 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. FIG. 12 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. FIG. 13 is a cross-sectional view of the essential part manufacturing process of the semiconductor device of FIG. FIG. 14 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. FIG. 15 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. FIG. 16 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. FIG. 17 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. Cross-sectional view of essential parts of a semiconductor device having a p-MISFET 19 is an equivalent circuit diagram of the semiconductor device of FIG. Sectional drawing of the principal part of the semiconductor device of 2nd Example of this invention Sectional drawing of the principal part of the semiconductor device of 3rd Example of this invention. Sectional drawing of the principal part of the semiconductor device of 4th Example of this invention. Sectional drawing of the principal part of the semiconductor device of 5th Example of this invention Sectional drawing of the principal part of the semiconductor device of 6th Example of this invention Sectional view of the main part of a conventional semiconductor device having a protective diode having a planar structure The figure which shows the IV characteristic of two protection diodes from which operating resistance differs Sectional view of the main part of a conventional semiconductor device having a protective diode with a trench structure It is a schematic block diagram of the protection diode of a wide trench structure, the figure (a) is a principal part top view, the figure (b) is principal part sectional drawing cut | disconnected by the XX line of the figure (a). (C) is a cross-sectional view of the main part in which an insulating film is formed on the trench side wall of FIG. (B) and a conductive film is formed thereon. 29 is a fragmentary cross-sectional view corresponding to FIG. 29C when the trench of FIG. 29 is deep. Plan view of the main part of a protection diode with multiple trenches with terminations The figure which shows the shape abnormality in the bottom part of a trench termination | terminus part, The figure (a) is a normal shape figure, The figure (b) is an unusual shape figure. The figure which shows the residue in the bottom part of a trench termination | terminus part, the figure (a) is a normal figure, the figure (b) is a figure with a residue Sectional drawing of the principal part of the semiconductor device of 7th Example of this invention. 34 is an equivalent circuit diagram of the semiconductor device of FIG. FIG. 35 is a plan view of a main part of the trench shape of the semiconductor device of FIG. 34, where (a) is a trench having a terminal end, and (b) is a loop-shaped trench. 34 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. FIG. 37 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. 34 is a fragmentary manufacturing process cross-sectional view of the semiconductor device of FIG. 34 is a cross-sectional view of manufacturing steps of main parts of the semiconductor device in FIG. FIG. 40 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. FIG. 41 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. 34 is a fragmentary manufacturing process cross-sectional view of the semiconductor device of FIG. 34 is a fragmentary manufacturing process cross-sectional view of the semiconductor device of FIG. FIG. 44 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. FIG. 45 is a principal part manufacturing process sectional view of the semiconductor device in FIG. Sectional drawing of the principal part of the semiconductor device of 8th Example of this invention. IV characteristic diagrams of the protection diode 57 and the n-MISFET 35 alone Sectional drawing of the principal part of the semiconductor device of 9th Example of this invention. Sectional drawing of the principal part of the semiconductor device of 10th Example of this invention. Sectional drawing of the principal part of the semiconductor device of 11th Embodiment of this invention. Sectional view of the principal part of the semiconductor device according to the twelfth embodiment of the present invention. Sectional view of the principal part of the semiconductor device according to the thirteenth embodiment of the present invention. Sectional view of the principal part of the semiconductor device according to the fourteenth embodiment of the invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,101 p ⁺ board | substrate 2,102 p ⁺ diffused from board | substrate 3,103 p epitaxial layer 4,105 n well area | region 5 p offset area | region 6,104 n area | region (n-body)
7, 118 n region 8, 108 n ⁺ region 9, 109 p ⁺ region 10 n offset region 11 p region (p-body)
13, 107 LOCOS oxide film 14 111 Back electrode 15, 35, 55 n-MISFET
16 p-MISFET
17, 40, 57, 112 Protection diode 18 n-MISFET
19, 119 trench 20 gate oxide film 21 gate electrode 22 interlayer insulating film 23 115 metal film 24 110 metal electrode 25 106 p-well region 30 n layer (epitaxial layer)
31 BOX layer 114 Insulating film

Claims (9)

A protection element, and a protection diode for protecting the protection element from an overvoltage; a cathode of the protection diode and a high potential side of the protection element are connected; and an anode of the protection diode is the protection target In a semiconductor device formed in connection with the low potential side of the element,
A first conductivity type semiconductor substrate; a trench formed inward from the surface of the semiconductor substrate; a second conductivity type first semiconductor region formed in the semiconductor substrate at the bottom of the trench; and the semiconductor A semiconductor device comprising: the protective diode having a pn junction formed by a substrate and the first semiconductor region, wherein a planar shape of an opening of the trench is a loop shape. A protection element and a protection diode for protecting the protection element from overvoltage; a cathode of the protection diode and a high potential side of the protection element are connected; and an anode of the protection diode is the protection element In the semiconductor device formed connected to the low potential side of
A first conductivity type semiconductor substrate; a semiconductor layer formed on the semiconductor substrate via an insulating layer; a trench reaching the semiconductor substrate from the surface of the semiconductor layer through the insulating layer; and a bottom of the trench A first semiconductor region of a second conductivity type formed inside the semiconductor substrate, and the protection diode having a pn junction formed by the semiconductor substrate and the first semiconductor region, and having an opening in the trench A semiconductor device, wherein the planar shape is a loop shape. A protection element and a protection diode for protecting the protection element from overvoltage; a cathode of the protection diode and a high potential side of the protection element are connected; and an anode of the protection diode is the protection element In the semiconductor device formed connected to the low potential side of
A semiconductor substrate of a first conductivity type, a trench formed inward from the surface of the semiconductor substrate, a second semiconductor region of a second conductivity type formed on the semiconductor substrate at the bottom of the trench, and the semiconductor A semiconductor device comprising: the protection diode having a pn junction formed by a substrate and the second semiconductor region, wherein a planar shape of an opening of the trench is a loop shape. A protection element and a protection diode for protecting the protection element from overvoltage; a cathode of the protection diode and a high potential side of the protection element are connected; and an anode of the protection diode is the protection element In the semiconductor device formed connected to the low potential side of
A first conductivity type semiconductor substrate; a semiconductor layer formed on the semiconductor substrate via an insulating layer; a trench reaching the semiconductor substrate from the surface of the semiconductor layer through the insulating layer; and a bottom of the trench A second semiconductor region of a second conductivity type formed on the semiconductor substrate, and the protection diode having a pn junction formed by the semiconductor substrate and the second semiconductor region, and having an opening in the trench A semiconductor device, wherein the planar shape is a loop shape. The semiconductor device according to claim 1, wherein a plurality of the loop-shaped trenches are formed. The semiconductor device according to claim 3, wherein a plurality of the loop-shaped trenches are formed. The semiconductor device according to any one of claims 3 or 4, characterized in that said second semiconductor region is epitaxially grown layer. The trench and the semiconductor device according to any one of claims 1 to 7, characterized in that it has a conductive film formed in contact said first or second semiconductor region and the ohmic in the trench. Said protective diode is a semiconductor device according to any one of claims 1 to 8, characterized in that the formed under the electrode pads of the protected device.

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