CN114664817A - Transient voltage suppression device and method of manufacturing the same - Google Patents

Transient voltage suppression device and method of manufacturing the same Download PDF

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CN114664817A
CN114664817A CN202210215617.XA CN202210215617A CN114664817A CN 114664817 A CN114664817 A CN 114664817A CN 202210215617 A CN202210215617 A CN 202210215617A CN 114664817 A CN114664817 A CN 114664817A
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region
epitaxial layer
trench
semiconductor substrate
implanted
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王英杰
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Hangzhou Shilan Jixin Microelectronics Co ltd
Hangzhou Silan Integrated Circuit Co Ltd
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Hangzhou Shilan Jixin Microelectronics Co ltd
Hangzhou Silan Integrated Circuit Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • H01L27/067—Lateral bipolar transistor in combination with diodes, or capacitors, or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

Disclosed are a transient voltage suppression device and a method of manufacturing the same, including: a semiconductor substrate; an isolation layer and an epitaxial layer on the semiconductor substrate; the plurality of isolation structures penetrate through the epitaxial layer and extend into the isolation layer to divide the device into a first area, a second area and a third area in the transverse direction; the plurality of first groove structures are positioned in the first area and the third area, penetrate through the epitaxial layer and the isolation layer and extend into the semiconductor substrate; the well region is positioned in the epitaxial layer of the first region; a first implanted region and a second implanted region in the first region and the second region; and the third injection regions are positioned in the epitaxial layers at two sides of the well region, and the first injection regions are positioned at two sides of the second injection regions in the well region. This application draws forth silicon control rectifier unit's negative pole and diode's positive pole from the back of device through first groove structure, and the first interconnection line of epitaxial layer top does not have the restriction, can increase silicon control rectifier unit's anodal electrode width, reduces unit area current density.

Description

Transient voltage suppression device and method of manufacturing the same
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to an instantaneous voltage suppression device and a manufacturing method thereof.
Background
As integrated circuit technology continues to evolve, device volumes become smaller and operating voltages become lower. At the same time, devices are becoming faster and higher in operating frequency. Therefore, it is more difficult to implement a Transient Voltage Suppressor (TVS) or an electrostatic Discharge (ESD) protection device to meet the requirements of today's integrated circuits. The smaller the capacitance of the TVS or ESD device, the better, and the breakdown voltage of the TVS or EDS device is determined by the operating voltage of the integrated circuit, typically slightly higher than the operating voltage of the integrated circuit. For integrated circuits with low operating voltages, TVS or ESD devices must therefore provide low breakdown voltages and low capacitance to meet the requirements of low voltage and high speed, while also meeting the requirements of as small a chip size as possible, a larger peak-to-peak current Ipp in the breakdown direction, and a smaller clamping voltage.
In the conventional TVS device, at least one lateral Silicon Controlled Rectifier (SCR) and one lateral PN diode are integrated, and a power supply terminal Vcc or an input/output terminal (I/O) and a ground terminal GND of the TVS device are both led out from the front surface of the semiconductor device. Because the SCR and the diode are both in a horizontal structure, in order to improve the current capability, a multi-finger comb design is usually adopted, each finger is very thin, the requirement on metal wiring is very high, and the phenomenon that the device is burned down due to too thin metal electrode and overlarge current density in unit area is easy to occur. In addition, the electrodes of the TVS device are led out from the front side at the same time, so that the TVS device is not suitable for a back bonding packaging process and has higher cost.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a transient voltage suppression device and a method for manufacturing the same, in which a negative electrode of a scr unit and an anode of a diode are led out from a back surface of the device through a first trench structure, a metal lead of a positive electrode of the scr unit is not limited, an electrode width can be increased, a current density per unit area can be reduced, and a chip area utilization rate can be improved.
According to a first aspect of the present invention, there is provided a transient voltage suppression device comprising: a semiconductor substrate having a first conductivity type; the isolation layer is positioned on the semiconductor substrate; the epitaxial layer is positioned on the isolation layer; a plurality of isolation structures penetrating the epitaxial layer and extending into the isolation layer, the isolation structures dividing the transient voltage suppression device into a plurality of regions in a lateral direction, the plurality of regions including a first region, a second region and a third region, wherein the second region and the third region are disposed on at least one side of the first region, the second region is adjacent to the first region, the third region is adjacent to the second region and is far away from the first region, and the third region is located at an outermost side of the transient voltage suppression device; a plurality of first trench structures located in the first region and the third region, penetrating the epitaxial layer and the isolation layer and extending into the semiconductor substrate; the well region is positioned in the first region and extends from the surface of the epitaxial layer to the direction of the semiconductor substrate; a first injection region located in the well region and the second region of the first region, having a second conductivity type; a second injection region, located in the well region of the first region and in the second region, having the first conductivity type; the third injection region is positioned in the epitaxial layers on two sides of the well region of the first region; and in the well region, the first injection region is positioned at two sides of the second injection region.
Preferably, the first region includes at least one silicon controlled rectifier unit, the silicon controlled rectifier unit includes a first triode, a second triode, a series resistor and a clamping diode, and the second region includes a diode.
Preferably, when the first region includes a plurality of silicon controlled rectifier units, the plurality of silicon controlled rectifier units are connected together in parallel.
Preferably, when the second region and the third region are disposed on both sides of the first region, the diodes in the second regions on both sides are connected together in parallel.
Preferably, the epitaxial layer has a second conductivity type, the well region has a first conductivity type, and the third implanted region has the second conductivity type.
Preferably, the well region extends from the surface of the epitaxial layer into the epitaxial layer, and the first trench structure is located on two sides of the well region.
Preferably, the first and second implanted regions are located in the well region of the first region and in the epitaxial layer of the second region.
Preferably, the first triode comprises a first injection region and a well region which are arranged in the well region and close to one side of the silicon-controlled rectifying unit, and a third injection region which are arranged in the well region and close to one side of the silicon-controlled rectifying unit; the second triode comprises a well region, an epitaxial layer and an outer diffusion region of the first groove structure, wherein the outer diffusion region is close to one side of the silicon controlled rectifier unit; the clamping diode comprises a well region and a third injection region far away from one side of the silicon controlled rectifier unit; the diode includes a first implanted region, an epitaxial layer, and a second implanted region in a second region.
Preferably, the epitaxial layer has a first conductivity type, the well region has a second conductivity type, and the third implanted region has the first conductivity type.
Preferably, the well region extends from the surface of the epitaxial layer into the isolation layer, and the first trench structure penetrates through the well region and the isolation layer and extends into the semiconductor substrate.
Preferably, the first and second implanted regions are located in the epitaxial layer of the first region and in the epitaxial layer of the second region.
Preferably, the first triode comprises a first injection region close to one side of the silicon controlled rectifier unit, an epitaxial layer and a well region close to one side of the silicon controlled rectifier unit; the second triode comprises an epitaxial layer, a well region close to one side of the silicon control rectifying unit and an outer diffusion region of the first groove structure close to one side of the silicon control rectifying unit; the clamping diode comprises a well region and an epitaxial layer, wherein the well region is far away from one side of the silicon control rectifying unit; the diode includes a first implanted region, an epitaxial layer, and a second implanted region in a second region.
Preferably, the first trench structure in the first region is an emitter of the second triode and is electrically connected with the semiconductor substrate through the first trench structure; an anode of the diode is electrically connected to the semiconductor substrate via the first trench structure in the third region.
Preferably, the first trench structure extends into the semiconductor substrate to a depth of 1 μm to 10 μm.
Preferably, the first trench structure includes a first trench and a filling material located in the first trench, the filling material is polysilicon or amorphous silicon, and the filling material has a dopant of the first conductivity type.
Preferably, the dopant of the fill material out-diffuses through the sidewalls and bottom of the first trench to form an out-diffusion region around the first trench.
Preferably, the second implantation region in the second region is disposed to overlap or not overlap with the adjacent isolation structure.
Preferably, the first conductivity type is P-type, the second conductivity type is N-type, the first triode is a PNP transistor, the second triode is an NPN transistor, and the diode is a PIN transistor; or the first conduction type is an N type, the second conduction type is a P type, the first triode is an NPN tube, the second triode is a PNP tube, and the diode is an NIP tube.
Preferably, the transient voltage suppression device further comprises: the first electrode is positioned on the surface of the semiconductor substrate far away from the epitaxial layer; a first interconnect line connecting the first implant region in the first area, the second implant region, and the second implant region in the second area; at least one second interconnect line respectively connecting the first implant region in the second region and the first trench structure in the third region.
Preferably, the first interconnection line is connected to one of a power supply and a ground, and at least one of the second interconnection lines is connected to the other of the power supply and the ground via the first trench structure, the semiconductor substrate, and the first electrode.
Preferably, the semiconductor substrate is a heavily doped structure, the epitaxial layer is a lightly doped structure, the filling material in the first trench is a heavily doped structure, the first injection region is a heavily doped structure, the second injection region is a heavily doped structure, and the third injection region is a heavily doped structure.
Preferably, the semiconductor substrate has a resistivity of 0.0015 Ω · cm to 0.01 Ω · cm.
Preferably, the epitaxial layer has a resistivity of 10 Ω · cm to 200 Ω · cm and a thickness of 1 μm to 10 μm.
Preferably, the isolation structure includes a second trench and an insulating material filled in the second trench, and the second trench penetrates through the epitaxial layer and extends into the isolation layer.
According to another aspect of the present invention, there is provided a method of manufacturing a transient voltage suppression device, including: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first conduction type; sequentially forming an isolation layer and an epitaxial layer on the semiconductor substrate; forming a plurality of isolation structures, wherein the isolation structures penetrate through the epitaxial layer and extend into the isolation layer, the isolation structures divide the transient voltage suppression device into a plurality of regions in the transverse direction, the plurality of regions include a first region, a second region and a third region, the second region and the third region are arranged on at least one side of the first region, the second region is adjacent to the first region, the third region is adjacent to the second region and is far away from the first region, and the third region is located at the outermost side of the transient voltage suppression device; forming a plurality of first trench structures in the first region and the third region, wherein the plurality of first trench structures penetrate through the epitaxial layer and the isolation layer and extend into the semiconductor substrate; forming a well region in the first region, wherein the well region extends from the surface of the epitaxial layer towards the direction of a semiconductor substrate; forming a first implant region in the first region and the second region, the first implant region having the second conductivity type, forming a second implant region in the first region and the second region, the second implant region having the first conductivity type; forming third injection regions in the epitaxial layers on two sides of the well region of the first region; and in the well region, the first injection region is positioned at two sides of the second injection region.
Preferably, at least one silicon controlled rectifier unit is formed in the first region, the silicon controlled rectifier unit comprises a first triode, a second triode, a series resistor and a clamping diode, and the diode is formed in the second region.
Preferably, when a plurality of silicon controlled rectifier units are formed in the first region, the plurality of silicon controlled rectifier units are connected together in parallel.
Preferably, when the second region and the third region are disposed on both sides of the first region, the diodes in the second regions on both sides are connected together in parallel.
Preferably, the epitaxial layer has a second conductivity type, the well region has a first conductivity type, and the third implanted region has the second conductivity type.
Preferably, the well region extends from the surface of the epitaxial layer into the epitaxial layer, and the first trench structure is located on two sides of the well region.
Preferably, the first and second implanted regions are located in the well region of the first region and in the epitaxial layer of the second region.
Preferably, the first triode comprises a first injection region in the well region, the first injection region being close to one side of the silicon-controlled rectifying unit, the well region and a third injection region in the well region being close to one side of the silicon-controlled rectifying unit; the second triode comprises a well region, an epitaxial layer and an outer diffusion region of the first groove structure, wherein the outer diffusion region is close to one side of the silicon controlled rectifier unit; the clamping diode comprises a well region and a third injection region far away from one side of the silicon controlled rectifier unit; the diode includes a first implanted region, an epitaxial layer, and a second implanted region in a second region.
Preferably, the epitaxial layer has a first conductivity type, the well region has a second conductivity type, and the third implanted region has the first conductivity type.
Preferably, the well region extends from the surface of the epitaxial layer into the isolation layer, and the first trench structure penetrates through the well region, the epitaxial layer and the isolation layer and extends into the semiconductor substrate.
Preferably, the first implanted region and the second implanted region are located in the epitaxial layer of the first region and in the epitaxial layer of the second region.
Preferably, the first triode comprises a first injection region close to one side of the silicon controlled rectifier unit, an epitaxial layer and a well region close to one side of the silicon controlled rectifier unit; the second triode comprises an epitaxial layer, a well region close to one side of the silicon-controlled rectifying unit and an outer diffusion region of the first groove structure close to one side of the silicon-controlled rectifying unit; the clamping diode comprises a well region and an epitaxial layer, wherein the well region is far away from one side of the silicon-controlled rectifying unit; the diode includes a first implanted region, an epitaxial layer, and a second implanted region in a second region.
Preferably, the first trench structure in the first region is an emitter of the second triode and is electrically connected with the semiconductor substrate through the first trench structure; an anode of the diode is electrically connected to the semiconductor substrate via the first trench structure in the third region.
Preferably, the first trench structure extends into the semiconductor substrate to a depth of 1 μm to 10 μm.
Preferably, the forming of the first trench structure includes: forming a first trench; and arranging a filling material in the first groove, wherein the filling material is polysilicon or amorphous silicon, and the filling material is provided with a dopant of the second conduction type.
Preferably, the dopant of the fill material out-diffuses through the sidewalls and bottom of the first trench to form an out-diffusion region around the first trench.
Preferably, the second implantation region in the second region is disposed to overlap or not overlap with the adjacent isolation structure.
Preferably, the first conductivity type is P-type, the second conductivity type is N-type, the first triode is a PNP transistor, the second triode is an NPN transistor, and the diode is a PIN transistor; or the first conduction type is an N type, the second conduction type is a P type, the first triode is an NPN tube, the second triode is a PNP tube, and the diode is an NIP tube.
Preferably, the manufacturing method further includes: forming a first electrode on the surface of the semiconductor substrate far away from the epitaxial layer; forming a first interconnection line and at least one second interconnection line, wherein the first interconnection line is connected with the first injection area in the first area, the second injection area in the first area and the second injection area in the second area; at least one of the second interconnect lines is connected to the first implant region in the second region and the first trench structure in the third region, respectively.
Preferably, the manufacturing method further includes: the first interconnection line is connected to one of a power supply and a ground, and at least one of the second interconnection lines is connected to the other of the power supply and the ground via the first trench structure, the semiconductor substrate, and the first electrode.
Preferably, the semiconductor substrate is a heavily doped structure, the epitaxial layer is a lightly doped structure, the filling material in the first trench is a heavily doped structure, the first injection region is a heavily doped structure, the second injection region is a heavily doped structure, and the third injection region is a heavily doped structure.
Preferably, the resistivity of the semiconductor substrate is 0.0015 Ω. cm to 0.01 Ω. cm.
Preferably, the epitaxial layer has a resistivity of 10 Ω -cm to 200 Ω -cm and a thickness of 3 μm to 10 μm.
Preferably, the forming of the isolation structure comprises: forming a plurality of second trenches that penetrate through the epitaxial layer and extend into the isolation layer; and filling an insulating material in the second trench.
According to the transient voltage suppression device and the manufacturing method thereof provided by the embodiment of the invention, the cathode of the silicon control rectification unit and the anode of the diode are led out from the back surface of the device through the first groove structure, the first groove structure comprises polycrystal with the first conductive type dopant, the first interconnecting line above the epitaxial layer is not limited, the electrode width of the anode of the silicon control rectification unit can be increased, the current density in unit area is reduced, and the utilization rate of the chip area is improved.
Furthermore, the first groove structure extends into the semiconductor substrate, the negative electrode of the silicon control rectifying unit and the anode of the diode can be led out from the back of the device, and the back bonding process can be adopted for packaging, so that routing is reduced, and packaging cost is reduced.
Furthermore, the positive electrode bonding pad of the silicon control rectifying unit can be directly formed above the silicon control rectifying unit, and the area utilization rate of a chip is improved.
Furthermore, a third injection region is formed outside the well region to reduce the trigger voltage of the silicon controlled rectifier unit.
Furthermore, the second injection region in the second region is overlapped with the isolation structure, so that the area of a PN junction can be reduced, and the capacitance of the lateral diode is reduced.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows a schematic cross-sectional view of a transient voltage suppression device according to a first embodiment of the present invention;
FIG. 2 illustrates a cross-sectional view of a transient voltage suppression device in accordance with a second embodiment of the present invention;
fig. 3 shows a circuit schematic diagram of the transient voltage suppression device according to the first to second embodiments of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.
Fig. 1 is a schematic cross-sectional view of a transient voltage suppression device according to a first embodiment of the present invention. As shown in fig. 1, the tvs 100 includes a semiconductor substrate 101, an isolation layer 110 on the semiconductor substrate 101, an epitaxial layer 120 on the isolation layer 110, a plurality of isolation structures 130, a plurality of first trench structures 140, a well region 150, and a first implantation region 151, a second implantation region 152, and a third implantation region 153.
In this embodiment, the semiconductor substrate 101 has a first conductivity type, and the epitaxial layer 120 has a second conductivity type. The first conductive type is an N type, and the second conductive type is a P type. Of course, in different embodiments, the conductivity types may be opposite, for example, the first conductivity type is P-type, and the second conductivity type is N-type.
In some embodiments, the semiconductor substrate 101 is a heavily doped structure; the epitaxial layer 120 is a lightly doped structure. For example, the semiconductor substrate 101 is a heavily doped N + type substrate and the epitaxial layer 120 is a lightly doped P-type epitaxial layer.
In a preferred embodiment, the semiconductor substrate 101 has a resistivity of 0.0015 Ω · cm to 0.01 Ω · cm. The epitaxial layer 120 has a resistivity of 10 to 200 Ω · cm and a thickness of 1 to 10 μm.
Referring to fig. 1, a plurality of isolation structures 130 penetrate through the epitaxial layer 120 and extend into the isolation layer 110, the plurality of isolation structures 130 divide the epitaxial layer 120 into a plurality of regions in a lateral direction, the plurality of regions includes a first region, a second region and a third region, wherein at least one side of the first region is provided with the second region and the third region, the second region is adjacent to the first region, the third region is adjacent to the second region and is far away from the first region, and the third region is located at an outermost side of the transient voltage suppression device.
Fig. 1 shows only the second region and the third region on the left side of the first region for explanation. The second region and the third region may be located on the right side of the first region. Further, a second region and a third region may be provided on both left and right sides of the first region. The third regions on both sides are located on the outermost side of the transient voltage suppression device.
In this embodiment, the isolation structure 130 includes a second trench 131 and an insulating material 132 filled in the second trench, and the second trench 131 penetrates through the epitaxial layer 120 and extends into the isolation layer 110. The insulating material 132 comprises silicon dioxide. The material of the isolation layer 110 includes silicon dioxide (SiO)2). The thickness of the isolation layer 110 is generally 1 to 5 μm.
A plurality of first trench structures 140 extend through the epitaxial layer 120, the isolation layer 110 and into the semiconductor substrate 101. Each first trench structure 140 includes a first trench 141 and a fill material 142 located within the first trench 141, wherein the fill material 142 has a dopant of the first conductivity type. The fill material 142 is polysilicon or amorphous silicon. The dopant of the fill material 142 outdiffuses through the sidewalls and bottom of the first trench 141, forming an outdiffusion region 143 around the first trench 141. The first trench structure extends into the semiconductor substrate 101 to a depth of 1 μm to 10 μm.
Each trench unit includes a plurality of first trench structures 140, the widths of the plurality of first trench structures 140 are the same, and the distances between the plurality of first trench structures 140 in the same trench unit are the same. For example, in fig. 1, each trench cell has 5 first trench structures. In practice, the number of the first trench structures 140 in each trench unit is not limited, and may be, for example, 4 to 20. The width of the first trench structure 140 is generally 0.5-2 um.
A plurality of first trench structures 140 are located in the first region and in the third region.
The well region 150 is located in the epitaxial layer 120 of the first region and between the plurality of trench cells in the first region. The well region 150 has a first conductivity type. For example, the well region 150 is an N-type well region. The ion implantation dosage of the well region 150 is, for example, 1E 11-5E 13cm-2。
A first implantation region 151 formed in the well region 150 of the first region and the epitaxial layer 120 of the second region, having the second conductivity type; a second implanted region 152 is formed in the well region 150 of the first region and the epitaxial layer 120 of the second region, having the first conductivity type; a third implantation region 153 is formed in the epitaxial layer 120 on both sides of the well region 150 of the first region, and has the second conductivity type, and the third implantation region 153 has a certain distance from the first trench structure 140. In the well region 150, the first implantation regions 151 are located at two sides of the second implantation regions 152. The first, second and third implant regions 151, 152 and 153 are all heavily doped structures. For example, the first implantation region 151 is heavily doped P + type, the second implantation region 152 is heavily doped N + type, and the third implantation region 153 is heavily doped P + type.
In a preferred embodiment, the first implantation region 151 has an ion implantation dosage of 4E 14-2E 16cm-2. The ion implantation dosage of the second implantation region 152 is 2E 15-5E 16cm-2. The ion implantation dosage of the third implantation region 153 is 4E 14-2E 16cm-2。
The first region includes at least one silicon controlled rectifier unit (SCR unit), and when the first region includes a plurality of SCR units, the plurality of SCR units are connected together in parallel.
In the present embodiment, two SCR units are taken as an example for explanation, but the invention is not limited thereto, and the two SCR units are connected in parallel. The 3 trench cells in the first area divide the first area into a first block and a second block. The first block and the second block are respectively provided with an SCR unit, and each SCR unit comprises a first triode (PNP), a second triode (NPN), a series resistor R and a clamping diode ZD.
In each block, the first injection region 151 of the well region 150 near the side of the scr unit formed in each block, the well region 150, and the third injection region 153 near the side of the scr unit form a first transistor (PNP), and the well region 150, the epitaxial layer 120, and the outer diffusion region 143 of the first trench structure 140 near the side of the scr unit form a second transistor (NPN). The well region 150 between the first and second implanted regions 151 and 152 forms a series resistor R, and the well region 150 and a third implanted region 153 on a side away from the scr unit form a clamp diode ZD. The breakdown voltage of the tvs device is mainly determined by the doping concentration of the well 150. In this embodiment, the silicon controlled rectifier unit side is taken as the left side of the SCR unit formed in the block for illustration, but the invention is not limited thereto. Different blocks may also form different sides of the SCR unit in the block.
In the second region, the first implanted region 151, the epitaxial layer 120, and the second implanted region 152 constitute a lateral diode (PIN).
In a preferred embodiment, the second implantation region 152 in the second region overlaps the isolation structure 130, which can reduce the PN junction area and reduce the parasitic capacitance of the lateral diode (PIN).
In this embodiment, the first transistor is a PNP transistor, the second transistor is an NPN transistor, and the diode is a PIN transistor. In different embodiments, the first transistor is an NPN transistor, the second transistor is a PNP transistor, and the diode is an NIP transistor.
When the second region and the third region are disposed on both sides of the first region, lateral diodes (PINs) in the second region on both sides are connected together in parallel.
Referring to fig. 1, the transient voltage suppression device further includes a first interconnection line 161 and at least one second interconnection line 162, a dielectric layer 170 on the epitaxial layer 120, a contact hole 171 in the dielectric layer 170, and a first electrode 180 on the back surface of the semiconductor substrate 101, the contact hole 171 in the dielectric layer 170 exposing the first implantation region 151 and the second implantation region 152, wherein the first interconnection line 161 is connected with the first implantation region 151 in the first region, the second implantation region 152 in the second region, and the second implantation region 152 in the second region through the contact hole 171 in the dielectric layer 170. Each of the second interconnection lines 162 is connected to the first implantation region 151 in the second region and the first trench structure 140 in the third region through the contact hole 171 in the dielectric layer 170. In the present embodiment, the first interconnection line 161 is connected to a power supply Vcc, and the second interconnection line 162 is connected to a ground GND via the first trench structure 140, the semiconductor substrate 101, and the first electrode 180 on the back surface of the semiconductor substrate 101.
In other preferred embodiments, the first interconnection line 161 is connected to ground GND, and the second interconnection line 162 is connected to a power supply Vcc via the first trench structure 140, the semiconductor substrate 101, and the first electrode 180 on the back surface of the semiconductor substrate 101.
Fig. 3 shows a circuit schematic of a transient voltage suppression device of an embodiment of the present invention. The diode (PIN) is connected between a power supply Vcc and a ground GND, the cathode of the diode (PIN) is connected with the power supply Vcc, and the anode of the diode (PIN) is connected with the ground GND; an emitter of a first triode (PNP) is connected with a power supply Vcc, a base is connected with the power supply Vcc through a series resistor R, and a collector is connected with a base of a second triode (NPN); the collector of the second triode (NPN) is connected to the power supply Vcc via the series resistor R, and the emitter is connected to the ground GND. The clamping diode ZD is connected between the base of the first transistor (PNP) and the base of the second transistor (NPN). The first triode (PNP) and the second triode (NPN) form a transverse silicon-controlled rectifying unit. The starting voltage of the silicon controlled rectifier unit is determined by the sum of the withstand voltage of the clamping diode ZD and the forward voltage between the base B and the emitter E of the second triode (NPN). The series resistance R is constituted by the bulk resistance of the well region 150.
Because the silicon-controlled rectifier unit removes the width limitation of the metal lead of the anode electrode, the width of the anode electrode is increased, the current density per unit area is reduced, the utilization rate of the chip area is improved, the number of SCR units per unit area is increased, and the peak-peak current Ipp capability per unit area can be improved.
According to the transient voltage suppression device provided by the embodiment of the invention, the cathode of the silicon control rectification unit and the anode of the diode are led out from the back of the device through the first groove structure, and the metal lead of the anode electrode of the silicon control rectification unit is not limited, so that the electrode width of the anode of the silicon control rectification unit can be increased, the current density in unit area is reduced, and the utilization rate of the chip area is improved.
Furthermore, the first groove structure extends into the semiconductor substrate, the negative electrode of the silicon control rectifying unit and the anode of the diode can be led out from the back of the device, and the back bonding process can be adopted for packaging, so that routing is reduced, and packaging cost is reduced.
Furthermore, the positive electrode bonding pad of the silicon control rectifying unit can be directly formed above the silicon control rectifying unit, and the area utilization rate of a chip is improved.
Furthermore, a third injection region is formed outside the well region to reduce the trigger voltage of the SCR unit.
Furthermore, the second injection region in the second region is overlapped with the isolation structure, so that the area of a PN junction can be reduced, and the capacitance of the lateral diode is reduced.
Fig. 2 is a schematic cross-sectional view of a transient voltage suppression device according to a second embodiment of the present invention. Compared to the first embodiment shown in fig. 1, the epitaxial layer 120 of the tvs device has the first conductivity type.
In the present embodiment, the semiconductor substrate 101 has a first conductivity type, and the epitaxial layer 120 has the first conductivity type. Wherein the first conductivity type is N-type. Of course, in various embodiments, the first conductivity type is P-type.
In some embodiments, the semiconductor substrate 101 is a heavily doped structure; the epitaxial layer 120 is a lightly doped structure. For example, the semiconductor substrate 101 is a heavily doped N + type substrate and the epitaxial layer is a 120 lightly doped N-type epitaxial layer.
The well region 150 is located in the first region, extends from the surface of the epitaxial layer 120 into the isolation layer 120, and has the second conductivity type. Such as the well region 150 is a P-type well region.
A first implanted region 151 formed in the epitaxial layer of the first region and the second region, having the second conductivity type; a second implanted region 152 is formed in the epitaxial layer 120 of the first and second regions, having the first conductivity type; the third implantation region 153 is formed in the epitaxial layer 120 at both sides of the well region 150 of the first region and has the first conductivity type. The first, second and third implant regions 151, 152 and 153 are all heavily doped structures. For example, the first implant region 151 is heavily doped P + type, the second implant region is heavily doped N + type, and the third implant region is heavily doped N + type.
The plurality of first trench structures 140 in the first region penetrate the well region 150, the epitaxial layer 120, the isolation layer 110 and extend into the semiconductor substrate 101.
The first region includes at least one silicon controlled rectifier unit (SCR unit), and when the first region includes a plurality of SCR units, the plurality of SCR units are connected together in parallel.
In the present embodiment, two SCR units are taken as an example for explanation, but the invention is not limited thereto, and the two SCR units are connected in parallel. The 3 trench cells in the first area divide the first area into a first block and a second block. The first block and the second block are respectively provided with an SCR unit, and each SCR unit comprises a first triode (PNP), a second triode (NPN), a series resistor R and a clamping diode ZD.
In each block, the first implantation region 151 near the side of the scr unit formed in each block, the epitaxial layer 120, and the well region 150 near the side of the scr unit form a first transistor (PNP), and the epitaxial layer 120, the well region 150 near the side of the scr unit, and the out-diffusion region 143 of the first trench structure 140 near the side of the scr unit form a second transistor (NPN). The epitaxial layer 120 between the first implanted region 151 and the second implanted region 152 forms a series resistor R, and the well region 150 and the third implanted region 153 on the side far away from the scr unit form a clamping diode ZD. In this embodiment, the silicon controlled rectifier unit side is taken as the left side of the SCR unit formed in the block for illustration, but the invention is not limited thereto. Different blocks may also form different sides of the SCR unit in the block.
In the second region, the first implanted region 151, the epitaxial layer 120, and the second implanted region 152 constitute a lateral diode (PIN). When the second region and the third region are disposed on both sides of the first region, lateral diodes (PINs) in the second region on both sides are connected together in parallel.
Compared with the first embodiment, the second embodiment of the present invention has a relatively large series resistance R and a relatively small trigger current. The rest of the second embodiment of the present invention is the same as the first embodiment, and is not described herein again.
According to the transient voltage suppression device provided by the embodiment of the invention, the cathode of the silicon control rectification unit and the anode of the diode are led out from the back of the device through the first groove structure, and the metal lead of the anode electrode of the silicon control rectification unit is not limited, so that the electrode width of the anode of the silicon control rectification unit can be increased, the current density in unit area is reduced, and the utilization rate of the chip area is improved.
Furthermore, the first groove structure extends into the semiconductor substrate, the negative electrode of the silicon control rectifying unit and the anode of the diode can be led out from the back of the device, and the back bonding process can be adopted for packaging, so that routing is reduced, and packaging cost is reduced.
Furthermore, the positive electrode bonding pad of the silicon control rectifying unit can be directly formed above the silicon control rectifying unit, and the area utilization rate of a chip is improved.
Furthermore, a third injection region is formed outside the well region to reduce the trigger voltage of the SCR unit.
Furthermore, the second injection region in the second region is overlapped with the isolation structure, so that the area of a PN junction can be reduced, and the capacitance of the lateral diode is reduced.
The embodiment of the invention also provides a manufacturing method of the transient voltage suppression device. The method can be briefly described as follows:
in step S01, a semiconductor substrate 101 is provided, the semiconductor substrate 101 having a first conductivity type. The resistivity of the semiconductor substrate is 0.0015 omega cm-0.01 omega cm.
In step S02, an isolation layer 110 and an epitaxial layer 120 are sequentially formed on a semiconductor substrate 101, wherein the isolation layer 110 is located on the semiconductor substrate 101, the epitaxial layer 120 is located on the isolation layer 110, and the epitaxial layer 120 has a first conductivity type or a second conductivity type.
In step S03, a plurality of isolation structures 130 are formed, where the isolation structures 130 penetrate through the epitaxial layer 120 and extend into the isolation layer 110, the isolation structures 130 divide the transient voltage suppression device into a plurality of regions in a lateral direction, and the plurality of regions includes a first region, a second region and a third region, where at least one side of the first region is provided with the second region and the third region, the second region is adjacent to the first region, the third region is adjacent to the second region and is far away from the first region, and the third region is located at the outermost side of the transient voltage suppression device.
In step S04, a well region 150 is formed in the epitaxial layer 120 of the first region.
In the present embodiment, the epitaxial layer 120 has the second conductivity type, and the well region 150 has the first conductivity type. For example, the epitaxial layer 120 is lightly doped P-type, and the well region is N-type; alternatively, the epitaxial layer 120 has a first conductivity type and the well region 150 has a second conductivity type. For example, the epitaxial layer 120 is lightly doped N-type and the well region 150 is P-type. The ion implantation dosage of the well region 150 is, for example, 1E 11-5E 13cm-2. After the implantation is completed, the well region 150 is annealed.
In step S05, a plurality of first trenches 141 are formed in the first region and in the third region, the first trenches 141 penetrating the epitaxial layer 120, the isolation layer 110 and extending into the semiconductor substrate 101.
In the present embodiment, when the epitaxial layer 120 has the second conductivity type and the well region 150 has the first conductivity type, the first trenches 141 are formed on two sides of the well region 150. I.e. the well region 150 is located between the first trenches 141.
Alternatively, when the epitaxial layer 120 has the first conductivity type and the well region 150 has the second conductivity type, the first trench 141 penetrates the well region 150, the epitaxial layer 120, the isolation layer 110 and extends into the semiconductor substrate 101. The first trench 141 extends into the semiconductor substrate 101 to a depth of 1 to 10 μm.
In step S06, a filling material 142 is formed within the plurality of first trenches 141, the filling material 142 having a dopant of the first conductivity type. The dopant of the fill material 142 outdiffuses through the sidewalls and bottom of the first trench 141, forming an outdiffusion region 143 around the first trench 141.
In step S07, a first implanted region 151, a second implanted region 152, and a third implanted region 153 are formed, the first implanted region 151 having the second conductivity type, the second implanted region 152 having the first conductivity type. Third implant regions 153 are formed in the epitaxial layer 120 on both sides of the well region 150 of the first region.
The ion implantation dosage of the first implantation region 151 is 4E 14-2E 16cm-2. The ion implantation dosage of the second implantation region 152 is 2E 15-5E 16cm-2. The ion implantation dosage of the third implantation region 153 is 4E 14-2E 16cm-2。
When the epitaxial layer 120 has the second conductivity type and the well region 150 has the first conductivity type, the first implantation region 151 is formed in the well region 150 of the first region and the epitaxial layer 120 of the second region; a second implant region 152 is formed in the well region 150 of the first region and the epitaxial layer 120 of the second region. The third implanted region 153 has the second conductivity type.
Alternatively, when the epitaxial layer 120 has a first conductivity type and the well region 150 has a second conductivity type, the first implantation region 151 is formed in the epitaxial layer of the first region and the second region; a second implanted region 152 is formed in the epitaxial layer 120 in the first and second regions. The third implanted region 153 has the first conductivity type.
In step S08, the first, second, and third implantation regions 151, 152, and 153 are annealed.
In step S09, a dielectric layer 170 is formed on the epitaxial layer 120, a contact hole 171 is formed in the dielectric layer 170, and a first interconnection line 161 and at least one second interconnection line 162 are formed on the dielectric layer 170, wherein the first interconnection line 161 is connected to the first implantation region 151 in the first region, the second implantation region 152 in the second region, and the second implantation region 152 in the first region through the contact hole 171 in the dielectric layer 170. Each of the second interconnecting lines 162 is connected to the first implantation region 151 in the second region and the first trench structure 140 outside the second region through the contact hole 171 in the dielectric layer 170.
In step S10, the semiconductor substrate 101 is thinned and back-side metalized to form the first electrode 108.
The order of steps S04 and S05 in the above steps may be adjusted, for example, step S04 may be placed after step S08, and step S05 may be placed after step S03, but is not limited thereto.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims (48)

1. A transient voltage suppression device, comprising:
a semiconductor substrate having a first conductivity type;
the isolation layer is positioned on the semiconductor substrate;
the epitaxial layer is positioned on the isolation layer;
a plurality of isolation structures penetrating the epitaxial layer and extending into the isolation layer, the isolation structures dividing the transient voltage suppression device into a plurality of regions in a lateral direction, the plurality of regions including a first region, a second region and a third region, wherein the second region and the third region are disposed on at least one side of the first region, the second region is adjacent to the first region, the third region is adjacent to the second region and is far away from the first region, and the third region is located at an outermost side of the transient voltage suppression device;
a plurality of first trench structures located in the first region and the third region, penetrating the epitaxial layer and the isolation layer and extending into the semiconductor substrate;
the well region is positioned in the first region and extends from the surface of the epitaxial layer to the direction of the semiconductor substrate;
a first injection region located in the well region and the second region of the first region, having a second conductivity type;
a second injection region, located in the well region of the first region and in the second region, having the first conductivity type;
the third injection region is positioned in the epitaxial layers on two sides of the well region of the first region;
in the well region, the first injection region is positioned at two sides of the second injection region.
2. The transient voltage suppression device of claim 1, wherein the first region comprises at least one thyristor comprising a first transistor, a second transistor, a series resistor, and a clamping diode, and wherein the second region comprises a diode.
3. The transient voltage suppression device of claim 2, wherein when the first region comprises a plurality of scr units, the plurality of scr units are connected together in parallel.
4. The device according to claim 2, wherein when the second region and the third region are provided on both sides of the first region, the diodes in the second region on both sides are connected together in parallel.
5. The tvs device of claim 2, wherein said epitaxial layer has a second conductivity type, said well region has a first conductivity type, and said third implanted region has a second conductivity type.
6. The tvs device of claim 5, wherein said well region extends from a surface of an epitaxial layer into said epitaxial layer, said first trench structure being located on both sides of said well region.
7. The transient voltage suppression device of claim 5 wherein said first implant region and said second implant region are located in the well region of the first region and in the epitaxial layer of the second region.
8. The transient voltage suppression device of claim 6, wherein said first transistor comprises a first implanted region in a well region adjacent to a side of said SCR unit, a well region, and a third implanted region adjacent to a side of said SCR unit; the second triode comprises a well region, an epitaxial layer and an outer diffusion region of the first groove structure, wherein the outer diffusion region is close to one side of the silicon controlled rectifier unit; the clamping diode comprises a well region and a third injection region far away from one side of the silicon-controlled rectifying unit; the diode includes a first implanted region, an epitaxial layer, and a second implanted region in a second region.
9. The tvs device of claim 2, wherein said epitaxial layer has a first conductivity type, said well region has a second conductivity type, and said third implanted region has said first conductivity type.
10. The tvs device of claim 9, wherein said well region extends from a surface of said epitaxial layer into said isolation layer, and wherein said first trench structure extends through said well region and said isolation layer and into said semiconductor substrate.
11. The tvs device of claim 9, wherein said first and second implanted regions are located in the epitaxial layer of the first region and in the epitaxial layer of the second region.
12. The tvs device of claim 10, wherein said first transistor comprises a first implanted region adjacent to a side of said scr unit, an epitaxial layer, and a well region adjacent to a side of said scr unit; the second triode comprises an epitaxial layer, a well region close to one side of the silicon control rectifying unit and an outer diffusion region of the first groove structure close to one side of the silicon control rectifying unit; the clamping diode comprises a well region and an epitaxial layer, wherein the well region is far away from one side of the silicon control rectifying unit; the diode includes a first implanted region, an epitaxial layer, and a second implanted region in a second region.
13. The transient voltage suppression device of claim 8 or 12 wherein the first trench structure in the first region is an emitter of the second transistor and is electrically connected to the semiconductor substrate via the first trench structure; an anode of the diode is electrically connected to the semiconductor substrate via the first trench structure in the third region.
14. The transient voltage suppression device of claim 1 wherein said first trench structure extends into said semiconductor substrate to a depth of between 1 μm and 10 μm.
15. The tvs device of claim 1, wherein said first trench structure comprises a first trench and a fill material in said first trench, said fill material being polysilicon or amorphous silicon, wherein said fill material has a dopant of said first conductivity type.
16. The tvs device of claim 15, wherein said dopant of said fill material out-diffuses through sidewalls and bottom of said first trench to form an out-diffusion region around said first trench.
17. The device according to claim 1, wherein the second implantation region in the second region is disposed with or without overlapping with the adjacent isolation structure.
18. The transient voltage suppression device of claim 1, wherein said first conductivity type is P-type, said second conductivity type is N-type, said first transistor is PNP transistor, said second transistor is NPN transistor, and said diode is PIN transistor; or the first conduction type is an N type, the second conduction type is a P type, the first triode is an NPN tube, the second triode is a PNP tube, and the diode is an NIP tube.
19. The transient voltage suppression device of claim 1, further comprising:
the first electrode is positioned on the surface of the semiconductor substrate far away from the epitaxial layer;
a first interconnect line connecting the first implant region in the first area, the second implant region, and the second implant region in the second area;
at least one second interconnect line respectively connecting the first implant region in the second region and the first trench structure in the third region.
20. The device of claim 19, wherein the first interconnect line is connected to one of a power supply and ground, and at least one of the second interconnect lines is connected to the other of the power supply and ground via the first trench structure, the semiconductor substrate, the first electrode.
21. The tvs device of claim 15, wherein said semiconductor substrate is a heavily doped structure, said epitaxial layer is a lightly doped structure, said fill material in said first trench is a heavily doped structure, said first implanted region is a heavily doped structure, said second implanted region is a heavily doped structure, and said third implanted region is a heavily doped structure.
22. The device according to claim 1, wherein the semiconductor substrate has a resistivity of 0.0015 Ω -cm to 0.01 Ω -cm.
23. The transient voltage suppression device of claim 1, wherein said epitaxial layer has a resistivity of 10 Ω -cm to 200 Ω -cm and a thickness of 1 μm to 10 μm.
24. The tvs device of claim 1, wherein said isolation structure comprises a second trench and an insulating material filled in said second trench, said second trench extending through said epitaxial layer and into said isolation layer.
25. A method of manufacturing a transient voltage suppression device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first conduction type;
sequentially forming an isolation layer and an epitaxial layer on the semiconductor substrate;
forming a plurality of isolation structures, wherein the isolation structures penetrate through the epitaxial layer and extend into the isolation layer, the isolation structures divide the transient voltage suppression device into a plurality of regions in the transverse direction, the plurality of regions include a first region, a second region and a third region, the second region and the third region are arranged on at least one side of the first region, the second region is adjacent to the first region, the third region is adjacent to the second region and is far away from the first region, and the third region is located at the outermost side of the transient voltage suppression device;
forming a plurality of first trench structures in the first region and the third region, wherein the plurality of first trench structures penetrate through the epitaxial layer and the isolation layer and extend into the semiconductor substrate;
forming a well region in the first region, wherein the well region extends from the surface of the epitaxial layer towards the direction of a semiconductor substrate;
forming a first implant region in the first region and the second region, the first implant region having the second conductivity type,
forming a second implanted region in the first region and the second region, the second implanted region having the first conductivity type;
forming third injection regions in the epitaxial layer on two sides of the well region of the first region;
in the well region, the first injection region is positioned at two sides of the second injection region.
26. The method of claim 25, wherein at least one scr unit is formed in the first region, the scr unit includes a first transistor, a second transistor, a series resistor, and a clamp diode, and the diode is formed in the second region.
27. The method of claim 26, wherein when the plurality of scr units are formed in the first region, the plurality of scr units are connected together in parallel.
28. The manufacturing method according to claim 26, wherein when the second region and the third region are provided on both sides of the first region, the diodes in the second regions on both sides are connected together in parallel.
29. The method of manufacturing of claim 26 wherein the epitaxial layer has a second conductivity type, the well region has a first conductivity type, and the third implanted region has the second conductivity type.
30. The method of claim 29, wherein the well region extends from a surface of an epitaxial layer into the epitaxial layer, and the first trench structure is located on both sides of the well region.
31. The method of manufacturing of claim 29 wherein the first and second implant regions are located in the well region of the first region and in the epitaxial layer of the second region.
32. The method of claim 30, wherein the first transistor comprises a first implanted region in the well region near a side of the scr unit, a well region, and a third implanted region in the well region near a side of the scr unit; the second triode comprises a well region, an epitaxial layer and an outer diffusion region of the first groove structure, wherein the outer diffusion region is close to one side of the silicon controlled rectifier unit; the clamping diode comprises a well region and a third injection region far away from one side of the silicon controlled rectifier unit; the diode includes a first implanted region, an epitaxial layer, and a second implanted region in a second region.
33. The method of manufacturing of claim 26 wherein the epitaxial layer has a first conductivity type, the well region has a second conductivity type, and the third implanted region has the first conductivity type.
34. The method of claim 33, wherein the well region extends from a surface of the epitaxial layer into the isolation layer, and wherein the first trench structure extends through the well region, the epitaxial layer and the isolation layer and into the semiconductor substrate.
35. The method of manufacturing of claim 33 wherein the first and second implanted regions are located in the epitaxial layer of the first region and in the epitaxial layer of the second region.
36. The method of claim 34, wherein the first transistor comprises a first implanted region near one side of the scr unit, an epitaxial layer, and a well region near one side of the scr unit; the second triode comprises an epitaxial layer, a well region close to one side of the silicon control rectifying unit and an outer diffusion region of the first groove structure close to one side of the silicon control rectifying unit; the clamping diode comprises a well region and an epitaxial layer, wherein the well region is far away from one side of the silicon control rectifying unit; the diode includes a first implanted region in the second region, an epitaxial layer, and a second implanted region.
37. The manufacturing method according to claim 32 or 36, wherein the first trench structure in the first region is an emitter of the second transistor and is electrically connected to the semiconductor substrate via the first trench structure; an anode of the diode is electrically connected to the semiconductor substrate via the first trench structure in the third region.
38. The method of manufacturing of claim 25, wherein the first trench structure extends into the semiconductor substrate to a depth of 1 μ ι η to 10 μ ι η.
39. The method of manufacturing of claim 25, wherein forming a first trench structure comprises:
forming a first trench; and
and arranging a filling material in the first groove, wherein the filling material is polysilicon or amorphous silicon, and the filling material is provided with a dopant of the second conduction type.
40. The method of claim 39 wherein the dopant of the fill material out-diffuses through the sidewalls and bottom of the first trench to form an out-diffusion region around the first trench.
41. The method of claim 25, wherein the second implanted region in the second region is disposed with or without overlapping with an adjacent isolation structure.
42. The manufacturing method according to claim 25, wherein the first conductivity type is P-type, the second conductivity type is N-type, the first transistor is a PNP transistor, the second transistor is an NPN transistor, and the diode is a PIN transistor; or the first conduction type is an N type, the second conduction type is a P type, the first triode is an NPN tube, the second triode is a PNP tube, and the diode is an NIP tube.
43. The method of manufacturing of claim 25, further comprising:
forming a first electrode on the surface of the semiconductor substrate far away from the epitaxial layer;
forming a first interconnection line and at least one second interconnection line, wherein the first interconnection line is connected with the first injection area in the first area, the second injection area in the first area and the second injection area in the second area; at least one of the second interconnect lines is connected to the first implant region in the second region and the first trench structure in the third region, respectively.
44. The method of manufacturing of claim 43, further comprising:
the first interconnection line is connected to one of a power supply and a ground, and at least one of the second interconnection lines is connected to the other of the power supply and the ground via the first trench structure, the semiconductor substrate, and the first electrode.
45. The method of claim 39, wherein the semiconductor substrate is a heavily doped structure, the epitaxial layer is a lightly doped structure, the fill material in the first trench is a heavily doped structure, the first implanted region is a heavily doped structure, the second implanted region is a heavily doped structure, and the third implanted region is a heavily doped structure.
46. The manufacturing method according to claim 25, wherein the resistivity of the semiconductor substrate is 0.0015 Ω -cm to 0.01 Ω -cm.
47. The method of claim 25, wherein the epitaxial layer has a resistivity of 10 Ω -cm to 200 Ω -cm and a thickness of 3 μm to 10 μm.
48. The method of manufacturing of claim 25, wherein forming an isolation structure comprises:
forming a plurality of second trenches penetrating the epitaxial layer and extending into the isolation layer;
and filling an insulating material in the second trench.
CN202210215617.XA 2022-03-07 2022-03-07 Transient voltage suppression device and method of manufacturing the same Pending CN114664817A (en)

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CN116632003A (en) * 2023-07-25 2023-08-22 深圳市槟城电子股份有限公司 Preparation method of ESD protection device and ESD protection device
CN116632003B (en) * 2023-07-25 2023-12-15 深圳市槟城电子股份有限公司 Preparation method of ESD protection device and ESD protection device

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