CN114664817A - Transient voltage suppression device and method of manufacturing the same - Google Patents

Transient voltage suppression device and method of manufacturing the same Download PDF

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CN114664817A
CN114664817A CN202210215617.XA CN202210215617A CN114664817A CN 114664817 A CN114664817 A CN 114664817A CN 202210215617 A CN202210215617 A CN 202210215617A CN 114664817 A CN114664817 A CN 114664817A
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epitaxial layer
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王英杰
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Hangzhou Shilan Jixin Microelectronics Co ltd
Hangzhou Silan Integrated Circuit Co Ltd
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Hangzhou Silan Integrated Circuit Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/611—Combinations of BJTs and one or more of diodes, resistors or capacitors
    • H10D84/619—Combinations of lateral BJTs and one or more of diodes, resistors or capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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Abstract

公开了一种瞬间电压抑制器件及其制造方法，包括：半导体衬底；位于半导体衬底上的隔离层和外延层；多个隔离结构，贯穿外延层并延伸至隔离层中，将器件在横向方向上分为第一区域、第二区域和第三区域；多个第一沟槽结构，位于第一区域和第三区域中，贯穿外延层、隔离层并延伸至半导体衬底中；阱区，位于第一区域的外延层中；第一注入区和第二注入区，位于第一区域和第二区域中；第三注入区，位于阱区两侧的外延层中，在阱区中第一注入区位于第二注入区的两侧。本申请通过第一沟槽结构将硅控整流单元的负极以及二极管的阳极从器件的背面引出，外延层上方的第一互联线没有限制，可以增加硅控整流单元的正极的电极宽度，降低单位面积电流密度。An instantaneous voltage suppression device and a manufacturing method thereof are disclosed, including: a semiconductor substrate; an isolation layer and an epitaxial layer on the semiconductor substrate; It is divided into a first region, a second region and a third region in the direction; a plurality of first trench structures are located in the first region and the third region, penetrate the epitaxial layer, the isolation layer and extend into the semiconductor substrate; the well region , located in the epitaxial layer of the first region; the first implantation region and the second implantation region, located in the first region and the second region; the third implantation region, located in the epitaxial layer on both sides of the well region, in the well region An implantation region is located on both sides of the second implantation region. In this application, the cathode of the silicon-controlled rectifier unit and the anode of the diode are drawn out from the back of the device through the first trench structure. The first interconnection above the epitaxial layer is not limited, and the electrode width of the anode of the silicon-controlled rectifier unit can be increased, reducing the unit areal current density.

Description

瞬间电压抑制器件及其制造方法Transient voltage suppression device and method of making the same

技术领域technical field

本发明涉及半导体制造技术领域，特别涉及一种瞬间电压抑制器件及其制造方法。The invention relates to the technical field of semiconductor manufacturing, in particular to a transient voltage suppression device and a manufacturing method thereof.

背景技术Background technique

随着集成电路技术持续发展，器件体积变得越来越小且工作电压变得越来越低。同时，器件运行变得越来越快并且工作频率变得越来越高。因此，更加难以实现瞬间电压抑制器件(Transient Voltage Suppressor，TVS)或静电(Electro-Static Discharge，ESD)保护器件，以满足当今集成电路的需要。TVS或ESD器件的电容越小越好，而TVS或EDS器件的击穿电压由集成电路的工作电压决定，一般略高于集成电路的工作电压。因此对于工作电压低的集成电路，TVS或ESD器件必须提供低的击穿电压和低的电容以满足低压高速的要求，同时还需要满足尽可能小的芯片尺寸、击穿方向上更大的峰-峰值电流Ipp以及更小的钳位电压的要求。As integrated circuit technology continues to develop, devices are getting smaller and operating voltages are getting lower and lower. At the same time, devices are running faster and operating at higher frequencies. Therefore, it is more difficult to implement a transient voltage suppressor (TVS) or an electrostatic (Electro-Static Discharge, ESD) protection device to meet the needs of today's integrated circuits. The smaller the capacitance of the TVS or ESD device, the better, and the breakdown voltage of the TVS or EDS device is determined by the working voltage of the integrated circuit, which is generally slightly higher than the working voltage of the integrated circuit. Therefore, for integrated circuits with low operating voltage, TVS or ESD devices must provide low breakdown voltage and low capacitance to meet the requirements of low voltage and high speed, and also need to meet the smallest possible chip size and larger peak in the breakdown direction. - Requirements for peak current Ipp and smaller clamping voltage.

现有的TVS器件中，至少集成了一个横向硅控整流器(SCR)和一个横向PN二极管，TVS器件的电源端Vcc或者输入输出端(I/O)和接地端GND均从半导体器件的正面引出。由于SCR及二极管都是横向结构，为了提高电流能力，通常采用多手指梳状设计，每个手指都很细，对金属布线要求很高，容易出现金属电极由于太细而单位面积电流密度过大而导致器件烧毁的现象。另外，TVS器件的电极同时从正面引出，不适合背面键合封装工艺，成本较高。In the existing TVS device, at least one lateral silicon-controlled rectifier (SCR) and one lateral PN diode are integrated, and the power supply terminal Vcc or input and output terminal (I/O) and ground terminal GND of the TVS device are all drawn from the front side of the semiconductor device. . Since the SCR and diode are both lateral structures, in order to improve the current capability, a multi-finger comb design is usually used, each finger is very thin, and the requirements for metal wiring are very high. resulting in device burnout. In addition, the electrodes of the TVS device are drawn from the front side at the same time, which is not suitable for the backside bonding and packaging process, and the cost is high.

发明内容SUMMARY OF THE INVENTION

鉴于上述问题，本发明的目的在于提供一种瞬间电压抑制器件及其制造方法，将硅控整流单元的负极以及二极管的阳极通过第一沟槽结构从器件的背面引出，硅控整流单元的正极的金属引线没有限制，可以增加电极宽度，降低单位面积电流密度，提高芯片面积利用率。In view of the above problems, the purpose of the present invention is to provide a transient voltage suppression device and a manufacturing method thereof. There is no limit to the metal leads, which can increase the electrode width, reduce the current density per unit area, and improve the chip area utilization.

根据本发明的第一方面，提供一种瞬间电压抑制器件，包括：半导体衬底，具有第一导电类型；隔离层，位于所述半导体衬底上；外延层，位于所述隔离层上；多个隔离结构，贯穿所述外延层并延伸至所述隔离层中，所述多个隔离结构将所述瞬间电压抑制器件在横向方向上分为多个区域，所述多个区域包括第一区域、第二区域和第三区域，其中，所述第一区域的至少一侧设置有所述第二区域和所述第三区域，所述第二区域与所述第一区域相邻，所述第三区域与所述第二区域相邻并远离所述第一区域，且所述第三区域位于所述瞬间电压抑制器件的最外侧；多个第一沟槽结构，位于第一区域中以及所述第三区域中，贯穿所述外延层、隔离层并延伸至所述半导体衬底中；阱区，位于所述第一区域中，从所述外延层的表面朝半导体衬底方向延伸；第一注入区，位于第一区域的阱区中和第二区域中，具有第二导电类型；第二注入区，位于第一区域的阱区中和第二区域中，具有第一导电类型；第三注入区，位于第一区域的所述阱区两侧的外延层中；其中，在所述阱区中，所述第一注入区位于所述第二注入区的两侧。According to a first aspect of the present invention, there is provided a transient voltage suppression device, comprising: a semiconductor substrate having a first conductivity type; an isolation layer on the semiconductor substrate; an epitaxial layer on the isolation layer; a plurality of isolation structures extending through the epitaxial layer and into the isolation layer, the plurality of isolation structures dividing the transient voltage suppression device into a plurality of regions in a lateral direction, the plurality of regions including a first region , a second area and a third area, wherein at least one side of the first area is provided with the second area and the third area, the second area is adjacent to the first area, the a third region adjacent to the second region and away from the first region, and the third region is located at the outermost side of the transient voltage suppression device; a plurality of first trench structures located in the first region; and in the third region, penetrate the epitaxial layer and the isolation layer and extend into the semiconductor substrate; a well region, located in the first region, extends from the surface of the epitaxial layer toward the semiconductor substrate; a first implantation region, located in the well region of the first region and in the second region, and having a second conductivity type; a second implantation region, located in the well region of the first region and in the second region, having a first conductivity type; A third implantation region is located in the epitaxial layer on both sides of the well region of the first region; wherein, in the well region, the first implantation region is located on both sides of the second implantation region.

优选地，第一区域中包括至少一个硅控整流单元，所述硅控整流单元包括第一三极管、第二三极管、串联电阻以及钳位二极管，第二区域中包括二极管。Preferably, the first area includes at least one silicon-controlled rectifier unit, the silicon-controlled rectifier unit includes a first triode, a second triode, a series resistor and a clamping diode, and the second area includes a diode.

优选地，第一区域中包括多个硅控整流单元时，多个硅控整流单元并联连接在一起。Preferably, when the first region includes multiple silicon-controlled rectifier units, the multiple silicon-controlled rectifier units are connected together in parallel.

优选地，当所述第一区域的两侧均设置有所述第二区域和第三区域时，两侧的第二区域中的二极管并联连接在一起。Preferably, when both sides of the first area are provided with the second area and the third area, the diodes in the second areas on both sides are connected together in parallel.

优选地，所述外延层具有第二导电类型，所述阱区具有第一导电类型，所述第三注入区具有第二导电类型。Preferably, the epitaxial layer has a second conductivity type, the well region has a first conductivity type, and the third implantation region has a second conductivity type.

优选地，所述阱区从外延层的表面延伸至所述外延层中，所述第一沟槽结构位于所述阱区两侧。Preferably, the well region extends from the surface of the epitaxial layer into the epitaxial layer, and the first trench structure is located on both sides of the well region.

优选地，所述第一注入区和所述第二注入区位于第一区域的阱区中和第二区域的外延层中。Preferably, the first implanted region and the second implanted region are located in the well region of the first region and in the epitaxial layer of the second region.

优选地，所述第一三极管包括阱区中靠近所述硅控整流单元一侧的第一注入区、阱区以及靠近所述硅控整流单元一侧的第三注入区；第二三极管包括阱区、外延层以及靠近所述硅控整流单元一侧的第一沟槽结构的外扩散区域；钳位二极管包括阱区以及远离所述硅控整流单元一侧的第三注入区；二极管包括第二区域中的第一注入区、外延层以及第二注入区。Preferably, the first triode comprises a first injection region in the well region close to the side of the silicon-controlled rectifier unit, a well region and a third injection region close to the side of the silicon-controlled rectifier unit; The electrode tube includes a well region, an epitaxial layer, and an outer diffusion region of the first trench structure on one side of the silicon-controlled rectifier unit; the clamping diode includes a well region and a third injection region on the side away from the silicon-controlled rectifier unit. ; The diode includes a first implantation region, an epitaxial layer and a second implantation region in the second region.

优选地，所述外延层具有第一导电类型，所述阱区具有第二导电类型，所述第三注入区具有第一导电类型。Preferably, the epitaxial layer has a first conductivity type, the well region has a second conductivity type, and the third implantation region has a first conductivity type.

优选地，所述阱区从所述外延层的表面延伸至所述隔离层中，所述第一沟槽结构贯穿所述阱区以及隔离层，并延伸至半导体衬底中。Preferably, the well region extends from the surface of the epitaxial layer into the isolation layer, and the first trench structure penetrates the well region and the isolation layer, and extends into the semiconductor substrate.

优选地，所述第一注入区和所述第二注入区位于第一区域的外延层中和第二区域的外延层中。Preferably, the first implanted region and the second implanted region are located in the epitaxial layer of the first region and in the epitaxial layer of the second region.

优选地，所述第一三极管包括靠近所述硅控整流单元一侧的第一注入区、外延层以及靠近所述硅控整流单元一侧的阱区；第二三极管包括外延层、靠近所述硅控整流单元一侧的阱区以及靠近所述硅控整流单元一侧的第一沟槽结构的外扩散区域；钳位二极管包括远离所述硅控整流单元一侧的阱区以及外延层；二极管包括第二区域中的第一注入区、外延层以及第二注入区。Preferably, the first triode includes a first injection region close to the side of the silicon-controlled rectifier unit, an epitaxial layer, and a well region close to the side of the silicon-controlled rectifier unit; the second triode includes an epitaxial layer , a well region on one side of the silicon-controlled rectifier unit and an out-diffusion region of the first trench structure on one side of the silicon-controlled rectifier unit; the clamping diode includes a well region on the side away from the silicon-controlled rectifier unit and an epitaxial layer; the diode includes a first implanted region, an epitaxial layer, and a second implanted region in the second region.

优选地，第一区域中的第一沟槽结构为第二三极管的发射极，并经由第一沟槽结构与半导体衬底电连接；二极管的阳极经由第三区域中的第一沟槽结构与半导体衬底电连接。Preferably, the first trench structure in the first region is the emitter of the second triode, and is electrically connected to the semiconductor substrate through the first trench structure; the anode of the diode passes through the first trench in the third region The structure is electrically connected to the semiconductor substrate.

优选地，所述第一沟槽结构延伸至所述半导体衬底中的深度为1μm～10μm。Preferably, the depth of the first trench structure extending into the semiconductor substrate is 1 μm˜10 μm.

优选地，所述第一沟槽结构包括第一沟槽以及位于第一沟槽内的填充材料，所述填充材料为多晶硅或者非晶硅，其中，所述填充材料具有第一导电类型的掺杂剂。Preferably, the first trench structure includes a first trench and a filling material in the first trench, the filling material is polysilicon or amorphous silicon, wherein the filling material has a first conductivity type doped miscellaneous agents.

优选地，所述填充材料的掺杂剂通过第一沟槽的侧壁和底部向外扩散在第一沟槽周围形成外扩散区域。Preferably, the dopant of the filling material is outdiffused through the sidewall and bottom of the first trench to form an outdiffusion region around the first trench.

优选地，所述第二区域中的第二注入区与相邻的所述隔离结构重叠或不重叠设置。Preferably, the second injection region in the second region overlaps or does not overlap with the adjacent isolation structure.

优选地，所述第一导电类型为P型，所述第二导电类型为N型，第一三极管为PNP管，第二三极管为NPN管，二极管为PIN管；或者所述第一导电类型为N型，所述第二导电类型为P型，第一三极管为NPN管，第二三极管为PNP管，二极管为NIP管。Preferably, the first conductivity type is P type, the second conductivity type is N type, the first transistor is a PNP transistor, the second transistor is an NPN transistor, and the diode is a PIN transistor; One conductivity type is N type, the second conductivity type is P type, the first transistor is an NPN transistor, the second transistor is a PNP transistor, and the diode is a NIP transistor.

优选地，所述瞬间电压抑制器件还包括：第一电极，位于半导体衬底远离外延层的表面上；第一互连线，所述第一互连线连接第一区域中的第一注入区、第二注入区以及第二区域中的第二注入区；至少一个第二互连线，至少一个所述第二互连线分别连接第二区域中的第一注入区以及第三区域中的第一沟槽结构。Preferably, the transient voltage suppression device further comprises: a first electrode located on the surface of the semiconductor substrate away from the epitaxial layer; a first interconnection line, the first interconnection line connecting the first implantation region in the first region , a second injection region, and a second injection region in the second region; at least one second interconnection line, at least one of the second interconnection lines respectively connects the first injection region in the second region and the third region in the third region. the first trench structure.

优选地，所述第一互连线与电源和地中的一个连接，至少一个所述第二互连线经由第一沟槽结构、所述半导体衬底、第一电极与电源和地中的另一个连接。Preferably, the first interconnect line is connected to one of the power supply and the ground, and at least one of the second interconnect lines is connected to the one of the power supply and the ground via the first trench structure, the semiconductor substrate, and the first electrode. another connection.

优选地，所述半导体衬底为重掺杂结构，所述外延层为轻掺杂结构，位于第一沟槽内的填充材料为重掺杂结构，所述第一注入区为重掺杂结构，所述第二注入区为重掺杂结构，所述第三注入区为重掺杂结构。Preferably, the semiconductor substrate is a heavily doped structure, the epitaxial layer is a lightly doped structure, the filling material in the first trench is a heavily doped structure, and the first implantation region is a heavily doped structure , the second injection region is a heavily doped structure, and the third injection region is a heavily doped structure.

优选地，所述半导体衬底的电阻率为0.0015Ω·cm～0.01Ω·cm。Preferably, the resistivity of the semiconductor substrate is 0.0015Ω·cm˜0.01Ω·cm.

优选地，所述外延层的电阻率为10Ω·cm～200Ω·cm，厚度为1μm～10μm。Preferably, the resistivity of the epitaxial layer is 10Ω·cm˜200Ω·cm, and the thickness is 1 μm˜10 μm.

优选地，所述隔离结构包括第二沟槽和填充在第二沟槽内的绝缘材料，所述第二沟槽贯穿所述外延层并延伸至所述隔离层中。Preferably, the isolation structure includes a second trench and an insulating material filled in the second trench, the second trench penetrates the epitaxial layer and extends into the isolation layer.

根据本发明的另一方面，提供一种瞬间电压抑制器件的制造方法，包括：提供半导体衬底，所述半导体衬底具有第一导电类型；在所述半导体衬底上依次形成隔离层和外延层；形成多个隔离结构，所述隔离结构贯穿所述外延层并延伸至所述隔离层中，所述多个隔离结构将所述瞬间电压抑制器件在横向方向上分为多个区域，所述多个区域包括第一区域、第二区域和第三区域，其中，所述第一区域的至少一侧设置有所述第二区域和所述第三区域，所述第二区域与所述第一区域相邻，所述第三区域与所述第二区域相邻并远离所述第一区域，且所述第三区域位于所述瞬间电压抑制器件的最外侧；在第一区域和第三区域中形成多个第一沟槽结构，所述多个第一沟槽结构贯穿所述外延层、隔离层并延伸至所述半导体衬底中；在所述第一区域中形成阱区，所述阱区从所述外延层的表面朝半导体衬底方向延伸；在第一区域和第二区域中形成第一注入区，所述第一注入区具有第二导电类型，在第一区域和第二区域中形成第二注入区，所述第二注入区具有第一导电类型；在第一区域的所述阱区两侧的外延层中形成第三注入区；其中，在所述阱区中，所述第一注入区位于所述第二注入区的两侧。According to another aspect of the present invention, there is provided a method for manufacturing a transient voltage suppression device, comprising: providing a semiconductor substrate, the semiconductor substrate having a first conductivity type; and sequentially forming an isolation layer and an epitaxial layer on the semiconductor substrate layer; forming a plurality of isolation structures, the isolation structures penetrating the epitaxial layer and extending into the isolation layer, the plurality of isolation structures dividing the transient voltage suppression device into a plurality of regions in the lateral direction, so The plurality of areas include a first area, a second area and a third area, wherein at least one side of the first area is provided with the second area and the third area, the second area and the The first area is adjacent, the third area is adjacent to the second area and away from the first area, and the third area is located at the outermost side of the transient voltage suppression device; A plurality of first trench structures are formed in the three regions, the plurality of first trench structures penetrate the epitaxial layer, the isolation layer and extend into the semiconductor substrate; a well region is formed in the first region, The well region extends from the surface of the epitaxial layer toward the semiconductor substrate; a first implantation region is formed in the first region and the second region, the first implantation region has a second conductivity type, and the first region and the second region are formed in a direction of the semiconductor substrate; A second implantation region is formed in the second region, and the second implantation region has a first conductivity type; a third implantation region is formed in the epitaxial layers on both sides of the well region in the first region; wherein, in the well region , the first injection region is located on both sides of the second injection region.

优选地，在第一区域中形成至少一个硅控整流单元，所述硅控整流单元包括第一三极管、第二三极管、串联电阻以及钳位二极管，在第二区域中形成二极管。Preferably, at least one silicon-controlled rectifier unit is formed in the first area, the silicon-controlled rectifier unit includes a first triode, a second triode, a series resistor and a clamping diode, and a diode is formed in the second area.

优选地，在第一区域中形成多个硅控整流单元时，多个硅控整流单元并联连接在一起。Preferably, when multiple silicon-controlled rectifier units are formed in the first region, the multiple silicon-controlled rectifier units are connected together in parallel.

优选地，当所述第一区域的两侧均设置有所述第二区域和第三区域时，两侧的第二区域中的二极管并联连接在一起。Preferably, when both sides of the first area are provided with the second area and the third area, the diodes in the second areas on both sides are connected together in parallel.

优选地，所述外延层具有第二导电类型，所述阱区具有第一导电类型，所述第三注入区具有第二导电类型。Preferably, the epitaxial layer has a second conductivity type, the well region has a first conductivity type, and the third implantation region has a second conductivity type.

优选地，所述阱区从外延层的表面延伸至所述外延层中，所述第一沟槽结构位于所述阱区两侧。Preferably, the well region extends from the surface of the epitaxial layer into the epitaxial layer, and the first trench structure is located on both sides of the well region.

优选地，所述第一注入区和所述第二注入区位于第一区域的阱区中和第二区域的外延层中。Preferably, the first implanted region and the second implanted region are located in the well region of the first region and in the epitaxial layer of the second region.

优选地，所述第一三极管包括阱区中靠近所述硅控整流单元一侧的第一注入区、阱区以及阱区靠近所述硅控整流单元一侧的第三注入区；第二三极管包括阱区、外延层以及靠近所述硅控整流单元一侧的第一沟槽结构的外扩散区域；钳位二极管包括阱区以及远离所述硅控整流单元一侧的第三注入区；二极管包括第二区域中的第一注入区、外延层以及第二注入区。Preferably, the first triode comprises a first injection region in the well region close to the side of the silicon-controlled rectifier unit, a well region, and a third injection region of the well region close to the side of the silicon-controlled rectifier unit; The two transistors include a well region, an epitaxial layer and an out-diffusion region of the first trench structure on one side of the silicon-controlled rectifier unit; the clamping diode includes a well region and a third one on the side away from the silicon-controlled rectifier unit. an implanted region; the diode includes a first implanted region, an epitaxial layer, and a second implanted region in the second region.

优选地，所述外延层具有第一导电类型，所述阱区具有第二导电类型，所述第三注入区具有第一导电类型。Preferably, the epitaxial layer has a first conductivity type, the well region has a second conductivity type, and the third implantation region has a first conductivity type.

优选地，所述阱区从所述外延层的表面延伸至所述隔离层中，所述第一沟槽结构贯穿所述阱区、外延层以及隔离层，并延伸至半导体衬底中。Preferably, the well region extends from the surface of the epitaxial layer into the isolation layer, and the first trench structure penetrates the well region, the epitaxial layer and the isolation layer, and extends into the semiconductor substrate.

优选地，所述第一注入区和所述第二注入区位于第一区域的外延层中和第二区域的外延层中。Preferably, the first implanted region and the second implanted region are located in the epitaxial layer of the first region and in the epitaxial layer of the second region.

优选地，所述第一三极管包括靠近所述硅控整流单元一侧的第一注入区、外延层以及靠近所述硅控整流单元一侧的阱区；第二三极管包括外延层、靠近所述硅控整流单元一侧的阱区以及靠近所述硅控整流单元一侧的第一沟槽结构的外扩散区域；钳位二极管包括远离所述硅控整流单元一侧的阱区以及外延层；二极管包括第二区域中的第一注入区、外延层以及第二注入区。Preferably, the first triode includes a first injection region close to the side of the silicon-controlled rectifier unit, an epitaxial layer, and a well region close to the side of the silicon-controlled rectifier unit; the second triode includes an epitaxial layer , a well region on one side of the silicon-controlled rectifier unit and an out-diffusion region of the first trench structure on one side of the silicon-controlled rectifier unit; the clamping diode includes a well region on the side away from the silicon-controlled rectifier unit and an epitaxial layer; the diode includes a first implanted region, an epitaxial layer, and a second implanted region in the second region.

优选地，第一区域中的第一沟槽结构为第二三极管的发射极，并经由第一沟槽结构与半导体衬底电连接；二极管的阳极经由第三区域中的第一沟槽结构与半导体衬底电连接。Preferably, the first trench structure in the first region is the emitter of the second triode, and is electrically connected to the semiconductor substrate through the first trench structure; the anode of the diode passes through the first trench in the third region The structure is electrically connected to the semiconductor substrate.

优选地，所述第一沟槽结构延伸至所述半导体衬底中的深度为1μm～10μm。Preferably, the depth of the first trench structure extending into the semiconductor substrate is 1 μm˜10 μm.

优选地，形成第一沟槽结构包括：形成第一沟槽；以及在第一沟槽内设置填充材料，所述填充材料为多晶硅或者非晶硅，其中，所述填充材料具有第二导电类型的掺杂剂。Preferably, forming the first trench structure includes: forming a first trench; and disposing a filling material in the first trench, wherein the filling material is polysilicon or amorphous silicon, wherein the filling material has a second conductivity type dopant.

优选地，所述填充材料的掺杂剂通过第一沟槽的侧壁和底部向外扩散在第一沟槽周围形成外扩散区域。Preferably, the dopant of the filling material is outdiffused through the sidewall and bottom of the first trench to form an outdiffusion region around the first trench.

优选地，述第二区域中的第二注入区与相邻的所述隔离结构重叠或不重叠设置。Preferably, the second injection region in the second region overlaps or does not overlap with the adjacent isolation structure.

优选地，所述第一导电类型为P型，所述第二导电类型为N型，第一三极管为PNP管，第二三极管为NPN管，二极管为PIN管；或者所述第一导电类型为N型，所述第二导电类型为P型，第一三极管为NPN管，第二三极管为PNP管，二极管为NIP管。Preferably, the first conductivity type is P type, the second conductivity type is N type, the first transistor is a PNP transistor, the second transistor is an NPN transistor, and the diode is a PIN transistor; One conductivity type is N type, the second conductivity type is P type, the first transistor is an NPN transistor, the second transistor is a PNP transistor, and the diode is a NIP transistor.

优选地，所述制造方法还包括：在半导体衬底远离外延层的表面上形成第一电极；形成第一互连线及至少一个第二互连线，所述第一互连线连接第一区域中的第一注入区、第二注入区以及第二区域中的第二注入区；至少一个所述第二互连线分别连接第二区域中的第一注入区以及第三区域中的第一沟槽结构。Preferably, the manufacturing method further comprises: forming a first electrode on a surface of the semiconductor substrate away from the epitaxial layer; forming a first interconnection line and at least one second interconnection line, the first interconnection line connecting the first interconnection line The first implanted region in the region, the second implanted region and the second implanted region in the second region; at least one of the second interconnect lines respectively connects the first implanted region in the second region and the first implanted region in the third region a trench structure.

优选地，所述制造方法还包括：将所述第一互连线与电源和地中的一个连接、至少一个所述第二互连线经由第一沟槽结构、所述半导体衬底、第一电极与电源和地中的另一个连接。Preferably, the manufacturing method further includes: connecting the first interconnection line to one of a power source and a ground, at least one of the second interconnection lines via the first trench structure, the semiconductor substrate, the first One electrode is connected to the other of power and ground.

优选地，所述半导体衬底为重掺杂结构，所述外延层为轻掺杂结构，位于第一沟槽内的填充材料为重掺杂结构，所述第一注入区为重掺杂结构，所述第二注入区为重掺杂结构，所述第三注入区为重掺杂结构。Preferably, the semiconductor substrate is a heavily doped structure, the epitaxial layer is a lightly doped structure, the filling material in the first trench is a heavily doped structure, and the first implantation region is a heavily doped structure , the second injection region is a heavily doped structure, and the third injection region is a heavily doped structure.

优选地，所述半导体衬底的电阻率为0.0015Ω.cm～0.01Ω.cm。Preferably, the resistivity of the semiconductor substrate is 0.0015Ω.cm˜0.01Ω.cm.

优选地，所述外延层的电阻率为10Ω.cm～200Ω.cm，厚度为3μm～10μm。Preferably, the resistivity of the epitaxial layer is 10Ω.cm˜200Ω.cm, and the thickness is 3 μm˜10 μm.

优选地，形成隔离结构包括：形成多个第二沟槽，所述第二沟槽贯穿所述外延层并延伸至所述隔离层中；在所述第二沟槽内填充绝缘材料。Preferably, forming the isolation structure includes: forming a plurality of second trenches, the second trenches passing through the epitaxial layer and extending into the isolation layer; and filling the second trenches with an insulating material.

本发明实施例提供的瞬间电压抑制器件及其制造方法，通过第一沟槽结构将硅控整流单元的负极以及二极管的阳极从器件的背面引出，第一沟槽结构包括具有第一导电类型掺杂剂的多晶，外延层上方的第一互连线没有限制，可以增加硅控整流单元的正极的电极宽度，降低单位面积电流密度，提高芯片面积利用率。In the transient voltage suppression device and the manufacturing method thereof provided by the embodiments of the present invention, the cathode of the silicon-controlled rectifier unit and the anode of the diode are drawn out from the back side of the device through a first trench structure, and the first trench structure includes a dopant with a first conductivity type. For the polycrystalline dopant, the first interconnection line above the epitaxial layer is not limited, which can increase the electrode width of the positive electrode of the silicon-controlled rectifier unit, reduce the current density per unit area, and improve the utilization rate of the chip area.

进一步地，第一沟槽结构延伸至半导体衬底中，可以将硅控整流单元的负极以及二极管的阳极从器件的背面引出，可以采用背面键合工艺进行封装，减少打线，降低封装成本。Further, the first trench structure extends into the semiconductor substrate, and the cathode of the silicon-controlled rectifier unit and the anode of the diode can be drawn out from the back of the device, and the back-side bonding process can be used for packaging, reducing wire bonding and packaging costs.

进一步地，硅控整流单元的正极焊盘可以直接形成在硅控整流单元的上方，提高芯片面积利用率。Further, the positive electrode pad of the silicon-controlled rectifier unit can be directly formed above the silicon-controlled rectifier unit, so as to improve the utilization rate of the chip area.

进一步地，阱区外侧形成有第三注入区，以降低硅控整流单元的触发电压。Further, a third injection region is formed outside the well region to reduce the trigger voltage of the silicon-controlled rectifier unit.

进一步地，第二区域中的第二注入区与隔离结构重叠，可以减小PN结面积，降低横向二极管的电容。Further, the second injection region in the second region overlaps with the isolation structure, which can reduce the area of the PN junction and reduce the capacitance of the lateral diode.

附图说明Description of drawings

通过以下参照附图对本发明实施例的描述，本发明的上述以及其他目的、特征和优点将更为清楚，在附图中：The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

图1示出本发明第一实施例的瞬间电压抑制器件的剖面示意图；1 shows a schematic cross-sectional view of a transient voltage suppression device according to a first embodiment of the present invention;

图2示出本发明第二实施例的瞬间电压抑制器件的剖面示意图；2 shows a schematic cross-sectional view of a transient voltage suppression device according to a second embodiment of the present invention;

图3示出本发明第一至第二实施例的瞬间电压抑制器件的电路示意图。FIG. 3 shows schematic circuit diagrams of transient voltage suppression devices according to the first to second embodiments of the present invention.

具体实施方式Detailed ways

以下将参照附图更详细地描述本发明的各种实施例。在各个附图中，相同的元件采用相同或类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, the same elements are designated by the same or similar reference numerals. For the sake of clarity, various parts in the figures have not been drawn to scale.

下面结合附图和实施例，对本发明的具体实施方式作进一步详细描述。The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

图1示出本发明第一实施例提供的瞬间电压抑制器件的剖面示意图。如图1所示，所述瞬间电压抑制器件100包括半导体衬底101、位于半导体衬底101上的隔离层110、位于所述隔离层110上的外延层120、多个隔离结构130、多个第一沟槽结构140、阱区150以及第一注入区151、第二注入区152和第三注入区153。FIG. 1 shows a schematic cross-sectional view of a transient voltage suppression device provided by a first embodiment of the present invention. As shown in FIG. 1 , the transient voltage suppression device 100 includes a semiconductor substrate 101, an isolation layer 110 on the semiconductor substrate 101, an epitaxial layer 120 on the isolation layer 110, a plurality of isolation structures 130, a plurality of The first trench structure 140 , the well region 150 , and the first implantation region 151 , the second implantation region 152 and the third implantation region 153 .

在本实施例中，半导体衬底101具有第一导电类型，所述外延层120具有第二导电类型。其中，所述第一导电类型为N型，所述第二导电类型为P型。当然在不同的实施例中，导电类型也可以相反，例如所述第一导电类型为P型，所述第二导电类型为N型。In this embodiment, the semiconductor substrate 101 has a first conductivity type, and the epitaxial layer 120 has a second conductivity type. Wherein, the first conductivity type is N type, and the second conductivity type is P type. Of course, in different embodiments, the conductivity types may also be opposite, for example, the first conductivity type is P-type, and the second conductivity type is N-type.

在一些实施例中，半导体衬底101为重掺杂结构；所述外延层120为轻掺杂结构。例如，半导体衬底101是重掺杂N+型衬底，外延层120为轻掺杂P-型外延层。In some embodiments, the semiconductor substrate 101 is a heavily doped structure; the epitaxial layer 120 is a lightly doped structure. For example, the semiconductor substrate 101 is a heavily doped N+ type substrate, and the epitaxial layer 120 is a lightly doped P- type epitaxial layer.

在一个优选地实施例中，所述半导体衬底101的电阻率为0.0015Ω·cm～0.01Ω·cm。所述外延层120的电阻率为10Ω·cm～200Ω·cm，厚度为1μm～10μm。In a preferred embodiment, the resistivity of the semiconductor substrate 101 is 0.0015Ω·cm˜0.01Ω·cm. The resistivity of the epitaxial layer 120 is 10Ω·cm˜200Ω·cm, and the thickness is 1 μm˜10 μm.

参见图1，多个隔离结构130贯穿所述外延层120并延伸至所述隔离层110中，所述多个隔离结构130在横向方向上将外延层120分为多个区域，所述多个区域包括第一区域、第二区域和第三区域，其中，所述第一区域的至少一侧设置有所述第二区域和所述第三区域，所述第二区域与所述第一区域相邻，所述第三区域与所述第二区域相邻并远离所述第一区域，且所述第三区域位于所述瞬间电压抑制器件的最外侧。Referring to FIG. 1 , a plurality of isolation structures 130 penetrate the epitaxial layer 120 and extend into the isolation layer 110 , the plurality of isolation structures 130 divide the epitaxial layer 120 into a plurality of regions in a lateral direction, the plurality of The area includes a first area, a second area and a third area, wherein at least one side of the first area is provided with the second area and the third area, and the second area and the first area are Adjacent, the third region is adjacent to the second region and away from the first region, and the third region is located at the outermost side of the transient voltage suppression device.

图1仅示出第二区域和第三区域位于第一区域的左侧进行说明。第二区域和第三区域位于所述第一区域的右侧也可以。更进一步地，可以在所述第一区域的左侧和右侧都设置第二区域和第三区域。两侧的第三区域均位于所述瞬间电压抑制器件的最外侧。FIG. 1 only shows that the second area and the third area are located on the left side of the first area for illustration. The second area and the third area may also be located on the right side of the first area. Further, a second area and a third area may be provided on the left and right sides of the first area. The third regions on both sides are located at the outermost side of the transient voltage suppression device.

在本实施例中，所述隔离结构130包括第二沟槽131和填充在第二沟槽内的绝缘材料132，所述第二沟槽131贯穿所述外延层120并延伸至所述隔离层110中。所述绝缘材料132包括二氧化硅。隔离层110的材料包括二氧化硅(SiO2)。隔离层110的厚度一般为1～5μm。In this embodiment, the isolation structure 130 includes a second trench 131 and an insulating material 132 filled in the second trench, and the second trench 131 penetrates the epitaxial layer 120 and extends to the isolation layer 110. The insulating material 132 includes silicon dioxide. The material of the isolation layer 110 includes silicon dioxide (SiO 2 ). The thickness of the isolation layer 110 is generally 1˜5 μm.

多个第一沟槽结构140贯穿所述外延层120、隔离层110并延伸至所述半导体衬底101中。每个第一沟槽结构140均包括第一沟槽141以及位于第一沟槽141内的填充材料142，其中，所述填充材料142具有第一导电类型的掺杂剂。填充材料142为多晶硅或非晶硅。填充材料142的掺杂剂通过第一沟槽141的侧壁和底部向外扩散，在第一沟槽141周围形成外扩散区域143。第一沟槽结构延伸至半导体衬底101内的深度为1μm～10μm。A plurality of first trench structures 140 penetrate through the epitaxial layer 120 , the isolation layer 110 and extend into the semiconductor substrate 101 . Each of the first trench structures 140 includes a first trench 141 and a filling material 142 within the first trench 141 , wherein the filling material 142 has a dopant of a first conductivity type. The filling material 142 is polysilicon or amorphous silicon. The dopant of the filling material 142 is diffused outward through the sidewalls and bottoms of the first trenches 141 to form outdiffusion regions 143 around the first trenches 141 . The depth of the first trench structure extending into the semiconductor substrate 101 is 1 μm˜10 μm.

每个沟槽单元包括多个第一沟槽结构140，多个第一沟槽结构140的宽度相同，同一个沟槽单元中多个第一沟槽结构140之间的间距相同。例如图1中，每个沟槽单元具有5个第一沟槽结构。实际上，每个沟槽单元中第一沟槽结构140的数量不做限制，例如可以在4～20个。第一沟槽结构140的宽度一般为0.5～2um。Each trench unit includes a plurality of first trench structures 140 , the widths of the plurality of first trench structures 140 are the same, and the distances between the plurality of first trench structures 140 in the same trench unit are the same. For example, in FIG. 1 , each trench unit has five first trench structures. Actually, the number of the first trench structures 140 in each trench unit is not limited, for example, it can be 4-20. The width of the first trench structure 140 is generally 0.5˜2 μm.

多个第一沟槽结构140位于第一区域中以及第三区域中。A plurality of first trench structures 140 are located in the first region and in the third region.

阱区150位于第一区域的外延层120中，并且位于第一区域中的多个沟槽单元之间。阱区150具有第一导电类型。例如所述阱区150为N型阱区。阱区150的离子注入剂量例如为1E11～5E13cm-2。The well region 150 is located in the epitaxial layer 120 of the first region and between the plurality of trench cells in the first region. The well region 150 has the first conductivity type. For example, the well region 150 is an N-type well region. The ion implantation dose of the well region 150 is, for example, 1E11˜5E13 cm −2 .

第一注入区151形成在第一区域的阱区150和第二区域的外延层120中，具有第二导电类型；第二注入区152形成在第一区域的阱区150和第二区域的外延层120中，具有第一导电类型；第三注入区153形成在第一区域的阱区150两侧的外延层120中，具有第二导电类型，所述第三注入区153与所述第一沟槽结构140具有一定的间距。其中，在阱区150中，第一注入区151位于第二注入区152的两侧。第一注入区151、第二注入区152以及第三注入区153都是重掺杂结构。例如，第一注入区151为重掺杂P+型，第二注入区152为重掺杂N+型，第三注入区153为重掺杂P+型。The first implantation region 151 is formed in the well region 150 of the first region and the epitaxial layer 120 of the second region, and has the second conductivity type; the second implantation region 152 is formed in the well region 150 of the first region and the epitaxial layer of the second region The layer 120 has the first conductivity type; the third implantation region 153 is formed in the epitaxial layer 120 on both sides of the well region 150 in the first region, and has the second conductivity type, and the third implantation region 153 and the first The trench structures 140 have a certain pitch. Wherein, in the well region 150 , the first implantation region 151 is located on both sides of the second implantation region 152 . The first implantation region 151 , the second implantation region 152 and the third implantation region 153 are all heavily doped structures. For example, the first implantation region 151 is heavily doped P+ type, the second implantation region 152 is heavily doped N+ type, and the third implantation region 153 is heavily doped P+ type.

在一个优选地实施例中，所述第一注入区151的离子注入剂量为4E14～2E16cm-2。所述第二注入区152的离子注入剂量为2E15～5E16cm-2。所述第三注入区153的离子注入剂量为4E14～2E16cm-2。In a preferred embodiment, the ion implantation dose of the first implantation region 151 is 4E14˜2E16 cm −2 . The ion implantation dose of the second implantation region 152 is 2E15˜5E16 cm −2 . The ion implantation dose of the third implantation region 153 is 4E14˜2E16 cm −2 .

第一区域中包括至少一个硅控整流单元(SCR单元)，当第一区域中包括多个硅控整流单元时，多个硅控整流单元并联连接在一起。The first area includes at least one silicon-controlled rectifier unit (SCR unit), and when the first area includes multiple silicon-controlled rectifier units, the multiple silicon-controlled rectifier units are connected together in parallel.

本实施例中以两个SCR单元为例进行说明，但并不局限于此，两个SCR单元并联在一起。第一区域中的3个沟槽单元将第一区域分为第一区块和第二区块。其中，第一区块和第二区块内分别形成一个SCR单元，每个SCR单元包括第一三极管(PNP)、第二三极管(NPN)、串联电阻R以及钳位二极管ZD。In this embodiment, two SCR units are used as an example for description, but it is not limited to this, and the two SCR units are connected in parallel. The three trench cells in the first area divide the first area into a first block and a second block. One SCR unit is formed in the first block and the second block respectively, and each SCR unit includes a first triode (PNP), a second triode (NPN), a series resistor R and a clamping diode ZD.

在每个区块中，阱区150中靠近每个区块中形成的所述硅控整流单元一侧的第一注入区151、阱区150以及靠近所述硅控整流单元一侧的第三注入区153构成第一三极管(PNP)，阱区150、外延层120以及靠近所述硅控整流单元一侧的第一沟槽结构140的外扩散区域143构成第二三极管(NPN)。第一注入区151和第二注入区152之间的阱区150构成串联电阻R，阱区150以及远离所述硅控整流单元一侧的第三注入区153构成钳位二极管ZD。瞬间电压抑制器件的击穿电压主要由阱区150的掺杂浓度决定。本实施例中以所述硅控整流单元一侧为该区块中形成的SCR单元的左侧为例进行说明，但并不局限于此。不同区块也可以该区块中形成SCR单元的不同侧。In each block, the first injection region 151 in the well region 150 close to the side of the silicon-controlled rectifier unit formed in each block, the well region 150 and the third injection region 150 on the side of the silicon-controlled rectifier unit formed in each block The implantation region 153 constitutes a first triode (PNP), and the well region 150, the epitaxial layer 120 and the outer diffusion region 143 of the first trench structure 140 on one side of the silicon-controlled rectifier unit constitute a second triode (NPN). ). The well region 150 between the first injection region 151 and the second injection region 152 constitutes a series resistance R, and the well region 150 and the third injection region 153 on the side away from the silicon-controlled rectifier unit constitute a clamping diode ZD. The breakdown voltage of the transient voltage suppression device is mainly determined by the doping concentration of the well region 150 . In this embodiment, the side of the silicon-controlled rectifier unit is taken as an example to be the left side of the SCR unit formed in the block, but it is not limited to this. Different blocks may also form different sides of the SCR cell in the block.

在第二区域中，第一注入区151、外延层120以及第二注入区152构成横向二极管(PIN)。In the second region, the first implanted region 151, the epitaxial layer 120 and the second implanted region 152 constitute a lateral diode (PIN).

在一个优选地实施例中，第二区域中的第二注入区152与隔离结构130重叠，可以减小PN结面积，降低横向二极管(PIN)的寄生电容。In a preferred embodiment, the second injection region 152 in the second region overlaps with the isolation structure 130, which can reduce the area of the PN junction and reduce the parasitic capacitance of the lateral diode (PIN).

在本实施例中，第一三极管为PNP管，第二三极管为NPN管，二极管为PIN管。当然在不同的实施例中，第一三极管为NPN管，第二三极管为PNP管，二极管为NIP管。In this embodiment, the first transistor is a PNP transistor, the second transistor is an NPN transistor, and the diode is a PIN transistor. Of course, in different embodiments, the first transistor is an NPN transistor, the second transistor is a PNP transistor, and the diode is a NIP transistor.

当所述第一区域的两侧均设置有所述第二区域和第三区域时，两侧的第二区域中的横向二极管(PIN)并联连接在一起。When both sides of the first area are provided with the second area and the third area, the lateral diodes (PINs) in the second areas on both sides are connected together in parallel.

参见图1，所述瞬间电压抑制器件还包括第一互连线161和至少一个第二互连线162、位于外延层120上的介质层170、介质层170中的接触孔171以及位于半导体衬底101背面的第一电极180，介质层170中的接触孔171暴露出第一注入区151和第二注入区152，其中，所述第一互连线161通过介质层170中的接触孔171与第一区域中的第一注入区151、第二注入区152以及第二区域中的第二注入区152连接。所述每个第二互连线162通过介质层170中的接触孔171与第二区域中的第一注入区151以及第三区域中的第一沟槽结构140连接。在本实施例中，所述第一互连线161与电源Vcc连接，所述第二互连线162经由第一沟槽结构140、所述半导体衬底101以及半导体衬底101背面的第一电极180与地GND连接。Referring to FIG. 1 , the transient voltage suppression device further includes a first interconnection line 161 and at least one second interconnection line 162 , a dielectric layer 170 on the epitaxial layer 120 , a contact hole 171 in the dielectric layer 170 , and a semiconductor substrate The first electrode 180 on the back of the bottom 101, the contact hole 171 in the dielectric layer 170 exposes the first injection region 151 and the second injection region 152, wherein the first interconnection line 161 passes through the contact hole 171 in the dielectric layer 170 It is connected to the first implantation region 151 in the first region, the second implantation region 152 and the second implantation region 152 in the second region. Each of the second interconnect lines 162 is connected to the first injection region 151 in the second region and the first trench structure 140 in the third region through the contact hole 171 in the dielectric layer 170 . In this embodiment, the first interconnection line 161 is connected to the power supply Vcc, and the second interconnection line 162 passes through the first trench structure 140 , the semiconductor substrate 101 and the first interconnection on the backside of the semiconductor substrate 101 . The electrode 180 is connected to the ground GND.

在其他优选地实施例中，所述第一互连线161与地GND连接，所述第二互连线162经由第一沟槽结构140、所述半导体衬底101以及半导体衬底101背面的第一电极180与电源Vcc连接。In other preferred embodiments, the first interconnection line 161 is connected to the ground GND, and the second interconnection line 162 passes through the first trench structure 140 , the semiconductor substrate 101 and the backside of the semiconductor substrate 101 . The first electrode 180 is connected to the power supply Vcc.

图3示出本发明实施例的瞬间电压抑制器件的电路示意图。二极管(PIN)连接在电源Vcc和地GND之间，二极管(PIN)的阴极与电源Vcc连接，二极管(PIN)的阳极与地GND连接；第一三极管(PNP)的发射极与电源Vcc连接，基极经由串联电阻R与电源Vcc连接，集电极与第二三极管(NPN)的基极连接；第二三极管(NPN)的集电极经由串联电阻R与电源Vcc连接，发射极与地GND连接。钳位二极管ZD连接在第一三极管(PNP)的基极和第二三极管(NPN)的基极之间。第一三极管(PNP)和第二三极管(NPN)构成横向的硅控整流单元。硅控整流单元的启动电压由钳位二极管ZD的耐压以及第二三极管(NPN)的基极B和发射极E之间的正向电压之和决定。串联电阻R由阱区150的体电阻构成。FIG. 3 shows a schematic circuit diagram of a transient voltage suppression device according to an embodiment of the present invention. The diode (PIN) is connected between the power supply Vcc and the ground GND, the cathode of the diode (PIN) is connected to the power supply Vcc, the anode of the diode (PIN) is connected to the ground GND; the emitter of the first transistor (PNP) is connected to the power supply Vcc connection, the base is connected to the power supply Vcc through the series resistance R, and the collector is connected to the base of the second triode (NPN); the collector of the second triode (NPN) is connected to the power supply Vcc through the series resistance R, and the emission The pole is connected to ground GND. The clamping diode ZD is connected between the base of the first triode (PNP) and the base of the second triode (NPN). The first triode (PNP) and the second triode (NPN) constitute a lateral silicon-controlled rectifier unit. The starting voltage of the silicon-controlled rectifier unit is determined by the withstand voltage of the clamping diode ZD and the sum of the forward voltage between the base B and the emitter E of the second triode (NPN). The series resistance R is formed by the bulk resistance of the well region 150 .

由于硅控整流单元去除了正极电极金属引线的宽度限制，增加了正极电极宽度，降低了单位面积电流密度，提高芯片面积利用率，增加单位面积SCR单元数量，可以提升单位面积的峰-峰值电流Ipp能力。Since the silicon-controlled rectifier unit removes the width limitation of the metal lead of the positive electrode, increases the width of the positive electrode, reduces the current density per unit area, improves the utilization rate of chip area, and increases the number of SCR units per unit area, which can improve the peak-to-peak current per unit area. Ipp capability.

本发明实施例提供的瞬间电压抑制器件，将硅控整流单元的负极以及二极管的阳极通过第一沟槽结构从器件的背面引出，硅控整流单元的正极电极金属引线没有限制，可以增加硅控整流单元的正极的电极宽度，降低单位面积电流密度，提高芯片面积利用率。In the transient voltage suppression device provided by the embodiment of the present invention, the negative electrode of the silicon-controlled rectifier unit and the anode of the diode are drawn out from the back of the device through the first trench structure. The metal lead of the positive electrode of the silicon-controlled rectifier unit is not limited. The electrode width of the positive electrode of the rectifier unit reduces the current density per unit area and improves the utilization rate of the chip area.

进一步地，第一沟槽结构延伸至半导体衬底中，可以将硅控整流单元的负极以及二极管的阳极从器件的背面引出，可以采用背面键合工艺进行封装，减少打线，降低封装成本。Further, the first trench structure extends into the semiconductor substrate, and the cathode of the silicon-controlled rectifier unit and the anode of the diode can be drawn out from the back of the device, and the back-side bonding process can be used for packaging, reducing wire bonding and packaging costs.

进一步地，硅控整流单元的正极焊盘可以直接形成在硅控整流单元的上方，提高芯片面积利用率。Further, the positive electrode pad of the silicon-controlled rectifier unit can be directly formed above the silicon-controlled rectifier unit, so as to improve the utilization rate of the chip area.

进一步地，阱区外侧形成有第三注入区，以降低硅控整流单元的触发电压。Further, a third injection region is formed outside the well region to reduce the trigger voltage of the silicon-controlled rectifier unit.

进一步地，第二区域中的第二注入区与隔离结构重叠，可以减小PN结面积，降低横向二极管的电容。Further, the second injection region in the second region overlaps with the isolation structure, which can reduce the area of the PN junction and reduce the capacitance of the lateral diode.

图2示出本发明第二实施例提供的瞬间电压抑制器件的剖面示意图。与图1所示的第一实施例相比，所述瞬间电压抑制器件的外延层120具有第一导电类型。FIG. 2 shows a schematic cross-sectional view of the transient voltage suppression device provided by the second embodiment of the present invention. Compared with the first embodiment shown in FIG. 1 , the epitaxial layer 120 of the transient voltage suppression device has a first conductivity type.

在本实施例中，半导体衬底101具有第一导电类型，所述外延层120具有第一导电类型。其中，所述第一导电类型为N型。当然在不同的实施例中，所述第一导电类型为P型。In this embodiment, the semiconductor substrate 101 has the first conductivity type, and the epitaxial layer 120 has the first conductivity type. Wherein, the first conductivity type is N-type. Of course, in different embodiments, the first conductivity type is P-type.

在一些实施例中，半导体衬底101为重掺杂结构；所述外延层120为轻掺杂结构。例如，半导体衬底101是重掺杂N+型衬底，外延层为120轻掺杂N-型外延层。In some embodiments, the semiconductor substrate 101 is a heavily doped structure; the epitaxial layer 120 is a lightly doped structure. For example, the semiconductor substrate 101 is a heavily doped N+ type substrate, and the epitaxial layer is a 120 lightly doped N- type epitaxial layer.

阱区150位于第一区域中，从外延层120的表面延伸至所述隔离层120中，具有第二导电类型。例如所述阱区150位P型阱区。The well region 150 is located in the first region, extends from the surface of the epitaxial layer 120 into the isolation layer 120 , and has the second conductivity type. For example, the well region is a 150-bit P-type well region.

第一注入区151形成在第一区域和第二区域的外延层中，具有第二导电类型；第二注入区152形成在第一区域和第二区域的外延层120中，具有第一导电类型；第三注入区153形成在第一区域的阱区150两侧的外延层120中，具有第一导电类型。第一注入区151、第二注入区152以及第三注入区153都是重掺杂结构。例如，第一注入区151为重掺杂P+型，第二注入区为重掺杂N+型，第三注入区为重掺杂N+型。The first implantation region 151 is formed in the epitaxial layer of the first region and the second region, and has the second conductivity type; the second implantation region 152 is formed in the epitaxial layer 120 of the first region and the second region, and has the first conductivity type ; The third implantation region 153 is formed in the epitaxial layer 120 on both sides of the well region 150 in the first region, and has the first conductivity type. The first implantation region 151 , the second implantation region 152 and the third implantation region 153 are all heavily doped structures. For example, the first implantation region 151 is heavily doped P+ type, the second implantation region is heavily doped N+ type, and the third implantation region is heavily doped N+ type.

第一区域中的多个第一沟槽结构140贯穿阱区150、外延层120、隔离层110并延伸至所述半导体衬底101中。The plurality of first trench structures 140 in the first region penetrate through the well region 150 , the epitaxial layer 120 , the isolation layer 110 and extend into the semiconductor substrate 101 .

第一区域中包括至少一个硅控整流单元(SCR单元)，当第一区域中包括多个硅控整流单元时，多个硅控整流单元并联连接在一起。The first area includes at least one silicon-controlled rectifier unit (SCR unit), and when the first area includes multiple silicon-controlled rectifier units, the multiple silicon-controlled rectifier units are connected together in parallel.

本实施例中以两个SCR单元为例进行说明，但并不局限于此，两个SCR单元并联在一起。第一区域中的3个沟槽单元将第一区域分为第一区块和第二区块。其中，第一区块和第二区块内分别形成一个SCR单元，每个SCR单元包括第一三极管(PNP)、第二三极管(NPN)、串联电阻R以及钳位二极管ZD。In this embodiment, two SCR units are used as an example for description, but it is not limited to this, and the two SCR units are connected in parallel. The three trench cells in the first area divide the first area into a first block and a second block. One SCR unit is formed in the first block and the second block respectively, and each SCR unit includes a first triode (PNP), a second triode (NPN), a series resistor R and a clamping diode ZD.

在每个区块中，靠近每个区块中形成的所述硅控整流单元一侧的第一注入区151、外延层120以及靠近所述硅控整流单元一侧的阱区150构成第一三极管(PNP)，外延层120、靠近所述硅控整流单元一侧的阱区150以及靠近所述硅控整流单元一侧的第一沟槽结构140的外扩散区域143构成第二三极管(NPN)。第一注入区151和第二注入区152之间的外延层120构成串联电阻R，远离所述硅控整流单元一侧的阱区150以及第三注入区153构成钳位二极管ZD。本实施例中以所述硅控整流单元一侧为该区块中形成的SCR单元的左侧为例进行说明，但并不局限于此。不同区块也可以该区块中形成SCR单元的不同侧。In each block, the first injection region 151, the epitaxial layer 120 and the well region 150 on the side of the silicon-controlled rectifier unit formed in each block constitute the first Triode (PNP), the epitaxial layer 120, the well region 150 on the side of the silicon-controlled rectifier unit, and the outdiffusion region 143 of the first trench structure 140 on the side of the silicon-controlled rectifier unit constitute the second and third pole tube (NPN). The epitaxial layer 120 between the first injection region 151 and the second injection region 152 constitutes a series resistance R, and the well region 150 and the third injection region 153 on the side away from the silicon-controlled rectifier unit constitute a clamping diode ZD. In this embodiment, the side of the silicon-controlled rectifier unit is taken as an example to be the left side of the SCR unit formed in the block, but it is not limited to this. Different blocks may also form different sides of the SCR cell in the block.

在第二区域中，第一注入区151、外延层120以及第二注入区152构成横向二极管(PIN)。当所述第一区域的两侧均设置有所述第二区域和第三区域时，两侧的第二区域中的横向二极管(PIN)并联连接在一起。In the second region, the first implanted region 151, the epitaxial layer 120 and the second implanted region 152 constitute a lateral diode (PIN). When both sides of the first area are provided with the second area and the third area, the lateral diodes (PINs) in the second areas on both sides are connected together in parallel.

本发明第二实施例与第一实施例相比，串联电阻R相对较大，触发电流相对较小。本发明第二实施例的其余部分与第一实施例相同，在此不再赘述。Compared with the first embodiment, the series resistance R of the second embodiment of the present invention is relatively large, and the trigger current is relatively small. The rest of the second embodiment of the present invention is the same as that of the first embodiment, and will not be repeated here.

本发明实施例提供的瞬间电压抑制器件，将硅控整流单元的负极以及二极管的阳极通过第一沟槽结构从器件的背面引出，硅控整流单元的正极电极金属引线没有限制，可以增加硅控整流单元的正极的电极宽度，降低单位面积电流密度，提高芯片面积利用率。In the transient voltage suppression device provided by the embodiment of the present invention, the negative electrode of the silicon-controlled rectifier unit and the anode of the diode are drawn out from the back of the device through the first trench structure. The metal lead of the positive electrode of the silicon-controlled rectifier unit is not limited. The electrode width of the positive electrode of the rectifier unit reduces the current density per unit area and improves the utilization rate of the chip area.

进一步地，第一沟槽结构延伸至半导体衬底中，可以将硅控整流单元的负极以及二极管的阳极从器件的背面引出，可以采用背面键合工艺进行封装，减少打线，降低封装成本。Further, the first trench structure extends into the semiconductor substrate, and the cathode of the silicon-controlled rectifier unit and the anode of the diode can be drawn out from the back of the device, and the back-side bonding process can be used for packaging, reducing wire bonding and packaging costs.

进一步地，硅控整流单元的正极焊盘可以直接形成在硅控整流单元的上方，提高芯片面积利用率。Further, the positive electrode pad of the silicon-controlled rectifier unit can be directly formed above the silicon-controlled rectifier unit, so as to improve the utilization rate of the chip area.

进一步地，阱区外侧形成有第三注入区，以降低硅控整流单元的触发电压。Further, a third injection region is formed outside the well region to reduce the trigger voltage of the silicon-controlled rectifier unit.

进一步地，第二区域中的第二注入区与隔离结构重叠，可以减小PN结面积，降低横向二极管的电容。Further, the second injection region in the second region overlaps with the isolation structure, which can reduce the area of the PN junction and reduce the capacitance of the lateral diode.

本发明实施例还提供了一种瞬间电压抑制器件的制造方法。该方法可以简要地描述如下：Embodiments of the present invention also provide a method for manufacturing a transient voltage suppression device. The method can be briefly described as follows:

在步骤S01中，提供半导体衬底101，所述半导体衬底101具有第一导电类型。所述半导体衬底的电阻率为0.0015Ω·cm～0.01Ω·cm。In step S01, a semiconductor substrate 101 is provided, the semiconductor substrate 101 having a first conductivity type. The resistivity of the semiconductor substrate is 0.0015Ω·cm˜0.01Ω·cm.

在步骤S02中，在半导体衬底101上依次形成隔离层110以及外延层120，所述隔离层110位于所述半导体衬底上101，所述外延层120位于所述隔离层110上，所述外延层120具有第一导电类型或第二导电类型。In step S02, an isolation layer 110 and an epitaxial layer 120 are sequentially formed on the semiconductor substrate 101, the isolation layer 110 is located on the semiconductor substrate 101, the epitaxial layer 120 is located on the isolation layer 110, and the isolation layer 110 is located on the isolation layer 110. The epitaxial layer 120 has the first conductivity type or the second conductivity type.

在步骤S03中，形成多个隔离结构130，所述隔离结构130贯穿所述外延层120并延伸至隔离层110中，所述多个隔离结构130在横向方向上将瞬间电压抑制器件分为多个区域，所述多个区域包括第一区域、第二区域和第三区域，其中，所述第一区域的至少一侧设置有所述第二区域和所述第三区域，所述第二区域与所述第一区域相邻，所述第三区域与所述第二区域相邻并远离所述第一区域，且所述第三区域位于所述瞬间电压抑制器件的最外侧。In step S03 , a plurality of isolation structures 130 are formed, the isolation structures 130 penetrate the epitaxial layer 120 and extend into the isolation layer 110 , and the plurality of isolation structures 130 divide the transient voltage suppression device into multiple a plurality of regions, the plurality of regions include a first region, a second region and a third region, wherein at least one side of the first region is provided with the second region and the third region, the second region An area is adjacent to the first area, the third area is adjacent to and away from the second area, and the third area is located at the outermost side of the transient voltage suppression device.

在步骤S04中，在第一区域的外延层120中形成阱区150。In step S04, a well region 150 is formed in the epitaxial layer 120 of the first region.

在本实施例中，外延层120具有第二导电类型，所述阱区150具有第一导电类型。例如，外延层120为轻掺杂P-型，所述阱区为N型；或者所述外延层120具有第一导电类型，所述阱区150具有第二导电类型。例如，外延层120为轻掺杂N-型，所述阱区150为P型。阱区150的离子注入剂量例如为1E11～5E13cm-2。注入完成后，对阱区150进行退火。In this embodiment, the epitaxial layer 120 has the second conductivity type, and the well region 150 has the first conductivity type. For example, the epitaxial layer 120 is lightly doped P-type, and the well region is N-type; or the epitaxial layer 120 has a first conductivity type, and the well region 150 has a second conductivity type. For example, the epitaxial layer 120 is lightly doped N-type, and the well region 150 is P-type. The ion implantation dose of the well region 150 is, for example, 1E11˜5E13 cm −2 . After the implantation is completed, the well region 150 is annealed.

在步骤S05中，在第一区域中以及第三区域中形成多个第一沟槽141，所述第一沟槽141贯穿所述外延层120、隔离层110并延伸至所述半导体衬底101中。In step S05 , a plurality of first trenches 141 are formed in the first region and in the third region, the first trenches 141 penetrate through the epitaxial layer 120 , the isolation layer 110 and extend to the semiconductor substrate 101 middle.

在本实施例中，当外延层120具有第二导电类型，所述阱区150具有第一导电类型时，所述第一沟槽141形成在阱区150的两侧。即阱区150位于第一沟槽141之间。In this embodiment, when the epitaxial layer 120 has the second conductivity type and the well region 150 has the first conductivity type, the first trenches 141 are formed on both sides of the well region 150 . That is, the well region 150 is located between the first trenches 141 .

或者，当所述外延层120具有第一导电类型，所述阱区150具有第二导电类型时，第一沟槽141贯穿所述阱区150、外延层120、隔离层110并延伸至半导体衬底101中。第一沟槽141延伸至半导体衬底101内的深度为1μm～10μm。Alternatively, when the epitaxial layer 120 has the first conductivity type and the well region 150 has the second conductivity type, the first trench 141 penetrates the well region 150 , the epitaxial layer 120 , the isolation layer 110 and extends to the semiconductor liner Bottom 101. The depth of the first trench 141 extending into the semiconductor substrate 101 is 1 μm˜10 μm.

在步骤S06中，在所述多个第一沟槽141内形成填充材料142，所述填充材料142具有第一导电类型的掺杂剂。填充材料142的掺杂剂通过第一沟槽141的侧壁和底部向外扩散，在第一沟槽141周围形成外扩散区域143。In step S06, a filling material 142 is formed in the plurality of first trenches 141, and the filling material 142 has a dopant of a first conductivity type. The dopant of the filling material 142 is diffused outward through the sidewalls and bottoms of the first trenches 141 to form outdiffusion regions 143 around the first trenches 141 .

在步骤S07中，形成第一注入区151、第二注入区152以及第三注入区153，所述第一注入区151具有第二导电类型，第二注入区152具有第一导电类型。第三注入区153形成在第一区域的阱区150两侧的外延层120中。In step S07, a first implantation region 151, a second implantation region 152 and a third implantation region 153 are formed, wherein the first implantation region 151 has the second conductivity type, and the second implantation region 152 has the first conductivity type. The third implantation region 153 is formed in the epitaxial layer 120 on both sides of the well region 150 of the first region.

所述第一注入区151的离子注入剂量为4E14～2E16cm-2。所述第二注入区152的离子注入剂量为2E15～5E16cm-2。所述第三注入区153的离子注入剂量为4E14～2E16cm-2。The ion implantation dose of the first implantation region 151 is 4E14˜2E16 cm −2 . The ion implantation dose of the second implantation region 152 is 2E15˜5E16 cm −2 . The ion implantation dose of the third implantation region 153 is 4E14˜2E16 cm −2 .

当外延层120具有第二导电类型，所述阱区150具有第一导电类型时，第一注入区151形成在第一区域的阱区150和第二区域的外延层120中；第二注入区152形成在第一区域的阱区150和第二区域的外延层120中。所述第三注入区153具有第二导电类型。When the epitaxial layer 120 has the second conductivity type and the well region 150 has the first conductivity type, the first implantation region 151 is formed in the well region 150 of the first region and the epitaxial layer 120 of the second region; the second implantation region 152 is formed in the well region 150 of the first region and the epitaxial layer 120 of the second region. The third injection region 153 has the second conductivity type.

或者，当所述外延层120具有第一导电类型，所述阱区150具有第二导电类型时，第一注入区151形成在第一区域和第二区域的外延层中；第二注入区152形成在第一区域和第二区域的外延层120中。所述第三注入区153具有第一导电类型。Alternatively, when the epitaxial layer 120 has the first conductivity type and the well region 150 has the second conductivity type, the first implantation region 151 is formed in the epitaxial layers of the first region and the second region; the second implantation region 152 is formed in the epitaxial layer 120 in the first region and the second region. The third injection region 153 has a first conductivity type.

在步骤S08中，对第一注入区151、第二注入区152以及第三注入区153进行退火处理。In step S08 , annealing is performed on the first implanted region 151 , the second implanted region 152 and the third implanted region 153 .

在步骤S09中，在所述外延层120上形成介质层170，并在介质层170中形成接触孔171，以及在所述介质层170上形成第一互连线161及至少一个第二互连线162，所述第一互连线161通过介质层170中的接触孔171与第一区域中的第一注入区151、第二注入区152以及第二区域中的第二注入区152连接。所述每个第二互连线162通过介质层170中的接触孔171与第二区域中的第一注入区151以及第二区域外的第一沟槽结构140连接。In step S09 , a dielectric layer 170 is formed on the epitaxial layer 120 , a contact hole 171 is formed in the dielectric layer 170 , and a first interconnection line 161 and at least one second interconnection are formed on the dielectric layer 170 Line 162, the first interconnect line 161 is connected to the first injection region 151 in the first region, the second injection region 152 and the second injection region 152 in the second region through the contact hole 171 in the dielectric layer 170. Each of the second interconnect lines 162 is connected to the first injection region 151 in the second region and the first trench structure 140 outside the second region through the contact hole 171 in the dielectric layer 170 .

在步骤S10中，对半导体衬底101进行减薄以及背面金属化形成第一电极108。In step S10 , the semiconductor substrate 101 is thinned and backside metallized to form the first electrode 108 .

以上步骤中步骤S04和步骤S05的顺序可以调整，例如，步骤S04可以放在步骤S08之后，步骤S05可以放在步骤S03之后，但并不限于此。The order of step S04 and step S05 in the above steps can be adjusted. For example, step S04 can be placed after step S08, and step S05 can be placed after step S03, but it is not limited thereto.

依照本发明的实施例如上文所述，这些实施例并没有详尽叙述所有的细节，也不限制该发明仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本发明的原理和实际应用，从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明仅受权利要求书及其全部范围和等效物的限制。Embodiments in accordance with the present invention are described above, but these embodiments do not exhaust all the details and do not limit the invention to only the specific embodiments described. Obviously, many modifications and variations are possible in light of the above description. This specification selects and describes these embodiments in order to better explain the principle and practical application of the present invention, so that those skilled in the art can make good use of the present invention and modifications based on the present invention. The present invention is to be limited only by the claims and their full scope and equivalents.

Claims (48)

1. A transient voltage suppression device, comprising:
a semiconductor substrate having a first conductivity type;
the isolation layer is positioned on the semiconductor substrate;
the epitaxial layer is positioned on the isolation layer;
a plurality of isolation structures penetrating the epitaxial layer and extending into the isolation layer, the isolation structures dividing the transient voltage suppression device into a plurality of regions in a lateral direction, the plurality of regions including a first region, a second region and a third region, wherein the second region and the third region are disposed on at least one side of the first region, the second region is adjacent to the first region, the third region is adjacent to the second region and is far away from the first region, and the third region is located at an outermost side of the transient voltage suppression device;
a plurality of first trench structures located in the first region and the third region, penetrating the epitaxial layer and the isolation layer and extending into the semiconductor substrate;
the well region is positioned in the first region and extends from the surface of the epitaxial layer to the direction of the semiconductor substrate;
a first injection region located in the well region and the second region of the first region, having a second conductivity type;
a second injection region, located in the well region of the first region and in the second region, having the first conductivity type;
the third injection region is positioned in the epitaxial layers on two sides of the well region of the first region;
in the well region, the first injection region is positioned at two sides of the second injection region.
2. The transient voltage suppression device of claim 1, wherein the first region comprises at least one thyristor comprising a first transistor, a second transistor, a series resistor, and a clamping diode, and wherein the second region comprises a diode.
3. The transient voltage suppression device of claim 2, wherein when the first region comprises a plurality of scr units, the plurality of scr units are connected together in parallel.
4. The device according to claim 2, wherein when the second region and the third region are provided on both sides of the first region, the diodes in the second region on both sides are connected together in parallel.
5. The tvs device of claim 2, wherein said epitaxial layer has a second conductivity type, said well region has a first conductivity type, and said third implanted region has a second conductivity type.
6. The tvs device of claim 5, wherein said well region extends from a surface of an epitaxial layer into said epitaxial layer, said first trench structure being located on both sides of said well region.
7. The transient voltage suppression device of claim 5 wherein said first implant region and said second implant region are located in the well region of the first region and in the epitaxial layer of the second region.
8. The transient voltage suppression device of claim 6, wherein said first transistor comprises a first implanted region in a well region adjacent to a side of said SCR unit, a well region, and a third implanted region adjacent to a side of said SCR unit; the second triode comprises a well region, an epitaxial layer and an outer diffusion region of the first groove structure, wherein the outer diffusion region is close to one side of the silicon controlled rectifier unit; the clamping diode comprises a well region and a third injection region far away from one side of the silicon-controlled rectifying unit; the diode includes a first implanted region, an epitaxial layer, and a second implanted region in a second region.
9. The tvs device of claim 2, wherein said epitaxial layer has a first conductivity type, said well region has a second conductivity type, and said third implanted region has said first conductivity type.
10. The tvs device of claim 9, wherein said well region extends from a surface of said epitaxial layer into said isolation layer, and wherein said first trench structure extends through said well region and said isolation layer and into said semiconductor substrate.
11. The tvs device of claim 9, wherein said first and second implanted regions are located in the epitaxial layer of the first region and in the epitaxial layer of the second region.
12. The tvs device of claim 10, wherein said first transistor comprises a first implanted region adjacent to a side of said scr unit, an epitaxial layer, and a well region adjacent to a side of said scr unit; the second triode comprises an epitaxial layer, a well region close to one side of the silicon control rectifying unit and an outer diffusion region of the first groove structure close to one side of the silicon control rectifying unit; the clamping diode comprises a well region and an epitaxial layer, wherein the well region is far away from one side of the silicon control rectifying unit; the diode includes a first implanted region, an epitaxial layer, and a second implanted region in a second region.
13. The transient voltage suppression device of claim 8 or 12 wherein the first trench structure in the first region is an emitter of the second transistor and is electrically connected to the semiconductor substrate via the first trench structure; an anode of the diode is electrically connected to the semiconductor substrate via the first trench structure in the third region.
14. The transient voltage suppression device of claim 1 wherein said first trench structure extends into said semiconductor substrate to a depth of between 1 μm and 10 μm.
15. The tvs device of claim 1, wherein said first trench structure comprises a first trench and a fill material in said first trench, said fill material being polysilicon or amorphous silicon, wherein said fill material has a dopant of said first conductivity type.
16. The tvs device of claim 15, wherein said dopant of said fill material out-diffuses through sidewalls and bottom of said first trench to form an out-diffusion region around said first trench.
17. The device according to claim 1, wherein the second implantation region in the second region is disposed with or without overlapping with the adjacent isolation structure.
18. The transient voltage suppression device of claim 1, wherein said first conductivity type is P-type, said second conductivity type is N-type, said first transistor is PNP transistor, said second transistor is NPN transistor, and said diode is PIN transistor; or the first conduction type is an N type, the second conduction type is a P type, the first triode is an NPN tube, the second triode is a PNP tube, and the diode is an NIP tube.
19. The transient voltage suppression device of claim 1, further comprising:
the first electrode is positioned on the surface of the semiconductor substrate far away from the epitaxial layer;
a first interconnect line connecting the first implant region in the first area, the second implant region, and the second implant region in the second area;
at least one second interconnect line respectively connecting the first implant region in the second region and the first trench structure in the third region.
20. The device of claim 19, wherein the first interconnect line is connected to one of a power supply and ground, and at least one of the second interconnect lines is connected to the other of the power supply and ground via the first trench structure, the semiconductor substrate, the first electrode.
21. The tvs device of claim 15, wherein said semiconductor substrate is a heavily doped structure, said epitaxial layer is a lightly doped structure, said fill material in said first trench is a heavily doped structure, said first implanted region is a heavily doped structure, said second implanted region is a heavily doped structure, and said third implanted region is a heavily doped structure.
22. The device according to claim 1, wherein the semiconductor substrate has a resistivity of 0.0015 Ω -cm to 0.01 Ω -cm.
23. The transient voltage suppression device of claim 1, wherein said epitaxial layer has a resistivity of 10 Ω -cm to 200 Ω -cm and a thickness of 1 μm to 10 μm.
24. The tvs device of claim 1, wherein said isolation structure comprises a second trench and an insulating material filled in said second trench, said second trench extending through said epitaxial layer and into said isolation layer.
25. A method of manufacturing a transient voltage suppression device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first conduction type;
sequentially forming an isolation layer and an epitaxial layer on the semiconductor substrate;
forming a plurality of isolation structures, wherein the isolation structures penetrate through the epitaxial layer and extend into the isolation layer, the isolation structures divide the transient voltage suppression device into a plurality of regions in the transverse direction, the plurality of regions include a first region, a second region and a third region, the second region and the third region are arranged on at least one side of the first region, the second region is adjacent to the first region, the third region is adjacent to the second region and is far away from the first region, and the third region is located at the outermost side of the transient voltage suppression device;
forming a plurality of first trench structures in the first region and the third region, wherein the plurality of first trench structures penetrate through the epitaxial layer and the isolation layer and extend into the semiconductor substrate;
forming a well region in the first region, wherein the well region extends from the surface of the epitaxial layer towards the direction of a semiconductor substrate;
forming a first implant region in the first region and the second region, the first implant region having the second conductivity type,
forming a second implanted region in the first region and the second region, the second implanted region having the first conductivity type;
forming third injection regions in the epitaxial layer on two sides of the well region of the first region;
in the well region, the first injection region is positioned at two sides of the second injection region.
26. The method of claim 25, wherein at least one scr unit is formed in the first region, the scr unit includes a first transistor, a second transistor, a series resistor, and a clamp diode, and the diode is formed in the second region.
27. The method of claim 26, wherein when the plurality of scr units are formed in the first region, the plurality of scr units are connected together in parallel.
28. The manufacturing method according to claim 26, wherein when the second region and the third region are provided on both sides of the first region, the diodes in the second regions on both sides are connected together in parallel.
29. The method of manufacturing of claim 26 wherein the epitaxial layer has a second conductivity type, the well region has a first conductivity type, and the third implanted region has the second conductivity type.
30. The method of claim 29, wherein the well region extends from a surface of an epitaxial layer into the epitaxial layer, and the first trench structure is located on both sides of the well region.
31. The method of manufacturing of claim 29 wherein the first and second implant regions are located in the well region of the first region and in the epitaxial layer of the second region.
32. The method of claim 30, wherein the first transistor comprises a first implanted region in the well region near a side of the scr unit, a well region, and a third implanted region in the well region near a side of the scr unit; the second triode comprises a well region, an epitaxial layer and an outer diffusion region of the first groove structure, wherein the outer diffusion region is close to one side of the silicon controlled rectifier unit; the clamping diode comprises a well region and a third injection region far away from one side of the silicon controlled rectifier unit; the diode includes a first implanted region, an epitaxial layer, and a second implanted region in a second region.
33. The method of manufacturing of claim 26 wherein the epitaxial layer has a first conductivity type, the well region has a second conductivity type, and the third implanted region has the first conductivity type.
34. The method of claim 33, wherein the well region extends from a surface of the epitaxial layer into the isolation layer, and wherein the first trench structure extends through the well region, the epitaxial layer and the isolation layer and into the semiconductor substrate.
35. The method of manufacturing of claim 33 wherein the first and second implanted regions are located in the epitaxial layer of the first region and in the epitaxial layer of the second region.
36. The method of claim 34, wherein the first transistor comprises a first implanted region near one side of the scr unit, an epitaxial layer, and a well region near one side of the scr unit; the second triode comprises an epitaxial layer, a well region close to one side of the silicon control rectifying unit and an outer diffusion region of the first groove structure close to one side of the silicon control rectifying unit; the clamping diode comprises a well region and an epitaxial layer, wherein the well region is far away from one side of the silicon control rectifying unit; the diode includes a first implanted region in the second region, an epitaxial layer, and a second implanted region.
37. The manufacturing method according to claim 32 or 36, wherein the first trench structure in the first region is an emitter of the second transistor and is electrically connected to the semiconductor substrate via the first trench structure; an anode of the diode is electrically connected to the semiconductor substrate via the first trench structure in the third region.
38. The method of manufacturing of claim 25, wherein the first trench structure extends into the semiconductor substrate to a depth of 1 μ ι η to 10 μ ι η.
39. The method of manufacturing of claim 25, wherein forming a first trench structure comprises:
forming a first trench; and
and arranging a filling material in the first groove, wherein the filling material is polysilicon or amorphous silicon, and the filling material is provided with a dopant of the second conduction type.
40. The method of claim 39 wherein the dopant of the fill material out-diffuses through the sidewalls and bottom of the first trench to form an out-diffusion region around the first trench.
41. The method of claim 25, wherein the second implanted region in the second region is disposed with or without overlapping with an adjacent isolation structure.
42. The manufacturing method according to claim 25, wherein the first conductivity type is P-type, the second conductivity type is N-type, the first transistor is a PNP transistor, the second transistor is an NPN transistor, and the diode is a PIN transistor; or the first conduction type is an N type, the second conduction type is a P type, the first triode is an NPN tube, the second triode is a PNP tube, and the diode is an NIP tube.
43. The method of manufacturing of claim 25, further comprising:
forming a first electrode on the surface of the semiconductor substrate far away from the epitaxial layer;
forming a first interconnection line and at least one second interconnection line, wherein the first interconnection line is connected with the first injection area in the first area, the second injection area in the first area and the second injection area in the second area; at least one of the second interconnect lines is connected to the first implant region in the second region and the first trench structure in the third region, respectively.
44. The method of manufacturing of claim 43, further comprising:
the first interconnection line is connected to one of a power supply and a ground, and at least one of the second interconnection lines is connected to the other of the power supply and the ground via the first trench structure, the semiconductor substrate, and the first electrode.
45. The method of claim 39, wherein the semiconductor substrate is a heavily doped structure, the epitaxial layer is a lightly doped structure, the fill material in the first trench is a heavily doped structure, the first implanted region is a heavily doped structure, the second implanted region is a heavily doped structure, and the third implanted region is a heavily doped structure.
46. The manufacturing method according to claim 25, wherein the resistivity of the semiconductor substrate is 0.0015 Ω -cm to 0.01 Ω -cm.
47. The method of claim 25, wherein the epitaxial layer has a resistivity of 10 Ω -cm to 200 Ω -cm and a thickness of 3 μm to 10 μm.
48. The method of manufacturing of claim 25, wherein forming an isolation structure comprises:
forming a plurality of second trenches penetrating the epitaxial layer and extending into the isolation layer;
and filling an insulating material in the second trench.
CN202210215617.XA 2022-03-07 2022-03-07 Transient voltage suppression device and method of manufacturing the same Pending CN114664817A (en)

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