KR20090076659A - Plasma display panel - Google Patents

Abstract

A plasma display panel is provided to prevent a spread of a sealant in a barrier rib by forming a groove part on the barrier rib. A front substrate(101) and a rear substrate(111) are crossed each other. A sealant(21) is provided according to a groove part(31). The groove part is formed on a bottom dielectric layer(115). A barrier rib(112) is positioned in a space between the front substrate and the rear substrate. An address electrode(113) intersects with the second electrode in a discharge cell. A first electrode and the second electrode are formed on the front substrate. A top dielectric layer(104) is arranged on a top part of the front substrate. A protecting layer is arranged on the top dielectric layer.

Description

Plasma display panel {Plasma display panel}

The present invention relates to a plasma display panel having an improved sealing structure.

A plasma display panel (hereinafter, PDP) is a display device in which ultraviolet rays emitted from a plasma formed by gas discharge excite a phosphor layer, and implement an image by using visible light generated at this time. Such PDPs have been spotlighted as next-generation flat panel displays because they can be composed of high resolution large screens.

The general structure of the PDP is a three-electrode surface discharge type structure, in which a pair of electrodes are formed on opposite surfaces of the front substrate to face each other, and a rear substrate spaced from the front substrate includes an address electrode. Such electrodes are formed corresponding to each discharge cell.

In the PDP, millions of unit discharge cells are arranged in a matrix form. These discharge cells select the discharge cells that are turned on and the discharge cells that are not turned on by using the storage characteristics of wall charges, and display an image by discharging the selected discharge cells.

In the conventional PDP, the front substrate and the rear substrate are sealed with a sealing material, and the two substrates are bonded by applying a sealing material along a portion where the front substrate and the rear substrate are crossed.

On the other hand, a sealing barrier rib is formed at the edge of the PDP so that the sealing material does not spread inside the effective area where the image is displayed, so that the sealing material does not spread to the inside of the effective area and the flow is blocked by the sealing wall.

However, since the sealing material becomes hard after the sealing material is fired, there is a problem that noise is generated while the sealing material collides with the sealing wall when the PDP is driven.

The present invention has been made in view of the above technical background, and provides a plasma display panel which prevents the sealing material from spreading into the effective area without using the conventional sealing wall.

In order to achieve the above object, an embodiment of the present invention includes a front substrate, a rear substrate facing the front substrate, a partition wall partitioning a space between the front substrate and the rear substrate to form a discharge cell, and facing the discharge cell. A first electrode and a second electrode, a third electrode formed to intersect the second electrode in the discharge cell, a lower dielectric layer covering the third electrode, the front substrate and the back substrate where the lower substrate is staggered. Provided is a plasma display panel including a groove portion formed in a dielectric layer and a sealing material formed over the groove portion.

Here, the groove portion is preferably formed inward toward the partition wall than the boundary line extending the front substrate.

In addition, the groove portion may be formed in plural between the partition wall and the boundary line.

In addition, the groove portion is formed to a depth of 90% or less of the thickness of the lower dielectric layer, or has a width of 5mm or less.

In addition, the present invention may include an upper dielectric layer covering the first electrode and the second electrode, and a groove portion may be further formed to face the groove portion of the upper dielectric layer.

In this case, the groove portion formed in the upper dielectric layer and the groove portion formed in the lower dielectric layer are preferably arranged alternately.

According to this invention, since the groove part is formed along with the application of the sealing material, it is possible to prevent the sealing material from spreading into the partition wall even without using the sealing wall. Therefore, it is possible to solve the noise problem caused by the sealing material hit the wall or partition.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

1 is a diagram illustrating a state in which two substrates of a plasma display are bonded together according to an exemplary embodiment of the present invention. 2 is an exploded perspective view showing an enlarged portion "A" of FIG. 1.

1 and 2, in the plasma display panel according to the exemplary embodiment, the front substrate 101 and the rear substrate 111 are alternately arranged. The sealing material 21 is provided along the groove 31 along the portion where the front substrate 101 and the rear substrate 111 are staggered, thereby sealing a gap between the front substrate 101 and the rear substrate 111. The front substrate 101 and the rear substrate 111 are coupled to each other.

Here, the groove 31 is formed in the lower dielectric layer 115 along the portion where the front substrate 101 and the rear substrate 111 are staggered, and serves to block the flow of the sealing material 21. Meanwhile, in FIG. 1, the groove 31 is exemplified as being formed over the entire panel. However, the groove 31 may be selectively formed only on the long axis or the short axis of the panel. As such, the groove portion 31 can be deformed as necessary.

 In addition, the space between the front substrate 101 and the rear substrate 111 partitions the discharge cells 18 constituting the sub-pixel which is the minimum unit in which the partition wall 112 is positioned.

The plasma display panel may be divided into a display area DA displaying an image including the discharge cells 18 and a non-display area UD in which no image is displayed around the display area DA. Here, the sealing material 21 and the groove part 31 are located in the non-display area UD.

On the other hand, the discharge cells for displaying an image can be formed in the following structure.

The first electrode 103 and the second electrode 102 are arranged side by side along the discharge cell 18, and the address electrode 113 intersects the second electrode 102 in the discharge cell 18. It is arranged.

The first electrode 103 and the second electrode 102 are formed of the front substrate 101, and the address electrode 113 is formed on the rear substrate 111.

An upper dielectric layer 104 filling the second electrode 102 and the first electrode 103 is disposed on the front substrate 101 on which the second electrode 102 and the first electrode 103 are disposed.

The upper dielectric layer 104 insulates between the second electrode 102 and the first electrode 103, and a protective layer 105 may be disposed over the upper dielectric layer 104 to facilitate a discharge condition. The protective layer 105 may include a material having a high secondary electron emission coefficient, such as magnesium oxide (MgO).

In addition, an electrode, for example, an address electrode 113 is disposed on the rear substrate 111, and the rear substrate 111 on which the address electrode 113 is disposed covers the address electrode 113 and insulates the address electrode 113. A dielectric layer, such as lower dielectric layer 115, may be disposed. The lower dielectric layer 115 is provided with a groove portion 31 for fixing the sealing material 21.

On top of the lower dielectric layer 115, a discharge space, that is, a partition wall 112 such as a stripe type, a well type, a delta type, a honeycomb type, etc., which partitions a discharge cell, may be disposed. Can be. The barrier rib 112 may be provided with a red (R), green (G), and blue (B) discharge cell between the front substrate 101 and the rear substrate 111. In addition, in addition to the red (R), green (G), and blue (B) discharge cells, white (W) or yellow (Yellow: Y) discharge cells may be further provided.

In the discharge cell partitioned by the partition wall 112, a discharge gas such as xenon (Xe), neon (Ne), or the like may be filled.

In addition, a phosphor layer 114 that emits visible light for image display may be disposed in the discharge cell partitioned by the partition wall 112. For example, a first phosphor layer emitting red (R) light, a second phosphor layer emitting blue (B) light, and a third phosphor layer emitting green (G) light are disposed. Can be. In addition to the red (R), green (G), and blue (B) light, it is also possible to further arrange other phosphor layers emitting white (W) light or yellow (Yellow: Y) light.

In addition, the thickness of the phosphor layer 114 in at least one of the red (R), green (G), and blue (B) discharge cells may be different from other discharge cells. For example, a phosphor layer of a green (G) discharge cell, that is, a phosphor layer in a third phosphor layer or a blue (B) discharge cell, that is, a thickness of a second phosphor layer in a red (R) discharge cell, Ie thicker than the thickness of the first phosphor layer. Here, the thickness of the third phosphor layer may be substantially the same or different from the thickness of the second phosphor layer.

In addition, in the plasma display panel 100 according to an exemplary embodiment, the widths of the red (R), green (G), and blue (B) discharge cells may be substantially the same, but the red (R) and green (G) colors may be substantially the same. And at least one of the blue (B) discharge cells may be different from the widths of the other discharge cells.

For example, the width of the red (R) discharge cell is the smallest, and the width of the green (G) and blue (B) discharge cells can be made larger than the width of the red (R) discharge cell. Here, the width of the green (G) discharge cell may be substantially the same as or different from the width of the blue (B) discharge cell.

The width of the phosphor layer 114 disposed in the discharge cell is then changed in relation to the width of the discharge cell. For example, the width of the second phosphor layer disposed in the blue (B) discharge cell is wider than the width of the first phosphor layer disposed in the red (R) discharge cell, and the third disposed in the green (G) discharge cell. The width of the phosphor layer may be wider than the width of the first phosphor layer disposed in the red (R) discharge cell, thereby improving the color temperature characteristics of the image implemented.

In addition, the plasma display panel 100 according to an exemplary embodiment of the present invention may have not only the structure of the partition wall 112 shown in FIG. 2 but also the structure of the partition wall having various shapes. For example, the partition wall 112 includes a first partition wall 112b and a second partition wall 112a, where the height of the first partition wall 112b and the height of the second partition wall 112a are different from each other. Etc. are possible.

In the case of the differential partition wall structure, the height of the first partition wall 112b among the first partition wall 112b or the second partition wall 112a may be lower than the height of the second partition wall 112a.

In addition, although the red (R), green (G), and blue (B) discharge cells are each shown and described as being arranged on the same line in FIG. 1, they may be arranged in other shapes. For example, a delta type arrangement in which red (R), green (G) and blue (B) discharge cells are arranged in a triangular shape is also possible. In addition, the shape of the discharge cell is not only rectangular but also various polygonal shapes such as pentagon and hexagon.

In addition, in FIG. 2, only the case where the partition wall 112 is formed on the rear substrate 111 is illustrated, but the partition wall 112 may be disposed on at least one of the front substrate 101 and the rear substrate 111.

Hereinafter, the front substrate 101 and the rear substrate 111 are bonded to each other in detail with reference to FIGS. 3 and 4. FIG. 3 is an enlarged view of portion “B” of FIG. 1, and FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. 1.

3 and 4, the rear substrate 111 protrudes more than the front substrate 101. Then, the sealing material 21 is applied along the boundary line between the front substrate 101 and the rear substrate 111, so that the two substrates 101 and 111 are sealed while sealing between the front substrate 101 and the rear substrate 111. FIG. I'm joining.

On the other hand, an address electrode 113 is formed on the rear substrate 111, and the address electrode 113 extends further than the lower dielectric layer 113 covering the address electrode 113 to drive the panel. It has a structure that is connected to.

In addition, the lower dielectric layer 113 has a groove 31 formed inward adjacent to the boundary BL between the front substrate 101 and the rear substrate 111.

In one embodiment of the present invention, since the groove portion 31 is located in the region to which the sealing material 21 is applied, the sealing material 21 can be prevented from flowing toward the partition wall 112.

More specifically, the process of bonding the front substrate 101 and the rear substrate 111 includes applying a paste-like sealing material to the rear substrate 111 and then plasticizing it to melt the sealing material.

Therefore, the molten sealing material can flow toward the partition because it is fluid in the intermediate state between the sol and the gel. Since the groove 31 is located between the partition 112 and the sealing material 21, the flow of the sealing material 21 is prevented. This prevents the sealing material from spreading toward the bulkhead.

On the other hand, the space between the partition 112 and the groove portion 31 is spaced apart by a certain distance can more effectively block the flow of the sealing material. The distance between the partition and the groove is determined in consideration of the following points. First, the viscosity of the sealant must be taken into account, and secondly, when the molten sealant is cured in the atmosphere, the rate of change of state over time should also be considered.

As such, when the partition wall and the groove portion fall in the critical range, the flow of the sealing material may be blocked by the groove portion first, and the flow of the sealing material is blocked by the separation distance so that the sealing material does not touch the partition wall. do.

As described above, according to the exemplary embodiment of the present invention, since the sealing member does not harden while touching the partition wall even without the sealing wall, the noise problem as before can be solved.

Meanwhile, the depth h2 of the groove 21 may be 90% or less than the thickness h1 of the lower dielectric layer 113. Below the groove 21, the address electrode 115 extends outside the boundary BL to form a terminal. Therefore, when 90% or more, the address electrode 115 is exposed to the outside of the dielectric layer, or there is a problem that the disconnection.

In addition, the groove portion 21 is preferably formed with a width w1 of 5 mm or less. Generally, since the sealing material 21 plasticized at about 400 degreeC has fluidity in the range of about 5 mm, it is preferable to make the groove part 21 in such a range.

Meanwhile, FIG. 5 illustrates that the groove 33 is formed in the upper dielectric layer 104.

The grooves 33 formed in the upper dielectric layer 104 may be formed to face the grooves 31 of the lower dielectric layer 115 as shown in the figure, or may be alternately formed. That is, the groove 33 formed in the upper dielectric layer 104 and the groove 31 formed in the lower dielectric layer 115 may be located on the same line or may be formed off the same line.

6 illustrates that a plurality of grooves 31 and 33 are formed. Referring to FIG. 6, a plurality of grooves 31a to 31c and 33a to 33c are formed between the partition wall 112 and the boundary line BL. Here, the boundary line BL extends the end of the front substrate 101.

In this way, when the groove portion is formed in a large number, the sealing member 21 is prevented from spreading more effectively than one when the flow is interrupted by the groove portions 31 and 33 step by step.

On the other hand, it is preferable that the groove parts 31 and 33 which face each other with the sealing material 21 interposed are arrange | positioned alternately. As such, when the grooves 31 and 33 are alternately arranged, the sealing material 21 is interrupted step by step to the grooves 31 and 33 respectively positioned at the top and the bottom thereof, which is more effective in restricting the flow.

As described above, the rear substrate 111 and the front substrate 101 including the groove portion 31 are coupled as follows.

First, the groove 31 may be formed together while patterning the partition wall. That is, when the barrier ribs are formed by etching, the groove portion 31 can be formed by simultaneously exposing and developing the barrier ribs and the lower dielectric layer 115. Also, even when the partition wall is formed by sand blasting, the groove portion may be formed by sanding the lower dielectric layer 115 together while sanding the partition wall.

Thus, after the groove part 31 is made, the sealing material of a paste state is applied along a groove part. At this time, it is better to apply the paste adjacent to the outside rather than just above the groove.

Next, the paste is plasticized at a temperature of 400 ° C. to melt the sealing material. The molten sealing material is prevented from spreading to the partition wall 112 because the flow is blocked by neighboring grooves.

Next, the front substrate 101 is placed on the rear substrate 111 to align the rear substrate 111 and the front substrate 101, and then the front substrate 101 and the rear substrate 111 are hardened by baking the sealing material. ) Will be combined.

 Hereinafter, the driving of the plasma display panel according to the exemplary embodiment of the present invention configured as described above will be described.

7 is a view for explaining an example of the operation of the plasma display panel according to an embodiment of the present invention. FIG. 7 illustrates an example of a method of operating a plasma display panel according to an embodiment of the present invention. The present invention is not limited to FIG. 7, and the plasma display panel according to an embodiment of the present invention is described. The method of operation may be variously changed.

Referring to FIG. 7, a reset signal may be supplied to the second electrode in the reset period for initialization. The reset signal may include a ramp-up signal and a ramp-down signal.

For example, in the set-up period, the voltage gradually increases from the second voltage V2 to the third voltage V3 after rapidly increasing from the first voltage V1 to the second voltage V2 with the second electrode. Rising ramp signal may be supplied. Here, the first voltage V1 may be a voltage of the ground level GND.

In this setup period, a weak dark discharge, that is, setup discharge, occurs in the discharge cell by the rising ramp signal. By this setup discharge, some wall charges can be accumulated in the discharge cells.

In the set-down period after the setup period, the rising ramp signal may be supplied to the second electrode after the rising ramp signal in the opposite polarity direction.

Here, the falling ramp signal may gradually fall from the peak voltage of the rising ramp signal, that is, the fourth voltage V4 lower than the third voltage V3 to the fifth voltage V5.

As the falling ramp signal is supplied, a weak erase discharge, that is, a setdown discharge, occurs in the discharge cell. By this set-down discharge, wall charges such that address discharge can be stably generated in the discharge cells remain uniformly.

In the address period after the reset period, a scan bias signal that substantially maintains the lowest voltage of the falling ramp signal, that is, a voltage higher than the fifth voltage V5, for example, the sixth voltage V6, is supplied to the second electrode.

In addition, a scan signal falling from the scan bias signal may be supplied to the second electrode.

Meanwhile, the pulse width of the scan signal Scan supplied to the second electrode in the address period of at least one subfield may be different from the pulse width of the scan signal of another subfield. For example, the width of the scan signal in the subfield located later in time may be smaller than the width of the scan signal in the preceding subfield. In addition, the reduction of the scan signal width according to the arrangement order of the subfields can be made gradually, such as 2.6 Hz (microseconds), 2.3 Hz, 2.1 Hz, 1.9 Hz, or 2.6 Hz, 2.3 Hz, 2.3 Hz, 2.1 Hz. .... 1.9 ㎲, 1.9 ㎲ and so on.

As such, when the scan signal is supplied to the second electrode, the data signal may be supplied to the address electrode corresponding to the scan signal.

When the scan signal and the data signal are supplied, an address discharge may be generated in the discharge cell to which the data signal is supplied while the voltage difference between the scan signal and the data signal and the wall voltage generated by the wall charges generated in the reset period are added. .

Here, the sustain bias signal may be supplied to the first electrode to prevent the address discharge from becoming unstable due to the interference of the first electrode in the address period.

The sustain bias signal can keep the sustain bias voltage Vz smaller than the voltage of the sustain signal supplied in the sustain period and larger than the voltage of the ground level GND.

Subsequently, in the sustain period for displaying an image, a sustain signal may be supplied to at least one of the second electrode and the first electrode. For example, a sustain signal may be alternately supplied to the second electrode and the first electrode.

When such a sustain signal is supplied, the discharge cell selected by the address discharge is sustained discharge between the second electrode and the first electrode when the sustain signal is supplied while the wall voltage in the discharge cell and the sustain voltage Vs of the sustain signal are added. , Display discharge may occur.

Meanwhile, in the at least one subfield, a plurality of sustain signals are supplied in the sustain period, and the pulse width of at least one sustain signal of the plurality of sustain signals may be different from the pulse widths of other sustain signals. For example, the pulse width of the sustain signal that is supplied first of the plurality of sustain signals may be larger than the pulse width of other sustain signals. Then, the sustain discharge can be more stabilized.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited thereto, and various modifications or changes can be made within the scope of the claims and the detailed description of the invention and the accompanying drawings. In addition, it is natural that it belongs to the scope of the present invention.

1 is a diagram illustrating a state in which two substrates of a plasma display are bonded together according to an exemplary embodiment of the present invention.

FIG. 2 is an exploded perspective view showing an enlarged portion "A" of FIG. 1.

3 is an enlarged view of a portion “B” of FIG. 1.

4 is a cross-sectional view taken along the line IV-IV of FIG. 1.

5 is a view showing that a groove is formed in the upper dielectric layer.

6 is a view illustrating that a plurality of grooves are formed.

7 is a view for explaining an example of the operation of the plasma display panel according to an embodiment of the present invention.

Claims (7)

Front substrate; A rear substrate facing the front substrate; A partition wall partitioning a space between the front substrate and the rear substrate to form a discharge cell; First and second electrodes facing each other in the discharge cell; A third electrode formed to cross the second electrode in the discharge cell; A lower dielectric layer covering the third electrode; A groove portion formed in the lower dielectric layer to cross the front substrate and the rear substrate; And, Sealing material formed over the groove portion Plasma display panel comprising a. The method of claim 1, And the groove portion is formed inward toward the partition wall than a boundary line extending from the front substrate. The method of claim 2, And a plurality of grooves formed between the barrier ribs and the boundary line. The method of claim 1, And the groove portion is formed to a depth of 90% or less of the thickness of the lower dielectric layer. The method of claim 1, And the groove portion has a width of 5 mm or less. The method according to any one of claims 1 to 5, An upper dielectric layer covering the first electrode and the second electrode, And a groove portion formed to face the groove portion of the upper dielectric layer. The method of claim 6, And a groove portion formed in the upper dielectric layer and a groove portion formed in the lower dielectric layer are alternately disposed.

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