KR20090072090A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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KR20090072090A
KR20090072090A KR1020070140082A KR20070140082A KR20090072090A KR 20090072090 A KR20090072090 A KR 20090072090A KR 1020070140082 A KR1020070140082 A KR 1020070140082A KR 20070140082 A KR20070140082 A KR 20070140082A KR 20090072090 A KR20090072090 A KR 20090072090A
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South Korea
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film
semiconductor device
forming
pattern
manufacturing
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KR1020070140082A
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Korean (ko)
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김석중
김정근
조선영
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주식회사 하이닉스반도체
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Priority to KR1020070140082A priority Critical patent/KR20090072090A/en
Publication of KR20090072090A publication Critical patent/KR20090072090A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A manufacturing method of a semiconductor device is provided to prevent exposure of a top part of a transistor pattern during a flattening process by forming a buffer film as an anti-etch film of the flattening process. A cell gate pattern(101) and a transistor pattern(103) are formed on a semiconductor substrate(100) which is divided into a cell region and a peripheral region. A protecting film is formed on a whole structure including the cell gate pattern and the transistor pattern. A buffer film(106) is formed on a whole structure including the protecting film. An insulation film(107,108) is formed on a whole structure including the buffer film. A flattening process is performed in order to expose the buffer film. A spacer is formed on a side wall of the transistor pattern before forming the protecting film.

Description

반도체 소자의 제조 방법{Method of manufacturing semiconductor device}Method of manufacturing semiconductor device

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 게이트 패턴을 포함한 전체 구조 상에 층간 절연막을 형성하는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which an interlayer insulating film is formed on an entire structure including a gate pattern.

도 1은 종래 기술에 따른 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도이다.1 is a cross-sectional view of a device for explaining a method of manufacturing a semiconductor device according to the prior art.

도 1을 참조하면, 반도체 기판(10) 상에 셀 영역에 셀 게이트 패턴(11), 선택 트랜지스터 패턴(12), 주변 회로 영역에 트랜지스터 패턴(13)을 형성한다. 이 후, 선택 트랜지스터 패턴(12) 및 트랜지스터 패턴(13) 측벽에 스페이서(14)을 형성한 후, 전체 구조 상에 SAC 질화막(15)을 형성한다. 이 후, SAC 질화막(15)을 포함한 전체 구조 상에 절연막(16)을 채운 후, SAC 질화막(15)이 노출되도록 평탄화 공정을 실시한다.Referring to FIG. 1, a cell gate pattern 11, a selection transistor pattern 12, and a transistor pattern 13 are formed in a cell region on a semiconductor substrate 10. Thereafter, the spacers 14 are formed on the sidewalls of the selection transistor pattern 12 and the transistor pattern 13, and then the SAC nitride film 15 is formed over the entire structure. Thereafter, after filling the insulating film 16 over the entire structure including the SAC nitride film 15, the planarization process is performed so that the SAC nitride film 15 is exposed.

종래 기술에 따른 반도체 소자의 제조 공정은 SAC 질화막(15)이 얇게 형성되 고, 셀 영역의 셀 게이트 패턴(11), 및 선택 트랜지스터 패턴(12)의 높이보다 주변 회로 영역의 트랜지스터 패턴(13)의 높이가 낮게 형성되므로, 평탄화 공정시 주변 회로 영역의 트랜지스터 패턴(13) 상부에 형성된 SAC 질화막(15)이 완전히 제거되어 트랜지스터 패턴(12)의 상부가 노출되는 문제점이 발생할 수 있다.In the manufacturing process of the semiconductor device according to the related art, the SAC nitride film 15 is thinly formed, and the transistor pattern 13 of the peripheral circuit region 13 is greater than the height of the cell gate pattern 11 and the selection transistor pattern 12 of the cell region. Since the height is low, the SAC nitride film 15 formed on the transistor pattern 13 in the peripheral circuit region may be completely removed during the planarization process, thereby causing a problem in that the upper portion of the transistor pattern 12 is exposed.

도 2는 종래 기술에 따른 반도체 소자의 제조 공정 중 고전압 영역(HV), 저전압 영역(HV)의 트랜지스터 상부가 평탄화 공정시 노출되어 손상을 받은 사진을 나타낸다.FIG. 2 is a photo of the semiconductor device according to the related art, in which the upper portion of the transistors in the high voltage region HV and the low voltage region HV are exposed and damaged during the planarization process.

본 발명이 이루고자 하는 기술적 과제는 반도체 소자의 SAC 보호막을 형성한 후, 후속 평탄화 공정의 식각 방지막으로 버퍼막을 형성함으로써, 후속 층간 절연막 형성 후 평탄화 공정시 트랜지스터 패턴의 상부가 노출되는 것을 방지할 수 있는 반도체 소자의 제조 방법을 제공하는 데 있다.The technical problem to be achieved by the present invention is to form a SAC protective film of the semiconductor device, and then to form a buffer film as an etch stop layer of the subsequent planarization process, it is possible to prevent the upper portion of the transistor pattern is exposed during the planarization process after the formation of the subsequent interlayer insulating film There is provided a method for manufacturing a semiconductor device.

본 발명의 일실시 예에 따른 반도체 소자의 제조 방법은 주변 회로 영역과 셀 영역으로 구분되는 반도체 기판 상에 셀 게이트 패턴 및 트랜지스터 패턴을 형성하는 단계와, 상기 셀 게이트 패턴 및 상기 트랜지스터 패턴을 포함한 전체 구조 상에 SAC 보호막을 형성하는 단계와, 상기 SAC 보호막을 포함한 전체 구조 상에 버퍼막을 형성하는 단계와 상기 버퍼막을 포함한 전체 구조 상에 절연막을 형성하는 단계, 및 상기 버퍼막이 노출되도록 평탄화 공정을 실시하는 단계를 포함한다.A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a cell gate pattern and a transistor pattern on a semiconductor substrate divided into a peripheral circuit region and a cell region, and including the cell gate pattern and the transistor pattern. Forming a SAC protective film on the structure, forming a buffer film on the entire structure including the SAC protective film, forming an insulating film on the entire structure including the buffer film, and performing a planarization process to expose the buffer film. It includes a step.

상기 SAC 보호막을 형성하기 전에 상기 트랜지스터 패턴 측벽에 스페이서를 형성하는 단계를 더 포함한다.The method may further include forming spacers on sidewalls of the transistor pattern before forming the SAC passivation layer.

상기 SAC 보호막은 질화막으로 형성한다. 상기 SAC 보호막은 200 내지 500Å의 두께로 형성한다.The SAC protective film is formed of a nitride film. The SAC protective film is formed to a thickness of 200 to 500 kPa.

상기 버퍼막은 SiH4/O2 가스를 이용하여 형성한다. 상기 버퍼막은 상기 SiH4/O2 가스 유량 비율을 0.75 : 1 이상, 바람직하게는 0.75 : 1 내지 1 :1 로 하여 형성한다.The buffer film is formed using SiH 4 / O 2 gas. The buffer film is formed with the SiH 4 / O 2 gas flow rate ratio of 0.75: 1 or more, preferably 0.75: 1 to 1: 1.

상기 절연막은 SiH4/O2 가스를 이용하여 형성한다. 상기 절연막은 상기 SiH4/O2 가스 유량 비율을 0.75 : 1 이하, 바람직하게는 0.5 : 1 내지 0.75 :1 로 하여 형성한다.The insulating film is formed using SiH 4 / O 2 gas. The insulating film is formed by setting the SiH 4 / O 2 gas flow rate ratio to 0.75: 1 or less, preferably 0.5: 1 to 0.75: 1.

상기 평탄화 공정의 식각 선택비가 상기 버퍼막보다 상기 절연막이 높다.An etching selectivity of the planarization process is higher than that of the buffer layer.

본 발명의 일실시 예에 따르면, 반도체 소자의 SAC 보호막을 형성한 후, 후속 평탄화 공정의 식각 방지막으로 버퍼막을 형성함으로써, 후속 층간 절연막 형성 후 평탄화 공정시 트랜지스터 패턴의 상부가 노출되는 것을 방지할 수 있다.According to one embodiment of the present invention, after forming the SAC protective film of the semiconductor device, by forming a buffer film as an etch stop layer of the subsequent planarization process, it is possible to prevent the upper portion of the transistor pattern is exposed during the planarization process after the formation of the subsequent interlayer insulating film have.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 본 발명의 범위가 다음에 상술하는 실시예에 한정되는 것은 아니다. 단지 본 실시예는 본 발명의 개시가 완전하도록 하며 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명의 범위는 본원의 특허청구범위에 의해서 이해되어야 한다.Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

도 3 내지 도 5는 본 발명의 일실시 예에 따른 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도이다.3 to 5 are cross-sectional views of devices for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 3을 참조하면, 셀 영역과 주변 회로 영역으로 구분되는 반도체 기판(100) 상에 셀 게이트 패턴(101), 선택 트랜지스터 패턴(102), 및 트랜지스터 패턴(103)을 형성한다. 더욱 자세하게는 셀 영역 상에 셀 게이트 패턴(101), 선택 트랜지스터 패턴(102)을 형성하고, 고전압 영역과 저전압 영역을 포함하는 주변 회로 영역 상에 트랜지스터 패턴(103)을 형성한다.Referring to FIG. 3, a cell gate pattern 101, a selection transistor pattern 102, and a transistor pattern 103 are formed on a semiconductor substrate 100 that is divided into a cell region and a peripheral circuit region. In more detail, the cell gate pattern 101 and the selection transistor pattern 102 are formed in the cell region, and the transistor pattern 103 is formed in the peripheral circuit region including the high voltage region and the low voltage region.

도 4를 참조하면, 셀 게이트 패턴(101), 선택 트랜지스터 패턴(102), 및 트랜지스터 패턴(103)을 포함한 전체 구조 상에 절연막을 형성한 후, 이를 건식 식각하여 선택 트랜지스터 패턴(102), 및 트랜지스터 패턴(103)의 측벽에 잔류시켜 스페이서(104)를 형성한다. 이때 셀 게이트 패턴(101)들 사이의 공간에 절연막이 잔류할 수 있다.Referring to FIG. 4, an insulating film is formed on the entire structure including the cell gate pattern 101, the selection transistor pattern 102, and the transistor pattern 103, and then dry-etched to select the transistor pattern 102. The spacer 104 is formed on the sidewalls of the transistor pattern 103. In this case, an insulating film may remain in the space between the cell gate patterns 101.

이 후, 스페이서(104)를 포함한 전체 구조 상에 SAC 보호막(105)을 형성한다. SAC 보호막(105)은 후속 자기 정렬 콘택 (Self Aligned Contact : 이하, SAC) 공정을 위하여 형성한다. SAC 보호막(105)은 질화막으로 형성하는 것이 바람직하다. SAC 보호막(105)은 200 내지 500Å의 두께로 형성하는 것이 바람직하다.Thereafter, the SAC protective film 105 is formed over the entire structure including the spacer 104. The SAC passivation layer 105 is formed for a subsequent Self Aligned Contact (hereinafter, SAC) process. The SAC protective film 105 is preferably formed of a nitride film. The SAC protective film 105 is preferably formed to a thickness of 200 to 500 kPa.

이 후, SAC 보호막(105)을 포함한 전체 구조 상에 식각 방지용 버퍼막(106)을 형성한다. 버퍼막(106)은 산화막으로 형성하는 것이 바람직하다. 버퍼막(106)은 SiH4/O2 가스를 이용하여 형성하는 것이 바람직하다. 버퍼막(106)은 SiH4/O2 가스 유 량 비율을 0.75 : 1 이상, 바람직하게는 0.75 : 1 내지 1 :1 로 하여 형성하는 것이 바람직하다. 또한 버퍼막(106)은 굴절율(RI)이 1.48 이상되도록 형성하는 것이 바람직하다. 이로 인하여 버퍼막(106)은 Si 함유량이 높아지게 되어 후속 평탄화 공정의 식각 선택비(WER)이 낮아지게 된다.Thereafter, an etch stop buffer film 106 is formed over the entire structure including the SAC passivation film 105. The buffer film 106 is preferably formed of an oxide film. The buffer film 106 is preferably formed using SiH 4 / O 2 gas. The buffer film 106 is preferably formed with a SiH 4 / O 2 gas flow rate ratio of 0.75: 1 or more, preferably 0.75: 1 to 1: 1. In addition, the buffer film 106 is preferably formed so that the refractive index (RI) is 1.48 or more. As a result, the Si content of the buffer layer 106 is increased to lower the etching selectivity WER of the subsequent planarization process.

도 5를 참조하면, 버퍼막(106)을 포함한 전체 구조 상에 제1 절연막(107)을 형성한다. 제1 절연막(107)은 산화막으로 형성하는 것이 바람직하다. 제1 절연막(107)은 SiH4/O2 가스를 이용하여 형성하는 것이 바람직하다. 제1 절연막(107)은 SiH4/O2 가스 유량 비율을 0.75 : 1 이하, 바람직하게는 0.5 : 1 내지 0.75 :1 로 하여 형성하는 것이 바람직하다. 이로 인하여 제1 절연막(107)은 버퍼막(106)에 비해 Si 함량이 적게 되어 후속 평탄화 공정시 식각 선택비가 서로 다르게 된다.Referring to FIG. 5, the first insulating film 107 is formed on the entire structure including the buffer film 106. The first insulating film 107 is preferably formed of an oxide film. The first insulating film 107 is preferably formed using SiH 4 / O 2 gas. The first insulating film 107 is preferably formed with a SiH 4 / O 2 gas flow rate ratio of 0.75: 1 or less, preferably 0.5: 1 to 0.75: 1. As a result, the Si content of the first insulating layer 107 is lower than that of the buffer layer 106, and thus the etching selectivity is different in the subsequent planarization process.

이 후, 버퍼막(106)의 상부가 노출되도록 평탄화 공정을 실시한다. 평탄화 공정은 화학적 기계적 연마 (Chemical Mechanical Polishing; CMP) 방법을 이용하여 실시하는 것이 바람직하다. 이때 주변 회로 영역의 트랜지스터 패턴(103)의 높이가 셀 영역의 선택 트랜지스터 패턴(102) 및 셀 게이트 패턴(101)의 높이보다 낮아도 버퍼막(106)에 의하여 SAC 질화막(105)이 잔류하게 되어 트랜지스터 패턴(103)의 식각 손상을 방지할 수 있다.Thereafter, the planarization process is performed so that the upper portion of the buffer film 106 is exposed. The planarization process is preferably carried out using a chemical mechanical polishing (CMP) method. At this time, even if the height of the transistor pattern 103 of the peripheral circuit region is lower than the height of the selection transistor pattern 102 and the cell gate pattern 101 of the cell region, the SAC nitride film 105 remains by the buffer film 106 and the transistor Etching damage of the pattern 103 can be prevented.

이 후, 제1 절연막(107)을 포함한 전체 구조 상에 제2 절연막(108)을 형성한다.Thereafter, the second insulating film 108 is formed over the entire structure including the first insulating film 107.

본 발명의 기술 사상은 상기 바람직한 실시 예에 따라 구체적으로 기술되었으나, 상기한 실시 예는 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주지하여야 한다. 또한, 본 발명의 기술 분야에서 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시 예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

도 3 내지 도 5는 본 발명의 일실시 예에 따른 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도이다.3 to 5 are cross-sectional views of devices for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>

100 : 반도체 기판 101 : 셀 게이트 패턴100 semiconductor substrate 101 cell gate pattern

102 : 선택 트랜지스터 패턴 103 : 트랜지스터 패턴102: select transistor pattern 103: transistor pattern

104 : 스페이서 105 : SAC 보호막104: spacer 105: SAC protective film

106 : 버퍼막 107 : 제1 절연막106: buffer film 107: first insulating film

108 : 제2 절연막108: second insulating film

Claims (9)

주변 회로 영역과 셀 영역으로 구분되는 반도체 기판 상에 셀 게이트 패턴 및 트랜지스터 패턴을 형성하는 단계;Forming a cell gate pattern and a transistor pattern on a semiconductor substrate divided into a peripheral circuit region and a cell region; 상기 셀 게이트 패턴 및 상기 트랜지스터 패턴을 포함한 전체 구조 상에 보호막을 형성하는 단계;Forming a protective film on the entire structure including the cell gate pattern and the transistor pattern; 상기 보호막을 포함한 전체 구조 상에 버퍼막을 형성하는 단계;Forming a buffer film on the entire structure including the protective film; 상기 버퍼막을 포함한 전체 구조 상에 절연막을 형성하는 단계; 및Forming an insulating film on the entire structure including the buffer film; And 상기 버퍼막이 노출되도록 평탄화 공정을 실시하는 단계를 포함하는 반도체 소자의 제조 방법.And performing a planarization process so that the buffer film is exposed. 제 1 항에 있어서,The method of claim 1, 상기 보호막을 형성하기 전에 상기 트랜지스터 패턴 측벽에 스페이서를 형성하는 단계를 더 포함하는 반도체 소자의 제조 방법.And forming a spacer on sidewalls of the transistor pattern before forming the passivation layer. 제 1 항에 있어서,The method of claim 1, 상기 보호막은 질화막으로 형성하는 반도체 소자의 제조 방법.The protective film is a semiconductor device manufacturing method of forming a nitride film. 제 1 항에 있어서,The method of claim 1, 상기 보호막은 200 내지 500Å의 두께로 형성하는 반도체 소자의 제조 방법.The protective film is a manufacturing method of a semiconductor device to form a thickness of 200 to 500Å. 제 1 항에 있어서,The method of claim 1, 상기 버퍼막은 SiH4/O2 가스를 이용하여 형성하는 반도체 소자의 제조 방법.The buffer film is a method of manufacturing a semiconductor device formed using a SiH 4 / O 2 gas. 제 5 항에 있어서,The method of claim 5, wherein 상기 버퍼막은 상기 SiH4/O2 가스 유량 비율을 0.75 : 1 이상, 바람직하게는 0.75 : 1 내지 1 :1 로 하여 형성하는 반도체 소자의 제조 방법.The buffer film is a method for manufacturing a semiconductor device, wherein the SiH 4 / O 2 gas flow rate ratio is 0.75: 1 or more, preferably 0.75: 1 to 1: 1. 제 1 항에 있어서,The method of claim 1, 상기 절연막은 SiH4/O2 가스를 이용하여 형성하는 반도체 소자의 제조 방법.The insulating film is a method of manufacturing a semiconductor device formed using a SiH 4 / O 2 gas. 제 7 항에 있어서,The method of claim 7, wherein 상기 절연막은 상기 SiH4/O2 가스 유량 비율을 0.75 : 1 이하, 바람직하게는 0.5 : 1 내지 0.75 :1 로 하여 형성하는 반도체 소자의 제조 방법.The insulating film is a method of manufacturing a semiconductor device, wherein the SiH 4 / O 2 gas flow rate ratio is 0.75: 1 or less, preferably 0.5: 1 to 0.75: 1. 제 1 항에 있어서,The method of claim 1, 상기 평탄화 공정의 식각 선택비가 상기 버퍼막보다 상기 절연막이 높은 반도체 소자의 제조 방법.The method of claim 1, wherein an etching selectivity of the planarization process is higher than that of the buffer layer.
KR1020070140082A 2007-12-28 2007-12-28 Method of manufacturing semiconductor device KR20090072090A (en)

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