KR20110024480A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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KR20110024480A
KR20110024480A KR1020090082495A KR20090082495A KR20110024480A KR 20110024480 A KR20110024480 A KR 20110024480A KR 1020090082495 A KR1020090082495 A KR 1020090082495A KR 20090082495 A KR20090082495 A KR 20090082495A KR 20110024480 A KR20110024480 A KR 20110024480A
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South Korea
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film
device isolation
forming
active region
gate
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KR1020090082495A
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Korean (ko)
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신창협
박정우
조상훈
정보경
문주영
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주식회사 하이닉스반도체
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Publication of KR20110024480A publication Critical patent/KR20110024480A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/06—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials
    • H01L21/10—Preliminary treatment of the selenium or tellurium, its application to the foundation plate, or the subsequent treatment of the combination
    • H01L21/108—Provision of discrete insulating layers, i.e. non-genetic barrier layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent a silicon substrate from being excessively lost in an etching process for forming a fin active area by forming a device isolation layer as an SOD(Spin On Dielectric). CONSTITUTION: A trench(32) is formed by selectively etching a silicon substrate(31). A device isolation layer(34) is formed by filling the trench with an SOD. A fin active area is formed by partially etching the device isolation layer on a gate reserved area. A gate crosses the device isolation layer and the fin active area simultaneously.

Description

반도체 장치 제조방법{METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}Semiconductor device manufacturing method {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

본 발명은 반도체 장치의 제조 기술에 관한 것으로, 특히 핀 트랜지스터(Fin Transistor)의 제조방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly, to a method of manufacturing a fin transistor.

수평 채널을 갖는 플래너형 트랜지스터는 반도체 장치의 집적도가 증가함에 따라 채널면적이 감소한다. 이러한 채널면적의 감소는 단채널효과(Short Channel Effect, SCE), 게이트제어력(Gate Controllability) 저하와 같은 문제점을 유발하여 결과적으로 반도체 장치의 고집적화를 어렵게 한다. 이를 해결하기 위해 핀(Fin) 형태로 활성영역을 돌출시키고 이를 포함하는 반도체 기판 상부에 게이트를 형성하여 채널면적을 증가시키는 핀 트랜지스터가 제안되었다. A planar transistor having a horizontal channel decreases in channel area as the degree of integration of a semiconductor device increases. Such a reduction in channel area causes problems such as short channel effect (SCE) and gate controllability (gate controllability), resulting in high integration of semiconductor devices. In order to solve this problem, a fin transistor has been proposed, which protrudes an active region in the form of a fin and increases a channel area by forming a gate over the semiconductor substrate including the fin.

도 1은 종래기술에 따른 핀트랜지스터를 구비하는 반도체 장치를 도시한 평면도이고, 도 2a 내지 도 2c는 종래기술에 따른 핀트랜지스터를 구비하는 반도체 장치의 제조방법을 도 1에 도시된 X-X'절취선을 따라 도시한 공정단면도이다. 1 is a plan view illustrating a semiconductor device having a pin transistor according to the prior art, and FIGS. 2A to 2C illustrate a method of manufacturing a semiconductor device having a pin transistor according to the prior art. It is a process cross-sectional view along the cut line.

도 2a에 도시된 바와 같이, 실리콘기판(11)을 선택적으로 식각하여 소자분리 를 위한 트렌치(12)를 형성한 후, 트렌치(12) 표면에 측벽산화막(wall oxide, 13) 및 라이너질화막(liner nitride, 14)을 순차적으로 형성한다. As shown in FIG. 2A, after the silicon substrate 11 is selectively etched to form the trench 12 for device isolation, a sidewall oxide 13 and a liner nitride layer are formed on the trench 12 surface. nitride 14 is sequentially formed.

다음으로, 라이너질화막(14) 상에 트렌치(12)를 매립하도록 고밀도플라즈마산화막(Hidh Density Plasma, HDP)를 증착하여 소자분리막(15)을 형성함과 동시에 활성영역(16)을 정의한다. Next, a high density plasma oxide (HDP) film is deposited to fill the trench 12 on the liner nitride layer 14 to form the device isolation layer 15 and define an active region 16.

도 2b에 도시된 바와 같이, 게이트예정영역을 오픈하는 마스크패턴(미도시)을 형성한 후, 마스크패턴을 식각장벽(etch barrier)으로 소자분리막(15), 라이너질화막(14) 및 측벽산화막(13)을 동시에 일부 식각하여 핀활성영역(16A)을 형성한다. As shown in FIG. 2B, after forming a mask pattern (not shown) for opening the gate region, the device isolation layer 15, the liner nitride layer 14, and the sidewall oxide layer may be formed as an etch barrier. 13) is partially etched at the same time to form the fin active region 16A.

도 2c에 도시된 바와 같이, 핀활성영역(16A)을 덮고, 핀활성영역(16A)과 소자분리막(15)을 동시에 가로지르는 게이트(20)를 형성한다. 이때, 게이트(20)는 핀활성영역(16A)의 표면을 따라 형성된 게이트절연막(17), 핀활성영역(16A)을 덮는 게이트전극(18) 및 게이트전극(18) 상의 게이트하드마스크막(19)이 순차적으로 적층된 적층구조물로 형성한다.As shown in FIG. 2C, a gate 20 is formed to cover the fin active region 16A and cross the fin active region 16A and the device isolation layer 15 simultaneously. In this case, the gate 20 includes a gate insulating film 17 formed along the surface of the fin active region 16A, a gate electrode 18 covering the fin active region 16A, and a gate hard mask layer 19 on the gate electrode 18. ) Is formed of a laminated structure stacked sequentially.

하지만, 종래기술은 핀활성영역(16A)을 형성하기 위한 식각공정시 소자분리막(15), 라이너질화막(14) 및 측벽산화막(13)을 동시에 식각하기 위해 식각가스로 불화탄소가스(CxFy, x,y는 0을 제외한 자연수)와 불화메탄가스(ClHmFn, l,m,n은 0을 제외한 자연수)가 혼합된 혼합가스를 사용하기 때문에 실리콘기판(11)이 과도손실되는 문제점이 발생한다. However, in the related art, in order to simultaneously etch the device isolation layer 15, the liner nitride layer 14, and the sidewall oxide layer 13 during the etching process for forming the fin active region 16A, carbon fluoride gas (C x F) may be used as an etching gas. The silicon substrate 11 is excessive because y , x, y use a mixed gas mixed with natural water excluding 0) and methane fluoride gas (C l H m F n , l, m, n is natural water except 0). There is a problem that is lost.

구체적으로, 불화메탄가스는 산화막 식각가스로 소자분리막(15) 및 측벽산화막(13)을 식각하는 역할을 수행하고, 불화탄소가스는 질화막 식각가스로 라이너질화막(14)을 식각하는 역할을 수행한다. 이때, 불화탄소가스는 실리콘기판(11)에 대한 식각선택비가 없기 때문에(즉, 불화탄소가스는 실리콘기판(11)도 잘 식각함) 핀활성영역(16A) 형성간 실리콘기판(11)이 과도손실되는 문제점이 발생한다. Specifically, the methane fluoride gas serves to etch the device isolation layer 15 and the sidewall oxide layer 13 with an oxide film etching gas, and the carbon fluoride gas serves to etch the liner nitride film 14 with the nitride film etching gas. . At this time, since the carbon fluoride gas has no etching selectivity with respect to the silicon substrate 11 (that is, the carbon fluoride gas is also etched well in the silicon substrate 11), the silicon substrate 11 between the fin active regions 16A is excessively formed. There is a problem that is lost.

일례로, 불화탄소가스와 불화메탄가스가 혼합된 혼합가스를 이용하여 400Å ~ 500Å 범위의 높이(H)를 갖는 핀활성영역(16A)를 형성하고자 할 때, 실리콘기판(11)은 대략 600Å 정도 손실(또는 식각)이 발생하고, 소자분리막(15)은 대략 1100Å 정도의 손실(또는 식각)이 발생한다. 즉, 소자분리막(15)과 실리콘기판(11) 사이의 식각선택비가 2:1(산화막:실리콘)이다. For example, when the fin active region 16A having a height H in the range of 400 kPa to 500 kPa is formed using a mixed gas of carbon fluoride gas and methane fluoride gas, the silicon substrate 11 is approximately 600 kPa. Loss (or etching) occurs, and the device isolation film 15 has a loss (or etching) of about 1100 Å. That is, the etching selectivity between the device isolation film 15 and the silicon substrate 11 is 2: 1 (oxide film: silicon).

정리하면, 종래기술은 소자분리막(15), 라이너질화막(14) 및 측벽산화막(13)을 동시에 식각하여 핀활성영역(16A)을 형성하기 위해 식각가스로 불화탄소가스와 불화메탄가스가 혼합된 혼합가스를 사용하기 때문에 소자분리막(15)과 실리콘기판(11) 사이의 식각선택비가 낮아 실리콘기판(11)이 과도손실되는 문제점이 발생한다. In summary, in the related art, in order to form the fin active region 16A by simultaneously etching the device isolation film 15, the liner nitride film 14, and the sidewall oxide film 13, carbon fluoride gas and methane fluoride gas are mixed as an etching gas. Since the mixed gas is used, the etching selectivity between the device isolation layer 15 and the silicon substrate 11 is low, resulting in excessive loss of the silicon substrate 11.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 핀활성영역을 형성시 기판이 과도손실되는 것을 방지할 수 있는 반도체 장치 제조방법을 제공하는데 그 목적이 있다. The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a method for manufacturing a semiconductor device which can prevent the substrate from being excessively lost when forming the fin active region.

상기 목적을 달성하기 위한 일 측면에 따른 본 발명의 반도체 장치 제조방법은, 실리콘기판을 선택적으로 식각하여 트렌치를 형성하는 단계; 상기 트렌치를 스핀온절연막으로 매립하여 소자분리막을 형성하는 단계; 게이트예정영역의 상기 소자분리막을 일부 식각하여 핀활성영역을 형성하는 단계; 및 상기 소자분리막과 상기 핀활성영역을 동시에 가로지르는 게이트를 형성하는 단계를 포함한다. According to one aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including selectively etching a silicon substrate to form a trench; Filling the trench with a spin-on insulating film to form a device isolation film; Partially etching the device isolation layer in the gate potential region to form a fin active region; And forming a gate crossing the device isolation layer and the fin active region at the same time.

또한, 본 발명의 반도체 장치 제조방법은 상기 소자분리막을 형성하기 이전에 상기 트렌치 표면에 측벽산화막을 형성하는 단계를 더 포함할 수 있다. In addition, the method of manufacturing a semiconductor device of the present invention may further include forming a sidewall oxide film on the trench surface before forming the device isolation layer.

상기 소자분리막은 폴리실라잔 기반의 스핀온절연막으로 형성할 수 있다. The device isolation layer may be formed of a polysilazane-based spin-on insulating layer.

상기 핀활성영역을 형성하는 단계는, 불화메탄가스를 사용하여 실시할 수 있다. 또한, 상기 핀활성영역을 형성하는 단계는, 산소가스 및 아르곤가스를 더 첨가하여 실시할 수 있다. Forming the fin active region may be performed using methane fluoride gas. In addition, the forming of the fin active region may be performed by further adding oxygen gas and argon gas.

상술한 과제 해결 수단을 바탕으로 하는 본 발명은 소자분리막을 스핀온절연막으로 형성하여 라이너질화막 형성공정을 생략함으로써, 핀활성영역을 형성하기 위한 식각공정시 실리콘기판이 과도손실되는 것을 방지할 수 있는 효과가 있다. The present invention based on the above-described problem solving means to form a device isolation film as a spin-on insulating film to omit the liner nitride film forming process, it is possible to prevent the excessive loss of the silicon substrate during the etching process for forming the fin active region It works.

이하 본 발명이 속하는 기술분야에서 통상의 지식을 가진자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

후술할 본 발명은 핀활성영역 형성시 기판 예컨대, 실리콘기판이 과도손실되는 것을 방지할 수 있는 반도체 장치의 제조방법을 제공한다. 이를 위해 본 발명은 소자분리막을 고밀도플라즈마산화막(High Density Plasma, HDP) 대신 스핀온절연막(Spin On Dielectric, SOD)으로 형성하여 소자분리를 위한 트렌치 측벽에 라이너질화막(liner nitride)을 형성하지 않음을 기술적 원리로 한다.The present invention, which will be described later, provides a method of manufacturing a semiconductor device which can prevent excessive loss of a substrate such as a silicon substrate when forming a fin active region. To this end, the present invention forms a device isolation film as a spin on dielectric (SOD) instead of a high density plasma oxide (HDP) film, so that a liner nitride film is not formed on the trench sidewalls for device isolation. It is a technical principle.

도 3a 내지 도 3c는 본 발명의 일실시예에 따른 핀트랜지스터를 구비하는 반도체 장치의 제조방법을 도 1에 도시된 X-X' 절취선을 따라 도시한 공정단면도이다. 3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device having a pin transistor according to an embodiment of the present invention along the line X-X 'of FIG. 1.

도 3a에 도시된 바와 같이, 실리콘기판(31) 상에 패드산화막(미도시) 및 패드질화막(미도시)이 적층된 구조의 하드마스크패턴(미도시)을 형성한 후에 하드마스크패턴을 식각장벽(etch barrier)으로 실리콘기판(31)을 식각하여 소자분리를 위한 트렌치(32)를 형성한다. As shown in FIG. 3A, after forming a hard mask pattern (not shown) having a structure in which a pad oxide film (not shown) and a pad nitride film (not shown) are stacked on the silicon substrate 31, the hard mask pattern is etched. The silicon substrate 31 is etched as an etch barrier to form the trench 32 for device isolation.

다음으로, 트렌치(32)를 형성하는 과정에서 트렌치(32) 표면에 발생된 손상을 치유(curing)하기 위해 트렌치(32) 표면에 측벽산화막(33)을 형성한다. 측벽산화막(33)은 실리콘산화막(SiO2)으로 형성할 수 있으며, 열산화법(thermal oxidation)을 사용하여 형성할 수 있다. Next, a sidewall oxide layer 33 is formed on the trench 32 surface in order to cure damage occurring on the trench 32 in the process of forming the trench 32. The sidewall oxide film 33 may be formed of a silicon oxide film (SiO 2 ), and may be formed using a thermal oxidation method.

다음으로, 측벽산화막(33) 상에 트렌치(32)를 매립하도록 스핀온절연막을 증착한 후에 실리콘기판(31) 상부면이 노출되도록 평탄화공정을 실시하여 소자분리막(34)을 형성한다. 이때, 평탄화공정은 화학적기계적연마법(CMP)을 사용하여 실시할 수 있으며, 실리콘기판(31)에서 소자분리막(34)이 형성되지 않은 나머지 영역을 활성영역(35)으로 정의할 수 있다. 그리고, 소자분리막(34)은 폴리실라잔(polysilazane)을 기반으로 스핀온절연막으로 형성할 수 있다. 참고로, 폴리실라잔 기반의 스핀온절연막은 실리콘산화막과 동일한 실리콘-산소(Si-O) 결합으로 이루어져 있다.Next, after the spin-on insulating film is deposited to fill the trench 32 on the sidewall oxide layer 33, a planarization process is performed to expose the upper surface of the silicon substrate 31 to form the device isolation layer 34. In this case, the planarization process may be performed using chemical mechanical polishing (CMP), and the remaining region in which the device isolation layer 34 is not formed in the silicon substrate 31 may be defined as the active region 35. In addition, the device isolation layer 34 may be formed of a spin-on insulating layer based on polysilazane. For reference, the polysilazane-based spin-on insulating film is made of the same silicon-oxygen (Si-O) bond as the silicon oxide film.

여기서, 본 발명은 소자분리막(34)을 스핀온절연막으로 형성하기 때문에 라이너질화막 형성공정을 생략할 수 있다. 즉, 측벽산화막(33) 상에 라이너질화막을 형성하지 않아도 무방하다. Here, since the device isolation layer 34 is formed of a spin-on insulating layer, the liner nitride film forming process may be omitted. That is, the liner nitride film may not be formed on the sidewall oxide film 33.

참고로, 종래에는 소자분리막(34)을 고밀도플라즈마산화막(HDP)로 형성했는데, 반도체 장치의 집적도가 증가함에 따라 고종횡비를 갖는 트렌치(32)를 고밀도플라즈마산화막으로 매립하기 위해 증착공정과 식각공정을 반복실시하여 소자분리막(34)를 형성하였다. 이때, 고밀도플라즈마산화막 식각공정시 식각가스로 사용되 는 삼불화질소(NF3)에 의하여 트렌치(32) 측벽이 손상되는 것을 방지하기 위해 라이너질화막을 형성하였다. For reference, in the related art, the device isolation film 34 is formed of a high density plasma oxide film (HDP), and the deposition process and the etching process are performed to fill the trench 32 having a high aspect ratio with the high density plasma oxide film as the degree of integration of semiconductor devices increases. Repeatingly, the device isolation film 34 was formed. In this case, a liner nitride film was formed to prevent the sidewalls of the trench 32 from being damaged by nitrogen trifluoride (NF 3 ) used as an etching gas during the high density plasma oxide layer etching process.

하지만, 본 발명은 소자분리막(34)을 스핀온절연막으로 형성함에 따라 삼불화질소에 의한 트렌치(32) 측벽 손상을 원천적으로 방지할 수 있으며, 스핀온절연막은 유동성이 큰 물질이기 때문에 증착공정과 식각공정을 반복실시하지 않아도 고종횡비를 갖는 트렌치(32)를 한번에 매립할 수 있다. However, according to the present invention, since the device isolation layer 34 is formed as a spin-on insulating layer, damage to the trench 32 sidewalls caused by nitrogen trifluoride can be prevented. Even if the etching process is not repeated, the trench 32 having a high aspect ratio can be filled at a time.

도 3b에 도시된 바와 같이, 실리콘기판(31) 상에 게이트예정영역을 오픈하는 하드마스크패턴(미도시)을 형성한 후에 하드마스크패턴을 식각장벽으로 소자분리막(34) 및 측벽산화막(33)을 일부 식각하여 핀활성영역(35A)을 형성한다. As shown in FIG. 3B, after forming a hard mask pattern (not shown) for opening a gate region to be formed on the silicon substrate 31, the device isolation layer 34 and the sidewall oxide layer 33 are formed using the hard mask pattern as an etch barrier. Is partially etched to form the fin active region 35A.

핀활성영역(35A)을 형성하기 위한 식각공정은 불화메탄가스(ClHmFn, l,m,n은 0을 제외한 자연수)를 사용하여 실시할 수 있다. 이때, 불화메탄가스는 산화막 식각가스로 스핀온절연막으로 이루어진 소자분리막(34) 및 측벽산화막(33)을 식각하는 역할을 수행하며, CHF3, CH2F2 등을 사용할 수 있다. 또한, 식각공정시 불화메탄가스와 더불어서 식각공정 특성을 향상시키기 위하여 산소가스(O2) 및 아르곤가스(Ar)를 첨가할 수 있다. The etching process for forming the fin active region 35A may be performed using methane fluoride gas (C l H m F n , l, m, n is a natural number except 0). In this case, the methane fluoride gas serves to etch the device isolation layer 34 and the sidewall oxide layer 33 formed of the spin-on insulating layer as the oxide etching gas, and may use CHF 3 , CH 2 F 2, or the like. In addition, in addition to methane fluoride gas during the etching process, oxygen gas (O 2 ) and argon gas (Ar) may be added to improve the etching process characteristics.

핀활성영역(35A)을 형성하기 위한 식각공정시 종래에는 소자분리막(34), 측벽산화막(33)과 더불어서 라이너질화막을 식각하기 위해 불화탄소가스와 불화메탄가스가 혼합된 혼합가스를 사용하였으나, 본 발명은 라이너질화막을 형성하지 않기 때문에 식각공정시 불화탄소가스를 사용하지 않는다. 즉, 실리콘기판(31)에 대한 식각선택비가 열악한(즉, 실리콘기판을 잘 식각하는) 불화탄소가스를 사용하지 않음으로써, 소자분리막(34)과 실리콘기판(31) 사이의 식각선택비를 향상시켜 실리콘기판(11)이 과도손실되는 것을 방지할 수 있다. In the etching process for forming the fin active region 35A, a mixed gas including carbon fluoride gas and methane fluoride gas is conventionally used to etch the liner nitride film together with the device isolation film 34 and the sidewall oxide film 33. Since the present invention does not form a liner nitride film, no carbon fluoride gas is used in the etching process. That is, the etch selectivity between the device isolation film 34 and the silicon substrate 31 is improved by not using fluorocarbon gas having poor etching selectivity with respect to the silicon substrate 31 (that is, etching the silicon substrate well). In this way, the silicon substrate 11 can be prevented from being excessively lost.

일례로, 불화메탄가스를 사용하여 소자분리막(34) 및 측벽산화막(33)을 식각하여 400Å ~ 500Å 범위의 높이(H)를 갖는 핀활성영역(35A)을 형성하는 경우에 실리콘기판(31)은 대략 150Å 정도가 식각되는데 반해, 소자분리막(34)은 대략 750Å 정도가 식각된다. 즉, 소자분리막(34)과 실리콘기판(31) 사이에서 5:1(소자분리막:실리콘기판)의 식각선택비를 확보할 수 있다. For example, the silicon substrate 31 may be formed by etching the device isolation layer 34 and the sidewall oxide layer 33 using methane fluoride gas to form a fin active region 35A having a height H in the range of 400 kV to 500 kV. Is about 150 Å etched, while the device isolation film 34 is about 750 Å. That is, an etching selectivity of 5: 1 (device isolation film: silicon substrate) can be secured between the device isolation film 34 and the silicon substrate 31.

또한, 본 발명은 산화막인 소자분리막(34)과 측벽산화막(33)만을 식각하여 핀활성영역(35A)을 형성하기 때문에 산화막에 대한 식각특성을 보다 용이하게 조절할 수 있는 산화막 식각 전용 장비에서 핀활성영역(35A)을 형성하기 위한 식각공정을 실시할 수 있다. 참고로, 종래에는 산화막인 소자분리막(34)과 측벽산화막(33)을 식각함과 동시에 라이너질화막을 식각하기 위해 폴리실리콘 식각 전용 장비에서 핀활성영역(35A)을 형성하기 위한 식각공정을 진행함에 따라 산화막 및 질화막에 대한 식각특성 조절이 본 발명에 비하여 상대적으로 떨어진다는 단점이 있다. In addition, since the fin active region 35A is formed by etching only the device isolation layer 34 and the sidewall oxide layer 33, which are oxides, the fin activity in the oxide-etching equipment that can more easily control the etching characteristics of the oxide layer. An etching process may be performed to form the region 35A. For reference, in the related art, in order to etch the device isolation layer 34 and the sidewall oxide layer 33, which are oxide films, to form a fin active region 35A in a polysilicon etching-only device to etch the liner nitride layer. Accordingly, there is a disadvantage in that the etching characteristic control for the oxide film and the nitride film is relatively inferior to the present invention.

도 3c에 도시된 바와 같이, 핀활성영역(35A) 표면에 게이트절연막(36)을 형성한다. 게이트절연막(36)은 산화막 예컨대, 실리콘산화막으로 형성할 수 있으며, 게이트절연막(36)으로 이용되는 실리콘산화막은 열산화법을 사용하여 형성할 수 있다. As shown in FIG. 3C, a gate insulating film 36 is formed on the surface of the fin active region 35A. The gate insulating film 36 may be formed of an oxide film, for example, a silicon oxide film, and the silicon oxide film used as the gate insulating film 36 may be formed using a thermal oxidation method.

다음으로, 게이트절연막(36) 상에 핀활성영역(35A)을 덮는 게이트도전막을 형성한다. 이때, 게이트도전막은 실리콘막, 금속성막 또는 실리콘막과 금속성막이 적층된 적층막으로 형성할 수 있다. 실리콘막으로는 폴리실리콘막(poly Si), 실리콘게르마늄막(SiGe)등을 사용할 수 있고, 금속성막으로 티타늄(Ti), 텅스텐(W), 텅스텐실리사이드(WSi), 티타늄질화막(TiN) 등을 사용할 수 있다.Next, a gate conductive film covering the fin active region 35A is formed on the gate insulating film 36. In this case, the gate conductive film may be formed of a silicon film, a metal film, or a laminated film in which a silicon film and a metal film are stacked. As the silicon film, a polysilicon film (poly Si), a silicon germanium film (SiGe), or the like may be used. As the metallic film, titanium (Ti), tungsten (W), tungsten silicide (WSi), or titanium nitride film (TiN) may be used. Can be used.

다음으로, 게이트도전막 상에 게이트하드마스크막(38)을 형성한다. 게이트하드마스크막(38)은 산화막, 질화막 및 산화질화막(oxynitride)으로 이루어진 그룹으로부터 선택된 어느 하나 또는 이들이 적층된 적층막으로 형성할 수 있다. Next, a gate hard mask film 38 is formed on the gate conductive film. The gate hard mask film 38 may be formed of any one selected from the group consisting of an oxide film, a nitride film, and an oxynitride, or a laminated film in which these are stacked.

다음으로, 게이트예정영역을 덮고, 게이트예정영역을 제외한 나머지 영역을 오픈하는 감광막패턴(미도시)을 형성한 후에 감광막패턴을 식각장벽으로 게이트절연막(38), 게이트도전막 및 게이트절연막(36)을 순차적으로 식각한다. Next, after forming a photoresist pattern (not shown) covering the gate region and opening other regions except for the gate region, the gate insulation layer 38, the gate conductive layer, and the gate insulation layer 36 are formed using the photoresist pattern as an etch barrier. Etch sequentially.

상술한 공정과정을 통해 소자분리막(34)과 핀활성영역(35A)을 동시에 가로지르고, 게이트절연막(36), 게이트전극(37) 및 게이트하드마스크막(38)이 순차적으로 적층된 구조의 게이트(39)를 형성할 수 있다. A gate having a structure in which the device isolation layer 34 and the fin active region 35A are simultaneously crossed through the above-described process, and the gate insulating layer 36, the gate electrode 37, and the gate hard mask layer 38 are sequentially stacked. 39 can be formed.

이와 같이, 본 발명은 소자분리막(34)을 스핀온절연막으로 형성하여 라이너질화막 형성공정을 생략함으로써, 핀활성영역(35A)을 형성하기 위한 식각공정시 실리콘기판(31)이 과도식각되는 것을 방지할 수 있다. As such, the present invention prevents the silicon substrate 31 from being excessively etched during the etching process for forming the fin active region 35A by omitting the liner nitride film forming process by forming the device isolation layer 34 as a spin-on insulating film. can do.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기 실시예는 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술분야의 통상의 전문가라면 본 발명의 기술사상의 범 위내의 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments within the scope of the technical idea of the present invention are possible.

도 1은 종래기술에 따른 핀트랜지스터를 구비하는 반도체 장치를 도시한 평면도.1 is a plan view showing a semiconductor device having a pin transistor according to the prior art.

도 2a 내지 도 2c는 종래기술에 따른 핀트랜지스터를 구비하는 반도체 장치의 제조방법을 도시한 공정단면도. 2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device having a pin transistor according to the prior art.

도 3a 내지 도 3c는 본 발명의 일실시예에 따른 핀트랜지스터를 구비하는 반도체 장치의 제조방법을 도시한 공정단면도. 3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device having a pin transistor according to an embodiment of the present invention.

*도면 주요 부분에 대한 부호 설명** Description of symbols on the main parts of the drawings *

31 : 실리콘기판 32 : 트렌치31 silicon substrate 32 trench

33 : 측벽산화막 34 : 소자분리막33 sidewall oxide film 34 device isolation film

35 : 활성영역 35A : 핀활성영역35: active area 35A: pin active area

36 : 게이트절연막 37 : 게이트전극36: gate insulating film 37: gate electrode

38 : 게이트하드마스크막 39 : 게이트38: gate hard mask film 39: gate

Claims (5)

실리콘기판을 선택적으로 식각하여 트렌치를 형성하는 단계;Selectively etching the silicon substrate to form a trench; 상기 트렌치를 스핀온절연막으로 매립하여 소자분리막을 형성하는 단계;Filling the trench with a spin-on insulating film to form a device isolation film; 게이트예정영역의 상기 소자분리막을 일부 식각하여 핀활성영역을 형성하는 단계; 및Partially etching the device isolation layer in the gate potential region to form a fin active region; And 상기 소자분리막과 상기 핀활성영역을 동시에 가로지르는 게이트를 형성하는 단계Forming a gate crossing the device isolation layer and the fin active region at the same time 를 포함하는 반도체 장치 제조방법. Semiconductor device manufacturing method comprising a. 제1항에 있어서, The method of claim 1, 상기 소자분리막을 형성하기 이전에 상기 트렌치 표면에 측벽산화막을 형성하는 단계를 더 포함하는 반도체 장치 제조방법. And forming a sidewall oxide film on the trench surface prior to forming the device isolation film. 제1항에 있어서, The method of claim 1, 상기 소자분리막은 폴리실라잔 기반의 스핀온절연막으로 형성하는 반도체 장치 제조방법. The device isolation film is a semiconductor device manufacturing method of forming a polysilazane-based spin-on insulating film. 제1항에 있어서, The method of claim 1, 상기 핀활성영역을 형성하는 단계는, Forming the pin active region, 불화메탄가스를 사용하여 실시하는 반도체 장치 제조방법. A semiconductor device manufacturing method using methane fluoride gas. 제4항에 있어서, The method of claim 4, wherein 상기 핀활성영역을 형성하는 단계는, Forming the pin active region, 산소가스 및 아르곤가스를 더 첨가하여 실시하는 반도체 장치 제조방법. A method of manufacturing a semiconductor device, further comprising oxygen gas and argon gas.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10157921B2 (en) 2015-03-03 2018-12-18 Samsung Electronics Co., Ltd. Integrated circuit devices including FIN active areas with different shapes

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10157921B2 (en) 2015-03-03 2018-12-18 Samsung Electronics Co., Ltd. Integrated circuit devices including FIN active areas with different shapes

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