KR20100074634A - Method of forming contact hole in semiconductor device - Google Patents

Method of forming contact hole in semiconductor device Download PDF

Info

Publication number
KR20100074634A
KR20100074634A KR1020080133123A KR20080133123A KR20100074634A KR 20100074634 A KR20100074634 A KR 20100074634A KR 1020080133123 A KR1020080133123 A KR 1020080133123A KR 20080133123 A KR20080133123 A KR 20080133123A KR 20100074634 A KR20100074634 A KR 20100074634A
Authority
KR
South Korea
Prior art keywords
layer
film
contact hole
etching
forming
Prior art date
Application number
KR1020080133123A
Other languages
Korean (ko)
Inventor
권우준
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080133123A priority Critical patent/KR20100074634A/en
Publication of KR20100074634A publication Critical patent/KR20100074634A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a contact hole of a semiconductor device is provided to stably secure the resistance of a contact plug in a contact hole by vertically forming the sidewall of a contact hole. CONSTITUTION: An etch stop layer(108), a first insulation layer(110), and a second insulation layer(112) are formed on a semiconductor substrate(102). Contact holes to expose the etch stop layer are formed by etching the first insulation layer and the second insulation layer. A protection layer(118) is formed on the sidewall and upper side of the second insulation layer. The thickness of the protection becomes thick on the lower side thereof. The part of the semiconductor substrate is exposed through the lower side of the contact holes by etching the etch stop layer exposed on the lower side of the contact holes.

Description

Method of forming contact hole in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly to a method for forming a contact hole in a semiconductor device for forming a reliable contact hole when forming a contact hole having a high aspect ratio.

The junction region formed in the semiconductor substrate is electrically connected to the metal wiring formed on the insulating layer thereon through contact plugs. The contact plug is formed by performing an etching process on the etch stop layer and the insulating layer formed on the semiconductor substrate to form a contact hole exposing the junction region, and then filling the contact hole with a conductive material. Therefore, precisely etching the insulating film or the etch stop film to form a contact hole to expose the junction region formed in the semiconductor substrate is an important process for forming a reliable contact plug.

However, as the size of the semiconductor device is gradually reduced, the width at which the contact hole is formed is also reduced, so that the area where the contact plug is in contact with the lower structure is reduced. As a result, the contact resistance of the contact plug may increase to deteriorate the characteristics of the semiconductor device.

According to an embodiment of the present invention, a thinner protective film is formed on the sidewall of the contact hole having an inclined profile, and thus the sidewall profile of the contact hole is formed closer to the vertical side. Can be removed to form the contact hole sidewalls closer to the vertical.

The method of forming a contact hole in a semiconductor device according to the present invention may include forming an etch stop layer, a first insulating layer, and a second insulating layer on a semiconductor substrate, etching the second insulating layer and the first insulating layer, and etching the lower portion. Forming contact holes exposing a stop layer, forming a passivation layer on the sidewalls and an upper portion of the second insulating layer, wherein the passivation layer is formed to become thinner toward the bottom; and the etch stop exposed to the bottom of the contact holes Etching the film to expose a portion of the semiconductor substrate through the bottom of the contact holes.

The passivation layer may be formed of a material layer having a different etching selectivity from the first or second insulating layer. The protective film may be formed of an LP nitride film. The forming of the contact holes may include forming a hard mask layer and a photoresist pattern on the second insulating layer, an etching process using the photoresist pattern as an etch mask, and forming the hard mask layer and the second insulating layer; The method may further include forming the contact holes by etching the first insulating layer, removing the photoresist pattern and the hard mask layer, and performing a first cleaning process. The passivation layer may also be formed in the curvature formed at the boundary between the first and second insulating layers during the first cleaning process. After forming the passivation layer, the method may further include performing a second cleaning process on the semiconductor substrate. The second cleaning process may be performed under conditions that the first insulating film is more etched than the protective film. The second cleaning process may use an HF solution. The HF solution may be diluted to 50: 1 to 200: 1 in water. The exposed sidewalls of the first insulating layer may be removed during the second cleaning process. The etching of the etch stop layer exposed to the lower portions of the contact holes may be performed by LET (Light Etch Treatment). The LET may use a gas obtained by mixing CF 4 gas, Ar gas, and O 2 gas.

According to the method for forming a contact hole of a semiconductor device of the present invention, by forming the sidewall of the contact hole close to the vertical, it is possible to improve the bridge margin between adjacent contact holes, and to stabilize the contact plug formed inside the contact hole. Resistance can be secured. Therefore, a higher performance semiconductor device can be manufactured.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application. In addition, when an arbitrary film is described as being formed on another film or on a semiconductor substrate, the arbitrary film may be formed in direct contact with the other film or the semiconductor substrate, or may be formed with a third film interposed therebetween. . In addition, the thickness or size of each layer shown in the drawings may be exaggerated for convenience and clarity of description.

1A to 1F are cross-sectional views of devices illustrated to describe one embodiment of a method for forming a contact hole in a semiconductor device according to the present invention. Hereinafter, a NAND flash memory device will be described as an example.

Referring to FIG. 1A, an isolation region 104 is formed on a semiconductor substrate 102 to define an active region. A junction region (reference numeral D), a gate electrode (not shown), or the like may be formed in the active region. The buffer film 106 is formed on the semiconductor substrate 102 including the device isolation structure 104. The buffer film 106 is a film for protecting the semiconductor substrate 102 or a structure formed on the semiconductor substrate 102 during a subsequent etching process, and may be formed of an oxide film. An etch stop layer 108 is formed on the buffer layer 106. The etch stop layer 108 is formed to form contact holes having a uniform depth in the subsequent etching process for forming the contact hole, and is formed of a material film having an etching selectivity different from that of the insulating layer formed thereon. For example, when the oxide film is formed on the etch stop film 108, the etch stop film 108 is formed of a nitride film.

The first insulating layer 110 is formed and planarized on the etch stop layer 108 as an interlayer insulating layer. The first insulating layer 110 may be formed to have a thickness of 2000 Pa to 10,000 Pa using an HDP (High Density Plasma) oxide film or a Low Pressure-Tetra Ethyl Ortho Silicate (LP-TEOS) oxide film. Subsequently, a mask pattern (not shown) is formed on the first insulating layer 110, and then the first insulating layer 110 is etched by an etching process using a mask pattern (not shown) to form an underlying semiconductor substrate 102. A source contact hole (not shown) to which the formed source region is exposed is formed. A source contact plug (not shown) is formed by filling a conductive material in the source contact hole (not shown).

Subsequently, the second insulating film 108 is formed and planarized on the semiconductor substrate 102 including the first insulating film 110 as an interlayer insulating film. The second insulating film 108 can be formed to a thickness of 100 kV to 2000 kV using an oxide film, for example, an HDP oxide film or an LP-TEOS oxide film.

The hard mask film 114 is formed on the second insulating film 108. The hard mask film 114 may be formed of a material film having a different etching selectivity from the insulating film 108. Preferably, the hard mask film 114 may be formed of an amorphous carbon film. A photoresist pattern 116 is formed on the hard mask layer 114 to open the region where the contact hole is to be formed.

Referring to FIG. 1B, the hard mask layer 114 is etched by the etching process using the photoresist pattern 116 (see FIG. 1A) to form the hard mask pattern 114, and the etching using the hard mask pattern 114 is performed. In the process, the second insulating film 112 and the first insulating film 110 are etched to form a contact hole (reference numeral C) exposing the etch stop film 108 in the lower portion.

The etching process of the insulating film 108 for forming the contact hole (reference numeral C) may be a dry etching process. Such a dry etching process may be performed with an etching gas obtained by mixing a fluorocarbon (C x F y ) gas, a fluorohydrocarbon (C x H y F z ) gas, an Ar gas, and an O 2 gas. At this time, the sidewall of the contact hole (reference numeral C) is formed in a profile having a predetermined inclination due to the nature of the etching process, the width of the contact hole (reference numeral C) may become narrower toward the bottom.

Referring to FIG. 1C, a photoresist strip process of removing the photoresist pattern 116 (see FIG. 1B) is performed and a cleaning process is performed. During the photoresist strip process, the hard mask 114 formed of the amorphous carbon film may also be removed. Meanwhile, a part of the first insulating film 110 and the second insulating film 112 may be removed together during the cleaning process, and in particular, a boundary between the first insulating film 110 and the second insulating film 112 may be further removed. . Accordingly, a bend may be formed on the sidewall of the contact hole C.

As such, the inclined profile of the sidewall of the contact hole (reference numeral C) narrows the lower width of the contact hole (reference numeral C), thereby reducing the contact area of the contact plug formed in the contact hole (reference numeral C). As a result, the resistance of the contact plug may increase. In addition, the bending formed on the sidewall of the contact hole (reference numeral C) may cause a poor deposition in the process of forming a contact plug inside the contact hole (reference numeral C) in a subsequent process, which may cause a defect in the contact plug. Therefore, the present invention is to make the inclined profile of the side wall of the contact hole (reference numeral C) to be close to the vertical profile and to perform a process to alleviate the curvature formed in the contact hole (reference numeral C), which will be described in detail below. do.

Referring to FIG. 1D, the passivation layer 118 is formed on the sidewalls and the upper portion of the second insulating layer 112. The passivation layer 118 may be formed of a material layer having excellent step coverage and having a different etching selectivity from the first insulating layer 110 or the second insulating layer 112, for example, a low pressure (LP) nitride layer. In addition, the passivation layer 118 is formed thicker on the upper sidewall of the second insulating layer 112 than on the lower sidewall of the second insulating layer 112 to form the contact hole (reference numeral C) sidewall closer to the vertical profile in the inclined profile. It is preferable. In addition, the protective film 118 is formed on the sidewalls of the boundary between the first insulating film 110 and the second insulating film 112, so that the bending formed on the sidewalls of the contact hole (reference numeral C) can be alleviated.

Referring to FIG. 1E, a cleaning process is performed on the semiconductor substrate 102. The cleaning process may be performed under the condition that the first insulating film 110 formed of the oxide film is further removed compared to the protective film 118 formed of the nitride film. Therefore, the second insulating film 112 is not etched by the passivation film 118 during the cleaning process, and the sidewalls (reference numeral A) of the first insulating film 110 exposed during the cleaning process are partially removed to be close to the vertical profile. Can be formed. This cleaning process may use a HF solution diluted 50: 1 to 200: 1 in water.

Referring to FIG. 1F, the etch stop film 108 and the buffer film 106 exposed to the lower portion of the contact hole (reference numeral C) are removed by an etching process using the protective film 118 as an etching mask, thereby removing the contact hole (drawing A junction region (reference numeral D), for example, a drain region, is exposed below the C. At this time, the etching process is preferably performed by LET (Light Etch Treatment). LET may use a gas obtained by mixing CF 4 gas with Ar gas and O 2 gas.

1A to 1F are cross-sectional views of devices illustrated to describe one embodiment of a method for forming a contact hole in a semiconductor device according to the present invention.

<Description of the symbols for the main parts of the drawings>

102 semiconductor substrate 104 device isolation structure

106: buffer film 108: etch stop film

110: first insulating film 112: second insulating film

114: hard mask film 116: photoresist pattern

118: shield

Claims (12)

Forming an etch stop film, a first insulating film and a second insulating film on the semiconductor substrate; Etching the second insulating layer and the first insulating layer to form contact holes exposing the etch stop layer below; Forming a passivation layer on sidewalls and an upper portion of the second insulating layer, wherein the passivation layer is formed to be thinner toward a lower portion thereof; And And etching the etch stop layer exposed in the lower portions of the contact holes to expose a portion of the semiconductor substrate through the lower portions of the contact holes. The method of claim 1, The protective layer may be formed of a material layer having a different etching selectivity from the first or second insulating layer. The method of claim 1, The protective film is a contact hole forming method of a semiconductor device formed of an LP nitride film. The method of claim 1, wherein the forming of the contact holes comprises: Forming a hard mask film and a photoresist pattern on the second insulating film; Etching the hard mask layer, the second insulating layer, and the first insulating layer by an etching process using the photoresist pattern as an etching mask to form the contact holes; And And removing the photoresist pattern and the hard mask layer, and performing a first cleaning process. The method of claim 4, wherein And wherein the passivation layer is formed in a curvature formed at a boundary between the first and second insulating layers during the first cleaning process. The method of claim 1, And forming a second passivation step on the semiconductor substrate after forming the passivation layer. The method of claim 6, And the second cleaning step is performed under conditions that the first insulating film is more etched than the protective film. The method of claim 6, The second cleaning process is a contact hole forming method of a semiconductor device using HF solution. The method of claim 6, The HF solution is a contact hole forming method of a semiconductor device used by diluting to 50: 1 to 200: 1 in water. The method of claim 6, The method of claim 1, wherein the exposed sidewalls of the first insulating layer are removed during the second cleaning process. The method of claim 1, And etching the etch stop layer exposed to the lower portions of the contact holes using a light etching treatment (LET). The method of claim 11, The LET is a contact hole forming method of a semiconductor device using a gas mixed with CF 4 gas, Ar gas and O 2 gas.
KR1020080133123A 2008-12-24 2008-12-24 Method of forming contact hole in semiconductor device KR20100074634A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080133123A KR20100074634A (en) 2008-12-24 2008-12-24 Method of forming contact hole in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080133123A KR20100074634A (en) 2008-12-24 2008-12-24 Method of forming contact hole in semiconductor device

Publications (1)

Publication Number Publication Date
KR20100074634A true KR20100074634A (en) 2010-07-02

Family

ID=42637130

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080133123A KR20100074634A (en) 2008-12-24 2008-12-24 Method of forming contact hole in semiconductor device

Country Status (1)

Country Link
KR (1) KR20100074634A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11450610B2 (en) 2019-08-07 2022-09-20 Samsung Electronics Co., Ltd. Vertical semiconductor devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11450610B2 (en) 2019-08-07 2022-09-20 Samsung Electronics Co., Ltd. Vertical semiconductor devices

Similar Documents

Publication Publication Date Title
US7696087B2 (en) Method of forming a dual damascene pattern of a semiconductor device
CN107731730B (en) Method for forming semiconductor structure
KR20100074634A (en) Method of forming contact hole in semiconductor device
KR100683492B1 (en) Method for contact etch in semiconductor device
KR101038378B1 (en) Method of forming contact hole in semiconductor device
KR100376986B1 (en) Manufacturing method for semiconductor device
KR20100011483A (en) Method of forming contact plug in semiconductor device
KR20090001396A (en) Method for manufacturing semiconductor device
KR20080071809A (en) Method of forming semiconductor device
KR20090077299A (en) Method of forming a contact plug in semiconductor device
KR100723769B1 (en) Method of manufacturing in flash memory device
KR20080038854A (en) Method of manufacturing a flash memory device
JP2005183916A (en) Method of manufacturing flash device
KR100739971B1 (en) Method for forming contact hole in a semiconductor device
KR20090081119A (en) Contact plug of semiconductor device and forming method thereof
KR100843903B1 (en) Method for manufacturing of semiconductor device
KR100744002B1 (en) Method for fabricating the same of semiconductor device
KR20070055880A (en) Method for manufacturing semiconductor device
KR20110075206A (en) Semiconductor device and method for forming using the same
KR20080029021A (en) Method of forming a trench
KR20090044648A (en) Semiconductor device and method for fabrication of the same
KR20060068908A (en) Method of manufacturing in flash memory device
KR20070052440A (en) Method of manufacturing a nand type flash memory device
KR20100023458A (en) Method of manufacturing a semiconductor memory device
KR20090130683A (en) Method of forming contact plug in semiconductor device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination