KR20100023458A - Method of manufacturing a semiconductor memory device - Google Patents

Method of manufacturing a semiconductor memory device Download PDF

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Publication number
KR20100023458A
KR20100023458A KR1020080082221A KR20080082221A KR20100023458A KR 20100023458 A KR20100023458 A KR 20100023458A KR 1020080082221 A KR1020080082221 A KR 1020080082221A KR 20080082221 A KR20080082221 A KR 20080082221A KR 20100023458 A KR20100023458 A KR 20100023458A
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KR
South Korea
Prior art keywords
insulating film
forming
memory device
semiconductor memory
manufacturing
Prior art date
Application number
KR1020080082221A
Other languages
Korean (ko)
Inventor
박보민
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080082221A priority Critical patent/KR20100023458A/en
Publication of KR20100023458A publication Critical patent/KR20100023458A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present invention relates to a method of manufacturing a semiconductor memory device, the method comprising: forming gate patterns on a semiconductor substrate, forming spacers on sidewalls of the gate patterns, and forming a SAC insulating film and a second structure on the entire structure including the spacers. A method of manufacturing a semiconductor memory device, comprising: forming an insulating film, performing an etching process to expose the SAC insulating film, and performing a cleaning process to remove an overhang on the first insulating film. .

Description

Method of manufacturing a semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly, to a method for manufacturing a semiconductor memory device including a step of gap filling an insulating film in a region where a contact is formed.

In general, in the manufacture of a semiconductor memory device, a contact connected to a source / drain of a transistor enables electrical operation with a capacitor and a bit line.

Recently, as the degree of integration of semiconductor devices increases, the gap between conductive lines such as gate lines has narrowed, and thus, contact process margins have decreased. In order to secure such a contact process margin, a self aligned contact (SAC) process is being performed.

The technical problem of the present invention is to form a SAC insulating film, and then form an insulating film on the entire structure and perform a planarization process so that the SAC insulating film is exposed to expose voids present in the insulating film in the region where the contact is to be formed. Thereafter, a method of manufacturing a semiconductor memory device capable of performing a cleaning process to etch an inlet of a void to prevent overhang and to remove residues generated during a planarization process.

A method of manufacturing a semiconductor memory device according to an embodiment of the present invention includes forming gate patterns on a semiconductor substrate, forming spacers on sidewalls of the gate patterns, and forming a SAC insulating film on the entire structure including the spacers. And forming a first insulating film, performing an etching process to expose the SAC insulating film, and performing a cleaning process to remove an overhang on the first insulating film.

After removing the overhang, the method may further include forming a second insulating film on the entire structure including the first insulating film. The first insulating film and the second insulating film are formed of an HDP oxide film.

The etching process is performed by a chemical mechanical polishing (CMP) process. The chemical mechanical polishing process exposes the voids of the first insulating film.

The cleaning process removes the by-products generated during the etching process and etches the acid portions of the first insulating layer in a V-shape to remove the overhang. The washing step is carried out by mixing the CLN-R (H 2 SO 4 and H 2 O 2 ), BOE, NH 4 OH-based chemicals alone or mixed.

According to an embodiment of the present invention, after forming the SAC insulating film, an insulating film is formed on the entire structure and a planarization process is performed to expose the SAC insulating film to expose voids existing in the insulating film of the region where the contact is to be formed. Thereafter, a cleaning process may be performed to etch the inlet of the void to prevent overhang and to remove residues generated during the planarization process.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

1A to 1D are cross-sectional views of devices for describing a method of manufacturing a semiconductor memory device according to a first embodiment of the present invention.

Referring to FIG. 1A, a cell gate pattern Cell and a selection transistor pattern DST are formed on a semiconductor substrate 100. The cell gate pattern Cell and the selection transistor pattern DST are typically formed by stacking a tunnel insulating film, a floating gate film, a dielectric film, a control gate film, a metal gate film, and a hard mask film. The selection transistor pattern DST is described using a drain selection transistor as an example.

In the present invention, the cell gate pattern Cell and the selection transistor pattern DST are described as an example, but the present invention can be applied to a general contact forming method using an SAC process of a semiconductor device.

Referring to FIG. 1B, an insulating film is formed on the entire structure including the cell gate patterns Cell and the selection transistor pattern DST. Thereafter, an etching process is performed to form an spacer layer 102 by leaving an insulating layer in the space between the cell gate patterns Cell and the sidewall of the selection transistor pattern DST. The spacer film 102 is preferably formed of an oxide film.

Thereafter, the SAC insulating film 103 is formed over the entire structure including the spacer film 102. The SAC insulating film 103 is preferably formed of a nitride film. The SAC insulating film 103 is preferably formed to a thickness of 200 to 1000 Å.

Referring to FIG. 1C, the first insulating film 104 is formed on the entire structure including the SAC insulating film 103. The first insulating film 104 is preferably formed of an HDP oxide film. The first insulating film 104 is preferably formed to a thickness of 500 to 5000 kPa.

Thereafter, a chemical mechanical polishing (CMP) process is performed to expose the spacer film 102.

As a result, voids generated in the first insulating layer 104 embedded in the region where the contact is formed, that is, the space between the selection transistors DST are exposed. In this case, the exposed void may be overhanged as shown in the drawing.

Referring to FIG. 1D, a cleaning process is performed to remove etch residues generated during the above-described chemical mechanical polishing (CMP) process, and at the same time, the overhang portion of the void is etched and removed. In more detail, the overhang of the void portion exposed to the upper end of the first insulating layer 104 is etched to form a slope in a V shape.

Washing step is preferably performed alone or in combination with a chemical of CLN-R (H 2 SO 4 and H 2 O 2), BOE, NH 4 OH series.

Thereafter, the second insulating film 105 is formed over the entire structure including the first insulating film 104. The second insulating film 105 is formed of an HDP oxide film. The second insulating film 105 is formed without the occurrence of voids by the upper end of the first insulating film 104 formed to have a slope in a V-shape. The second insulating film 105 is preferably formed to a thickness of 2000 to 8000.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1D are cross-sectional views of devices for describing a method of manufacturing a semiconductor memory device according to a first embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100 semiconductor substrate 102 spacer film

103: SAC insulating film 104: first insulating film

105: first insulating film

Claims (12)

Forming gate patterns on the semiconductor substrate; Forming a spacer on sidewalls of the gate patterns; Forming a SAC insulating film and a first insulating film on the entire structure including the spacers; Performing an etching process to expose the SAC insulating film; And Performing a cleaning process to remove an overhang on the first insulating layer. The method of claim 1, After removing the overhang, And forming a second insulating film on the entire structure including the first insulating film. The method of claim 2, And the first insulating film and the second insulating film are formed of an HDP oxide film. The method of claim 1, The etching process is a method of manufacturing a semiconductor memory device performed by a chemical mechanical polishing (CMP) process. The method of claim 4, wherein The chemical mechanical polishing process exposes the voids of the first insulating film. The method of claim 1, The cleaning process removes the by-products generated during the etching process and simultaneously removes the overhang by etching the acid portions of the first insulating layer into a V-shape. The method of claim 1, The cleaning process is a method for manufacturing a semiconductor memory device, which is performed by using CLN-R (H 2 SO 4 and H 2 O 2 ), BOE, NH 4 OH-based chemicals alone or mixed. Forming gate patterns on the semiconductor substrate; Forming a spacer on sidewalls of the gate patterns; Forming a SAC insulating film and a first insulating film on the entire structure including the spacers; Performing an etching process to expose the SAC insulating film and to expose voids inside the first insulating film; And Performing a cleaning process to remove the by-products of the etching process and at the same time to remove the overhang of the exposed voids. The method of claim 8, After removing the overhang, And forming a second insulating film on the entire structure including the first insulating film. The method of claim 9, And the first insulating film and the second insulating film are formed of an HDP oxide film. The method of claim 8, The etching process is a method of manufacturing a semiconductor memory device performed by a chemical mechanical polishing (CMP) process. The method of claim 8, The cleaning process is a method for manufacturing a semiconductor memory device, which is performed by using CLN-R (H 2 SO 4 and H 2 O 2 ), BOE, NH 4 OH-based chemicals alone or mixed.
KR1020080082221A 2008-08-22 2008-08-22 Method of manufacturing a semiconductor memory device KR20100023458A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080082221A KR20100023458A (en) 2008-08-22 2008-08-22 Method of manufacturing a semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080082221A KR20100023458A (en) 2008-08-22 2008-08-22 Method of manufacturing a semiconductor memory device

Publications (1)

Publication Number Publication Date
KR20100023458A true KR20100023458A (en) 2010-03-04

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KR1020080082221A KR20100023458A (en) 2008-08-22 2008-08-22 Method of manufacturing a semiconductor memory device

Country Status (1)

Country Link
KR (1) KR20100023458A (en)

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