KR100964273B1 - Method for fabricating pillar pattern - Google Patents

Method for fabricating pillar pattern Download PDF

Info

Publication number
KR100964273B1
KR100964273B1 KR1020070135305A KR20070135305A KR100964273B1 KR 100964273 B1 KR100964273 B1 KR 100964273B1 KR 1020070135305 A KR1020070135305 A KR 1020070135305A KR 20070135305 A KR20070135305 A KR 20070135305A KR 100964273 B1 KR100964273 B1 KR 100964273B1
Authority
KR
South Korea
Prior art keywords
pillar
pattern
hard mask
film
layer
Prior art date
Application number
KR1020070135305A
Other languages
Korean (ko)
Other versions
KR20090067598A (en
Inventor
강혜란
김광옥
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070135305A priority Critical patent/KR100964273B1/en
Publication of KR20090067598A publication Critical patent/KR20090067598A/en
Application granted granted Critical
Publication of KR100964273B1 publication Critical patent/KR100964273B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 필라패턴을 형성하기 위한 게이트 하드마스크막의 과도손실을 방지하는 필라패턴의 제조 방법을 제공하기 위한 것으로, 이를 위해 기판 상에 패드산화막, 게이트하드마스크막 및 식각보호막을 적층하는 단계; 하드마스크막을 식각장벽으로 상기 식각보호막을 식각하여 식각보호막패턴을 형성하는 단계; 상기 식각보호막패턴을 식각장벽으로 상기 게이트하드마스크막과 패드산화막을 식각하여 게이트하드마스크막패턴과 패드산화막패턴을 형성하는 단계; 상기 식각보호막패턴을 식각장벽으로 상기 기판을 식각하여 필라헤드를 형성하는 단계; 상기 식각보호막패턴, 게이트하드마스크막패턴, 패드산화막패턴 및 필라헤드의 측벽에 측벽보호막을 형성하는 단계; 및 상기 기판에 대한 등방성 식각 공정을 진행하여 필라넥을 형성하는 단계를 포함함으로써, 채널이 상/하로 형성되는 반도체 소자의 안정적인 동작 특성을 확보한다.The present invention is to provide a method of manufacturing a pillar pattern to prevent the transient loss of the gate hard mask layer for forming the pillar pattern, for this purpose, the step of laminating a pad oxide film, a gate hard mask film and an etching protection film on the substrate; Forming an etch passivation layer pattern by etching the etch passivation layer using the hard mask layer as an etch barrier; Etching the gate hard mask layer and the pad oxide layer using the etch barrier layer as an etch barrier to form a gate hard mask layer pattern and a pad oxide layer pattern; Forming a pillar head by etching the substrate using the etching protection layer pattern as an etch barrier; Forming a sidewall passivation layer on sidewalls of the etch passivation layer pattern, the gate hard mask layer pattern, the pad oxide layer pattern, and the pillar head; And forming a pillar neck by performing an isotropic etching process on the substrate, thereby securing stable operating characteristics of the semiconductor device having channels formed up and down.

게이트 하드마스크막, 식각보호막, 필라, 필라패턴 Gate hard mask layer, etch protection layer, pillar, pillar pattern

Description

필라패턴 제조 방법{METHOD FOR FABRICATING PILLAR PATTERN}Pillar pattern manufacturing method {METHOD FOR FABRICATING PILLAR PATTERN}

본 발명은 반도체 소자의 제조 기술에 관한 것으로, 특히 채널이 상/하로 형성되는 반도체 소자의 필라패턴 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly, to a method of manufacturing a pillar pattern of a semiconductor device in which channels are formed up and down.

반도체 소자의 대용량화는, 넷다이(net die)의 감소와 같은 생산성 저하의 원인이 되며, 칩 사이즈(chip size)를 증가시키는 원인이 된다. 이를 극복하고자 디자인룰(design rule)을 감소시키는 미세화 작업이 이루어지고 있으며, 하나의 대안으로 채널이 상/하로 형성되는 트랜지스터가 제안되었다. 그리고, 상기 트랜지스터는 상/하의 채널을 유도하고자, 기둥형상의 필라패턴을 포함한다.Increasing the capacity of the semiconductor device causes a decrease in productivity such as a decrease in the net die, and increases the chip size. In order to overcome this problem, miniaturization has been made to reduce design rules. As an alternative, transistors having channels formed up and down have been proposed. In addition, the transistor includes a pillar-shaped pillar pattern to induce up and down channels.

도 1a 내지 도 1c는 종래기술에 따른 필라패턴의 제조 방법을 나타낸 공정단면도이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a pillar pattern according to the related art.

도 1a에 도시된 바와 같이, 기판(11) 상에 패드산화막(12), 게이트 하드마스크막(13), 비정질카본막(14), 실리콘산화질화막(15), 반사방지막(16) 및 포토레지스트패턴(17)을 순차적으로 형성한다. 여기서, 게이트 하드마스크막(13)은 질화막으로 형성한다.As shown in FIG. 1A, a pad oxide film 12, a gate hard mask film 13, an amorphous carbon film 14, a silicon oxynitride film 15, an antireflection film 16, and a photoresist are disposed on a substrate 11. The pattern 17 is formed sequentially. Here, the gate hard mask film 13 is formed of a nitride film.

이어서, 포토레지스트패턴(17)을 식각장벽으로, 반사방지막(16), 실리콘산화질화막(15), 비정질카본막(14), 게이트 하드마스크막(13) 및 패드산화막(12)을 순차적으로 식각한다. 이때, 포토레지스트패턴(17), 반사방지막(16), 실리콘산화질화막(15) 및 비정질카본막(14)은 식각 중 소모되어 제거되거나, 별도의 제거 공정을 진행하여 제거한다.Subsequently, the anti-reflection film 16, the silicon oxynitride film 15, the amorphous carbon film 14, the gate hard mask film 13, and the pad oxide film 12 are sequentially etched using the photoresist pattern 17 as an etch barrier. do. In this case, the photoresist pattern 17, the antireflection film 16, the silicon oxynitride film 15, and the amorphous carbon film 14 are consumed and removed during etching, or are removed by a separate removal process.

도 1b에 도시된 바와 같이, 게이트 하드마스크막(13)을 식각장벽으로 기판(11)을 식각하여 필라헤드(18A, pillar head)를 형성한다.As shown in FIG. 1B, a pillar head 18A is formed by etching the substrate 11 using the gate hard mask layer 13 as an etch barrier.

도 1c에 도시된 바와 같이, 게이트 하드마스크막(13A), 패드산화막(12) 및 필라헤드(18A)의 측벽에 스페이서 형상(spacer profile)의 측벽보호막(19)을 형성한 후, 기판(11)에 대한 등방성식각 공정을 진행하여 필라넥(20, pillar neck)을 형성한다. 이때, 측벽보호막(19)은 질화막으로 형성하며, 등방성식각 공정은 CF4와 CH2F2를 포함하는 식각가스로 진행한다.As shown in FIG. 1C, after forming a spacer profile sidewall protective film 19 on sidewalls of the gate hard mask film 13A, the pad oxide film 12, and the pillar head 18A, the substrate 11 is formed. Isotropic etching process to form a pillar neck (20, pillar neck). At this time, the sidewall protective film 19 is formed of a nitride film, the isotropic etching process proceeds to the etching gas containing CF 4 and CH 2 F 2 .

이로써, 필라헤드(18A)와 필라넥(20)을 포함하는 필라패턴이 형성된다.As a result, a pillar pattern including the pillar head 18A and the pillar neck 20 is formed.

그러나, 필라헤드(18A)를 형성하는 과정에서 게이트 하드마스크막(13)의 과도손실(13B)이 발생하며, 이에 따라 잔류하는 게이트 하드마스크막(13A)의 두께가 700Å이하가 된다. 그리고, 게이트 하드마스크막(13)의 과도손실(13B)은 필라헤드(18A)를 보호하는 박막으로 작용하는 본연의 작용효과를 도출해낼 수 없음을 의미한다. 일반적으로 게이트 하드마스크막(13A)은 1000~1500Å의 두께로 잔류하는 것이 바람직하다. 또한, 필라넥(20)을 형성하기 위해 사용한 CF4와 CH2F2를 포함하 는 식각가스는 측벽보호막(19)과의 식각선택비가 낮아 게이트 하드마스크막(13A)과 필라헤드(18)의 측벽이 손실되는 문제점이 발생한다.However, in the process of forming the pillar head 18A, a transient loss 13B of the gate hard mask film 13 occurs, so that the thickness of the remaining gate hard mask film 13A becomes 700 Å or less. In addition, the transient loss 13B of the gate hard mask film 13 means that a natural working effect of the thin film protecting the pillar head 18A cannot be derived. Generally, it is preferable that the gate hard mask film 13A remain at a thickness of 1000 to 1500 kPa. In addition, the etching gas containing CF 4 and CH 2 F 2 used to form the pillar neck 20 has a low etching selectivity with respect to the sidewall protective layer 19, and thus the gate hard mask layer 13A and the pillar head 18. A problem arises in that the sidewalls of are lost.

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로서, 필라패턴을 형성하기 위한 게이트 하드마스크막의 과도손실을 방지하는 필라패턴의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a method of manufacturing a pillar pattern for preventing a transient loss of a gate hard mask layer for forming the pillar pattern.

상기의 목적을 달성하기 위한 본 발명의 필라패턴 제조 방법은 기판 상에 패드산화막, 게이트하드마스크막 및 식각보호막을 적층하는 단계; 하드마스크막을 식각장벽으로 상기 식각보호막을 식각하여 식각보호막패턴을 형성하는 단계; 상기 식각보호막패턴을 식각장벽으로 상기 게이트하드마스크막과 패드산화막을 식각하여 게이트하드마스크막패턴과 패드산화막패턴을 형성하는 단계; 상기 식각보호막패턴을 식각장벽으로 상기 기판을 식각하여 필라헤드를 형성하는 단계; 상기 식각보호막패턴, 게이트하드마스크막패턴, 패드산화막패턴 및 필라헤드의 측벽에 측벽보호막을 형성하는 단계; 및 상기 기판에 대한 등방성 식각 공정을 진행하여 필라넥을 형성하는 단계를 포함한다.The pillar pattern manufacturing method of the present invention for achieving the above object comprises the steps of laminating a pad oxide film, a gate hard mask film and an etching protection film on a substrate; Forming an etch passivation layer pattern by etching the etch passivation layer using the hard mask layer as an etch barrier; Etching the gate hard mask layer and the pad oxide layer using the etch barrier layer as an etch barrier to form a gate hard mask layer pattern and a pad oxide layer pattern; Forming a pillar head by etching the substrate using the etching protection layer pattern as an etch barrier; Forming a sidewall passivation layer on sidewalls of the etch passivation layer pattern, the gate hard mask layer pattern, the pad oxide layer pattern, and the pillar head; And forming a pillar neck by performing an isotropic etching process on the substrate.

상술한 바와 같은 과제 해결 수단을 바탕으로 하는 본 발명은, 게이트 하드마스크막의 과도손실을 방지하여 필라패턴을 안정적으로 보호한다.The present invention, which is based on the above-described problem solving means, prevents the transient loss of the gate hard mask film to stably protect the pillar pattern.

이로써, 채널이 상/하로 형성되는 반도체 소자의 안정적인 동작 특성을 확보할 수 있으며, 나아가 반도체 소자의 수율을 증가시킬 수 있는 효과를 갖는다.As a result, it is possible to secure stable operating characteristics of the semiconductor device in which channels are formed up and down, and further increase the yield of the semiconductor device.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위해 본 발명의 가장 바람직한 실시예를 첨부한 도면을 참조하여 설명한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

도 2a 내지 도 2f는 본 발명의 실시예에 따른 필라패턴의 제조 방법을 나타낸 공정단면도이다.2A to 2F are cross-sectional views illustrating a method of manufacturing a pillar pattern according to an exemplary embodiment of the present invention.

도 2a에 도시된 바와 같이, 기판(31) 상에 패드산화막(32), 게이트 하드마스크막(33), 식각보호막(34) 및 다층의 하드마스크막을 형성한다.As shown in FIG. 2A, a pad oxide film 32, a gate hard mask film 33, an etch protection film 34, and a multilayer hard mask film are formed on the substrate 31.

패드산화막(32)은 게이트 하드마스크막(33)과 기판(31)간의 박막 스트레스(film stress)를 완화하고자 형성된 박막이다. 그리고, 게이트 하드마스크막(33)은 기판(31)을 식각하여 필라패턴을 형성하고, 이후 공정에서 필라패턴을 보호하는 박막이다. 이를 위해 게이트 하드마스크막(33)은 질화막으로 형성한다.The pad oxide film 32 is a thin film formed to relieve the film stress between the gate hard mask film 33 and the substrate 31. The gate hard mask layer 33 is a thin film which forms a pillar pattern by etching the substrate 31 and protects the pillar pattern in a subsequent process. To this end, the gate hard mask film 33 is formed of a nitride film.

식각보호막(34)은 필라패턴을 형성하는 과정에서 게이트 하드마스크막(33)의 과도손실을 방지하고자 형성된 박막이다. 이를 위해 식각보호막(34)은 산화막으로 형성하며, 400~900Å의 두께를 갖는다.The etching protection layer 34 is a thin film formed to prevent excessive loss of the gate hard mask layer 33 in the process of forming the pillar pattern. To this end, the etching protection film 34 is formed of an oxide film and has a thickness of 400 ~ 900Å.

그리고, 다층의 하드마스크막은 비정질카본막(35), 실리콘산화질화막(36, SiON), 반사방지막(37) 및 포토레지스트 패턴(38)이 순차적으로 형성된 적층막이다.The multilayer hard mask film is a laminated film in which an amorphous carbon film 35, a silicon oxynitride film 36 (SiON), an antireflection film 37, and a photoresist pattern 38 are sequentially formed.

도 2b에 도시된 바와 같이, 포토레지스트 패턴(38)을 식각장벽으로 반사방지막(37)과 실리콘산화질화막(36)을 식각한 후, 식각된 실리콘산화질화막(36A)을 식각장벽으로 비정질카본막(35)을 식각한다. 그리고, 비정질카본막(35)을 식각하는 과정에서 포토레지스트 패턴(38)과 반사방지막(37)은 소모되어 제거된다.As shown in FIG. 2B, the anti-reflection film 37 and the silicon oxynitride film 36 are etched using the photoresist pattern 38 as an etch barrier, and the etched silicon oxynitride film 36A is used as the etch barrier. Etch (35). In the process of etching the amorphous carbon film 35, the photoresist pattern 38 and the anti-reflection film 37 are consumed and removed.

이어서, 식각된 비정질카본막(35A)을 식각장벽으로 식각보호막(34)을 식각하여 식각보호막패턴(34A)을 형성한 후, 이를 식각장벽으로 게이트 하드마스크막(33)과 패드산화막(32)을 식각하여 게이트 하드마스크막패턴(33A)과 패드산화막패턴(32A)을 형성한다. 그리고, 게이트 하드마스크막(33)을 식각하는 과정에서 실리콘산화질화막(36A)은 소모되어 제거된다.Subsequently, the etch protective film 34 is etched using the etched amorphous carbon film 35A as an etch barrier to form an etch passivation pattern 34A, and then the gate hard mask film 33 and the pad oxide film 32 are used as the etch barrier. Etching to form a gate hard mask film pattern 33A and a pad oxide film pattern 32A. The silicon oxynitride layer 36A is consumed and removed in the process of etching the gate hard mask layer 33.

이후, 비정질카본막(35A)을 제거한다.Thereafter, the amorphous carbon film 35A is removed.

도 2c에 도시된 바와 같이, 식각보호막패턴(34A)을 식각장벽으로 기판(31)을 식각하여 필라헤드(39)를 형성한다. As illustrated in FIG. 2C, the pillar head 39 is formed by etching the substrate 31 using the etch protection layer pattern 34A as an etch barrier.

필라헤드(39)의 형성은 CH2F2를 포함하는 식각가스를 사용한다. 이때, CH2F2를 포함하는 식각가스는 질화막보다 산화막에 더 높은 식각선택비를 나타내는바, 필라헤드(39) 형성시 식각보호막패턴(34A)의 과도손실은 발생하지 않는다. 또한, 식각보호막패턴(34A)의 과도손실이 발생하지 않아서 게이트 하드마스크막패턴(33A)의 손실은 방지된다.Formation of the pillar head 39 uses an etching gas containing CH 2 F 2 . At this time, the etching gas containing CH 2 F 2 shows a higher etching selectivity to the oxide film than the nitride film, so that the transient loss of the etching protection layer pattern 34A does not occur when the pillar head 39 is formed. In addition, since the excessive loss of the etching protection film pattern 34A does not occur, the loss of the gate hard mask film pattern 33A is prevented.

도 2d에 도시된 바와 같이, 식각보호막패턴(34A), 게이트 하드마스크막패턴(33A) 및 필라헤드(39)의 측벽에 측벽보호막(40)을 형성한다.As shown in FIG. 2D, the sidewall passivation layer 40 is formed on sidewalls of the etch passivation layer pattern 34A, the gate hard mask layer pattern 33A, and the pillar head 39.

측벽보호막(40)은 산화막, 특히 단차피복성이 우수한 HTO(high temperature oxide)막의 증착 및 에치백(etch back) 공정으로 형성하며, 스페이서 형상을 갖는다. 그리고, 측벽보호막(40)은 50~150Å으로 형성한다.The sidewall protective layer 40 is formed by depositing and etching back an oxide film, particularly a high temperature oxide (HTO) film having excellent step coverage. The sidewall protective layer 40 has a spacer shape. The sidewall protective film 40 is formed of 50 to 150 microns.

도 2e에 도시된 바와 같이, 기판(31)에 대한 등방성 식각 공정을 진행하여 필라넥(41)을 형성한다.As shown in FIG. 2E, an isotropic etching process is performed on the substrate 31 to form the pillar neck 41.

등방성 식각 공정은 CF4, CH2F2 및 O2를 포함하는 식각가스로 진행한다. 이때, 측벽보호막(40), 즉 산화막은 CH2F2가스에 대한 선택비가 우수하기 때문에 과도손실이 발생하지 않으며, 이에 따라 게이트 하드마스크막패턴(33A) 및 필라헤드(39)의 측벽은 안전하게 보호된다.The isotropic etching process proceeds with an etching gas containing CF 4 , CH 2 F 2 and O 2 . At this time, since the sidewall passivation layer 40, that is, the oxide layer has an excellent selectivity to the CH 2 F 2 gas, no excessive loss occurs, and thus the sidewalls of the gate hard mask layer pattern 33A and the pillar head 39 are safely secured. Protected.

도 2f에 도시된 바와 같이, 식각보호막패턴(34A)을 제거한다.As shown in FIG. 2F, the etching protection layer pattern 34A is removed.

식각보호막패턴(34A)의 제거는 부분 화학적기계적연마(partial chemical mechanical polishing) 공정, 또는 에치백 공정으로 진행하며, 이때, 식각보호막패턴(34A)의 측벽에 형성된 측벽보호막(40)까지 제거한다.The etching protection layer pattern 34A may be removed by a partial chemical mechanical polishing process or an etch back process. At this time, the sidewall protection layer 40 formed on the sidewall of the etching protection layer pattern 34A may be removed.

이로써, 필라패턴이 형성된다.As a result, a pillar pattern is formed.

전술한 바와 같은 본 발명의 실시예는, 필라패턴 형성시 발생하는 게이트 하드마스크막패턴(33A)의 과도손실을 방지하고자, 게이트 하드마스크막패턴(33A) 상에 식각보호막패턴(34A)을 형성한다. 식각보호막패턴(34A)은 산화막으로 이루어지며, 필라헤드(39)를 형성하기 위한 식각가스와의 식각선택비가 높아 게이트 하드마스크막패턴(33A)을 안정적으로 보호한다.As described above, the etching protection layer pattern 34A is formed on the gate hard mask layer pattern 33A in order to prevent excessive loss of the gate hard mask layer pattern 33A generated when the pillar pattern is formed. do. The etching protection layer pattern 34A is formed of an oxide layer, and thus, the etching protection ratio with the etching gas for forming the pillar head 39 is high, thereby stably protecting the gate hard mask layer pattern 33A.

또한, 측벽보호막(40)을 산화막으로 형성하여, 필라넥(41)을 형성하기 위한 식각가스와의 식각선택비를 높여 게이트 하드마스크막패턴(33A)의 측벽을 보호한다.In addition, the sidewall protection layer 40 is formed of an oxide film to increase the etching selectivity with the etching gas for forming the pillar neck 41 to protect the sidewall of the gate hard mask layer pattern 33A.

그리고, 게이트 하드마스크막패턴(33A)의 손실 방지를 통해, 안정적으로 필라헤드(39)를 보호하며, 나아가 필라패턴을 보호할 수 있다. 즉, 게이트 하드마스크막패턴(33A)의 두께를 1000~1500Å으로 유지시켜, 필라패턴을 보호하는 것이다.In addition, the pillar head 39 may be stably protected through the loss prevention of the gate hard mask layer pattern 33A, and the pillar pattern may be protected. That is, the thickness of the gate hard mask film pattern 33A is maintained at 1000 to 1500 mW to protect the pillar pattern.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

도 1a 내지 도 1c는 종래기술에 따른 필라패턴의 제조 방법을 나타낸 공정단면도.1A to 1C are cross-sectional views illustrating a method of manufacturing a pillar pattern according to the related art.

도 2a 내지 도 2f는 본 발명의 실시예에 따른 필라패턴의 제조 방법을 나타낸 공정단면도.2A to 2F are cross-sectional views illustrating a method of manufacturing a pillar pattern according to an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

31 : 기판 32 : 패드산화막31 substrate 32 pad oxide film

33 : 게이트 하드마스크막 34 : 식각보호막33: gate hard mask film 34: etching protection film

35 : 비정질카본막 36 : 실리콘산화질화막35 amorphous carbon film 36 silicon oxynitride film

37 : 반사방지막 38 : 포토레지스트 패턴37 antireflection film 38 photoresist pattern

Claims (7)

기판 상에 패드산화막, 게이트하드마스크막 및 식각보호막을 적층하는 단계;Depositing a pad oxide film, a gate hard mask film, and an etch protection film on the substrate; 하드마스크막을 식각장벽으로 상기 식각보호막을 식각하여 식각보호막패턴을 형성하는 단계;Forming an etch passivation layer pattern by etching the etch passivation layer using the hard mask layer as an etch barrier; 상기 식각보호막패턴을 식각장벽으로 상기 게이트하드마스크막과 패드산화막을 식각하여 게이트하드마스크막패턴과 패드산화막패턴을 형성하는 단계;Etching the gate hard mask layer and the pad oxide layer using the etch barrier layer as an etch barrier to form a gate hard mask layer pattern and a pad oxide layer pattern; 상기 식각보호막패턴을 식각장벽으로 상기 기판을 식각하여 필라헤드를 형성하는 단계;Forming a pillar head by etching the substrate using the etching protection layer pattern as an etch barrier; 상기 식각보호막패턴, 게이트하드마스크막패턴, 패드산화막패턴 및 필라헤드의 측벽에 측벽보호막을 형성하는 단계; 및Forming a sidewall passivation layer on sidewalls of the etch passivation layer pattern, the gate hard mask layer pattern, the pad oxide layer pattern, and the pillar head; And 상기 기판에 대한 등방성 식각 공정을 진행하여 필라넥을 형성하는 단계Forming a pillar neck by performing an isotropic etching process on the substrate; 를 포함하는 필라패턴 제조 방법.Pillar pattern manufacturing method comprising a. 제1항에 있어서,The method of claim 1, 상기 게이트 하드마스크막을 질화막으로 형성하고, 상기 식각보호막을 산화막으로 형성하는 필라패턴 제조 방법.Forming the gate hard mask layer as a nitride layer, and forming the etch protection layer as an oxide layer. 제1항에 있어서,The method of claim 1, 상기 필라헤드를 형성하는 단계는 CH2F2를 포함하는 식각가스로 진행하는 필라패턴 제조 방법.Forming the pillar head is a pillar pattern manufacturing method that proceeds to the etching gas containing CH 2 F 2 . 제1항에 있어서,The method of claim 1, 상기 측벽보호막을 산화막으로 형성하는 필라패턴 제조 방법.The pillar pattern manufacturing method of forming the sidewall protective film of an oxide film. 제1항에 있어서,The method of claim 1, 상기 필라넥을 형성하는 단계는 CH2F2를 포함하는 식각가스로 진행하는 필라패턴 제조 방법.Forming the pillar neck is a pillar pattern manufacturing method that proceeds to the etching gas containing CH 2 F 2 . 제1항에 있어서,The method of claim 1, 상기 필라넥을 형성하는 단계는 CF4, CH2F2 및 O2를 포함하는 식각가스로 진행하는 필라패턴 제조 방법.Forming the pillar neck is a pillar pattern manufacturing method that proceeds to the etching gas containing CF 4 , CH 2 F 2 and O 2 . 제1항에 있어서,The method of claim 1, 상기 하드마스크막은 적어도 비정질카본막과 실리콘산화질화막이 적층된 적층막을 포함하는 필라패턴 제조 방법.The hard mask film is a pillar pattern manufacturing method comprising a laminated film laminated at least an amorphous carbon film and a silicon oxynitride film.
KR1020070135305A 2007-12-21 2007-12-21 Method for fabricating pillar pattern KR100964273B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070135305A KR100964273B1 (en) 2007-12-21 2007-12-21 Method for fabricating pillar pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070135305A KR100964273B1 (en) 2007-12-21 2007-12-21 Method for fabricating pillar pattern

Publications (2)

Publication Number Publication Date
KR20090067598A KR20090067598A (en) 2009-06-25
KR100964273B1 true KR100964273B1 (en) 2010-06-16

Family

ID=40995298

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070135305A KR100964273B1 (en) 2007-12-21 2007-12-21 Method for fabricating pillar pattern

Country Status (1)

Country Link
KR (1) KR100964273B1 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070036200A (en) * 2005-09-29 2007-04-03 주식회사 하이닉스반도체 Method for manufacturing recess gate in semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070036200A (en) * 2005-09-29 2007-04-03 주식회사 하이닉스반도체 Method for manufacturing recess gate in semiconductor device

Also Published As

Publication number Publication date
KR20090067598A (en) 2009-06-25

Similar Documents

Publication Publication Date Title
US8946026B2 (en) Methods of fabricating a semiconductor device including metal gate electrodes
KR100949265B1 (en) Method for fabricating semiconductor device
CN107346759B (en) Semiconductor structure and manufacturing method thereof
CN115775766B (en) Forming method of shallow trench isolation structure and forming method of semiconductor device
TW201712867A (en) Method for forming semiconductor device structure
KR100824995B1 (en) Method for manufacturing semiconductor device with recess gate
KR100964273B1 (en) Method for fabricating pillar pattern
KR101316058B1 (en) Method for fabricating a semiconductor device
CN110911342A (en) Shallow trench isolation structure and preparation method thereof
KR101045092B1 (en) Method for fabricating semiconductor device
CN110534499B (en) Semiconductor device and method for manufacturing the same
KR100991382B1 (en) Transistor having multi-plane channel and method for forming the same
KR100875653B1 (en) Method of forming fine pattern of semiconductor device
TWI455206B (en) Method of etching oxide layer and nitride layer
KR100842762B1 (en) Method for manufacturing semiconductor device with recess gate
KR20060122578A (en) Method for forming hard mask in semiconductor memory device
US20100055912A1 (en) Semiconductor fabricating process
CN111725137B (en) Method for forming semiconductor device
CN108807267B (en) Semiconductor device and method for manufacturing the same
KR100998959B1 (en) Method for manufacturing of flash memory device
US8093153B2 (en) Method of etching oxide layer and nitride layer
US8298950B2 (en) Method of etching sacrificial layer
KR20090072090A (en) Method of manufacturing semiconductor device
CN115911000A (en) Semiconductor device and method of forming the same
KR20090022381A (en) Method for fabricating contact plug in semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee