KR20090054852A - Liquid crystal display device - Google Patents

Abstract

An LCD is provided to obtain the same effects as over driving for gradation voltage of the rest level even with respect to gradation voltage of the highest level when performing over driving for video implementation by using lower driving voltage of a data driver IC. An LCD(Liquid Crystal Display) comprises a timing controller(130), a data driver(120), a gate driver(110), a charge pumping circuit part(300), and an LC panel(100). When over driving is performed, the timing controller selects/outputs data, set with gradation voltage except highest gradation, with an over driven value than a normal value. Data set with highest gradation is selected/outputted with the normal value. The data driver stores data from the timing controller, and selects/outputs corresponding gradation voltage according to the data information. The charge pumping circuit part performs pumping up of the highest gradation voltage outputted from the data driver when the over driving of the timing controller is performed. The LC panel implements an image by the gradation voltage provided from the charge pumping circuit part.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to overdriving to a value higher than a normal value using data of red (R), green (G), and blue (B) for setting a gray scale voltage in units of frames. The present invention relates to a liquid crystal display having a charge pumping circuit that enables overdriving (or pumping-up) of the highest gray level even in a low driving voltage range of a data drive IC.

In general, a liquid crystal display device displays an image by controlling light transmittance for each liquid crystal cell according to pixel voltage. Recently, the liquid crystal display device has a light weight, thin shape, low power consumption, and is applicable to office automation equipment, audio and video equipment, and the like. As a result, the scope of application is gradually increasing.

The liquid crystal display device includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix form and driven by a data signal and a gate on signal to implement an image, a gate driver for supplying a gate on signal to each gate line of the liquid crystal panel, And a data driver for supplying a data signal to each data line of the liquid crystal panel.

In addition, a storage capacitor is formed in each of the liquid crystal cells, which is formed between the pixel electrode of the liquid crystal cell and the previous gate line or between the pixel electrode and the common electrode of the liquid crystal cell to maintain a constant voltage of the liquid crystal cell. Perform

When the turn-on signal is sequentially applied to the gate line of the liquid crystal panel, a data signal is applied to the pixel electrode of the corresponding line to realize an image.

Of course, such an image may be classified into a still image consisting of one frame and a still image consisting of a plurality of frames sequentially applied to the moving image.

In particular, when a moving image is implemented on the liquid crystal panel, the liquid crystal on the liquid crystal panel continuously changes by the size of the data signal corresponding to each frame. For example, in order to display a moving image of five consecutive frames on the liquid crystal panel, since each data signal of each frame has a different size, each liquid crystal continuously changes by the size of the data signal corresponding to each frame. Done.

At this time, the magnitude of the data signal corresponding to each frame is represented by the magnitude of the gray voltage in the liquid crystal layer to change the direction of the liquid crystal molecules forming the liquid crystal layer, so the response speed of the liquid crystal molecules forming the liquid crystal layer is Significantly depends on the change.

1 is a waveform diagram illustrating a driving state of a frame when a video is implemented in a general liquid crystal display.

As shown in FIG. 1, a general liquid crystal display device has a data signal corresponding to a current frame when a gradation voltage applied to a liquid crystal is changed from a low gradation voltage to a high gradation voltage (or from a high gradation voltage to a low gradation voltage). Since the gradation voltage of is affected by the gradation voltage of the data signal corresponding to the previous frame, the gradation voltage does not reach the desired gradation voltage immediately and reaches the normal gradation voltage only after several frames have elapsed.

For example, when a single video composed of two consecutive frames is implemented, the liquid crystal maintains a state changed to the magnitude of the gray voltage corresponding to the image of the first frame, and then the gray voltage corresponding to the image of the second frame. Since the response speed of the liquid crystal molecules is substantially slow, the liquid crystal does not sufficiently express the magnitude of the gray scale voltage corresponding to the image of the second frame within one frame time.

As a result, when the video is implemented, a problem of an afterimage in which two images overlap with each other in a liquid crystal panel is generated.

Recently, in order to solve such a problem, an overdriving circuit has improved the response speed of liquid crystal molecules through the grayscale voltage selected according to the converted data signal by overdriving the data signal for setting the grayscale voltage to a higher value than the normal value. A liquid crystal display device with an over driving circuit (ODC) has been proposed.

Hereinafter, a liquid crystal display device provided with a conventional ODC will be briefly described with reference to the accompanying drawings.

2 is a block diagram of a liquid crystal display device equipped with a prior art ODC.

As shown in FIG. 2, the conventional liquid crystal display device includes a liquid crystal panel 40 in which a plurality of gate lines GL1 to GLn and data lines DL1 to DLm cross each other to define a plurality of matrix pixel areas. And a driving circuit unit (not shown) for implementing an image on the liquid crystal panel 40.

Here, the driving circuit unit is connected to the external memory unit 36 of the EEPROM (Electrically Erasable and Programmable Read Only Memory) in which information in the form of a look-up table for overdriving driving is stored, and through the connector 20. A voltage is applied to the system to boost or step down to output the driving voltages Vcc and Vdd necessary for each sub-drive unit, and output the gate low voltage signal Vgl and the gate high voltage signal Vgh according to the operation signal of the timing controller 30. The output DC-DC converter 25 and the data information stored in the form of a look-up table of the external storage unit 36 when the power is applied are read and stored in the built-in ODC 31 and input from the system. A tie for outputting the corrected video signal (Do DATA) for overdriving and an operation signal for the operation of the DC-DC converter 25 based on the look-up table data. A scan pulse is generated by receiving the gate high voltage signal Vgh and the gate low voltage signal Vgl output from the DC-DC converter 25 by the controller 30 and the operation signal of the timing controller 30 to generate a scan pulse. The gate driver 41 sequentially supplies pulses to the gate lines GL1 to GLn of the liquid crystal panel 40, and receives the corrected video signal Do DATA output from the timing controller 30. And a data driver 43 for converting the corrected video signal into an analog corrected data signal and supplying the corrected data signal to each of the data lines DL1 to DLm of the liquid crystal panel 40. have.

On the other hand, the timing controller 30 checks the power control generating logic unit 32 that receives the driving voltage and outputs an operation signal, and check points for the look-up table data stored in the external storage unit 36. The communication unit 33 further includes a protocol unit 33 that provides the communication protocol I2C when communicating by reading the data by the I2C protocol method.

In addition, two active wires SCL and SDA are connected between the protocol unit 33 and the external storage unit 36 to communicate with each other.

Here, the R, G, and B video signals output from the system are sequentially input to the timing controller 30 for each frame, and the ODC 31 stores the current frame video signal and the previous frame video signal in the form of a look-up table. The corrected video signal (Do DATA) is output higher than that of the current frame video signal.

That is, in the look-up table, values corresponding to the video signal of the previous frame and the video signal of the current frame are arranged on the x-axis and y-axis, and the values corresponding to the corrected video signal (Do DATA) are the x-axis and The timing controller 30 reads the value of the portion where the video signal of the input previous frame and the video signal of the current frame intersect on the look-up table. It outputs a signal (Do DATA).

Accordingly, the pixel electrode receiving the corrected data signal output from the data driver 43 by the corrected video signal Do DATA causes the liquid crystal to overdrive the higher gray voltage.

3 is a waveform diagram illustrating a driving state of a frame when a video is implemented by applying the liquid crystal display of FIG. 2.

As shown in FIG. 3, in the liquid crystal display having the ODC, when the gray voltage applied to the liquid crystal is changed from a low gray voltage to a high gray voltage, the gray voltage of the data signal corresponding to the current frame corresponds to the previous frame. The gradation voltage of the data signal is of course influenced, but the desired gradation voltage is reached relatively quickly, and as a result, the normal gradation voltage is reached as soon as one frame elapses.

However, in a liquid crystal display device equipped with such an ODC circuit, when a video is implemented using gray scale voltages corresponding to 64 or 256 gray scales, gray level voltages corresponding to the highest levels, that is, normally white, are normally white. In the case of the gray level voltage corresponding to the black data is set in the maximum section of the driving voltage for driving the data driver, the overdriven gray level information data for the highest gray level does not substantially exist in the look-up table type data. As a result, the overdriven gray voltage for the highest gray level cannot be applied to the liquid crystal panel.

As such, when overdriving of the highest gray level of 64 gray levels or 256 gray levels is not performed, afterimages of a previous image and a current image overlap each other in a specific image when the video is implemented, and thus the image quality may be degraded.

For example, the above problem can be improved by improving the structure of the data drive IC constituting the data driver, but in this case, it is designed to increase the driving voltage of the data drive IC, thereby increasing power consumption of the LCD. It may be.

In addition, the above problem can be solved by increasing the number of bits of the R, G, and B data for setting the gradation voltage, but this may require a program reset for all the R, G, and B data. Excessive costs can be incurred.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide the highest level of gray level voltage with respect to the remaining level of gray level voltage when overdriving for moving picture using low driving voltage of the data driver IC. The present invention provides a liquid crystal display device comprising a charge pumping circuit part connected to a data line of a liquid crystal panel so as to obtain an effect such as overdriving.

In the liquid crystal display according to the present invention for achieving the above object, when the overdriving is performed, the data set to the gradation voltage other than the highest gradation selects and outputs the value overdriving than the normal value and is set to the highest gradation. A timing controller which selects and outputs a normal value as it is, and separately controls the highest gray level data and the remaining gray level data; A data driver which stores data from the timing controller and selects and outputs a corresponding gray voltage according to the data information; A gate driver for outputting a gate low voltage Vgl and a gate high voltage Vgh according to a control signal from the timing controller; A charge pumping circuit unit which pumps up the highest gray level voltage output from the data driver and outputs the remaining gray level voltages in an overdriven state when the timing controller performs overdriving; And a liquid crystal panel in which an image is realized by a gray voltage provided from the charge pumping circuit unit.

As a result of the above configuration, the liquid crystal display according to the present invention can output the pumped-up gray level voltage having the same effect as the overdriven gray level voltage with respect to the gray level voltage corresponding to the highest level even within the low driving voltage range of the data drive IC. It will be possible to solve the problem of deterioration of image quality caused by afterimages appearing in a plurality of consecutive frames in the video implementation.

Hereinafter, the configuration will be described in more detail with reference to the accompanying drawings.

4 is a block diagram showing a driving circuit unit of the liquid crystal display according to the present invention.

As shown in FIG. 4, the liquid crystal display according to the present invention receives R, G, and B data from an external interface 10, rearranges data for setting a gray voltage, and receives a vertical / horizontal synchronization signal. Generates a control signal, and when overdriving, selects and outputs the data set as the gradation voltage other than the highest gradation value over the normal value, and selects and outputs the normal value as it is. The timing controller 130 stores the highest gradation data and the remaining gradation data separately, and stores the correction data (Do DATA) from the timing controller 130 and stores corresponding gradation voltages according to the data information. Selects and outputs a data driver 120 and a gate low voltage V according to a control signal from the timing controller 130. gl) and the gate driver 110 outputting the gate high voltage Vgh, and the gray level voltage of the highest level output from the data driver 120 when the timing controller 130 is overdried is pumped up. And the remaining gray level voltage is composed of the charge pumping circuit unit 300 outputting the overdriven state and the liquid crystal panel 100 in which an image is realized by the gray level voltage provided from the charge pumping circuit unit 300. .

In addition, the liquid crystal display according to the present invention includes a power supply voltage generator 200 for generating a driving voltage, a backlight 220 for providing light to the liquid crystal panel 100, and a drive for driving the backlight 220. The lamp driver 210 generates a driving voltage and drives the backlight 220 according to a control signal from the timing controller 130, and receives a power supply voltage Vdd from the power supply voltage generator 200. And a reference voltage generation unit 230 for generating (Vref) and providing it to the data driver 120.

First, the liquid crystal panel 100 includes a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm + 1 that are insulated from and cross each other on the gate lines GL1 to GLn. The liquid crystal cells are arranged in a matrix form for each unit pixel defined by crossing the lines GL1 to GLn and the data lines DL1 to DLm + 1. Each liquid crystal cell includes thin film transistors 101 connected to n gate lines GL1 to GLn and m lines DL1 to DLm.

In addition, the backlight 220 includes a plurality of lamps, such as a Cold Cathode Fluorescent Lamp (CCFL) or an External Electrode Fluorescent Lamp (EEFL), which are turned on by an AC high voltage. It is provided to the liquid crystal panel 100 located.

The lamp driver 210 receives a DC voltage of about 24 V from the power supply voltage generator 200, converts the DC voltage into a DC AC waveform, and converts the AC waveform into an AC AC voltage having a high voltage and applies it to the backlight 220.

The power supply voltage generator 200 receives an AC voltage from the outside and generates a DC voltage of about 12V, and a DC-DC converter generating various types of DC voltages using the DC voltage. DC convertor). In this case, the DC-DC converter is formed by being integrated in a pulse width modulation integrated circuit (PWM IC), and the common voltage (Vcom), the power supply voltage (Vdd), and the overdriving voltage are combined with a peripheral circuit surrounding the PWM IC. Vodc and gate on / off voltages Vgl and Vgh are generated.

The reference voltage generator 230 divides the power supply voltage Vdd provided from the power supply voltage generator 200 to generate a gamma reference voltage Vref corresponding to various levels, and the gamma reference voltage Vref. To the gamma gradation voltage circuit (not shown) of the data driver 120. In this case, a plurality of gamma reference voltages Vref having various levels are generated through a plurality of resistors connected in series.

The timing controller 130 receives the vertical / horizontal synchronization signals Vsync and Hsync from the interface 10 that is coupled to an external system (or device) to control the gate driver 110 and the data driver ( And a control signal generation unit for generating a data control signal of 120, and a data rearranging unit for rearranging R, G, and B data from the interface 10 and supplying the data control signal to the data driver 120 again. At this time, the rearranged R, G, and B data are set according to the grayscale information of the R, G, and B data so that the corresponding gray voltage can be selected through the logic voltage Vlog generated and output from the power supply voltage generation unit 200. .

In addition, the timing controller 130 compares the current frame data and the previous frame data with a look-up table type data read and stored from a data storage device such as an EEPROM when performing overdriving. It includes an ODC unit 130a for outputting the corrected R, G, B data (Do DATA) to output a high gray voltage. Therefore, the timing controller 130 selects and outputs the data set to the gradation voltage other than the highest gradation value through the ODC unit 130a to overdrive the value than the normal value, and the data set to the highest gradation selects the normal value as it is. Will print.

As a result, the timing controller 130 controls the highest gray level data and the remaining gray level data respectively through the ODC unit 130a when performing overdriving, for example, corrected R, G, 64 or 256 gray levels. When the R, G, and B data corresponding to the highest gradation voltages are output from the B data, the charge pumping circuit unit 300 is operated to pump up the highest gradation voltages, or to correct other than the highest gradations. When the R, G, and B data (Do DATA) is outputted, the charge pumping circuit unit 300 may be additionally operated, and the control signal generation unit (not shown) may be additionally output as it is.

The timing controller 130 is a gate control signal (GSC), a gate output enable (GOE), a gate start pulse (Gate Start Pulse) as a gate control signal for controlling the gate driver 110. : GSP), etc., GSC is a signal for determining the time when the gate of the thin film transistor is turned on (On / Off), GOE is a signal for controlling the output of the gate driver 110, GSP is a single This signal indicates the first driving line of the screen among the vertical synchronization signals.

In addition, the timing controller 130 is a data control signal for controlling the data driver 120 as a source sampling clock (SSC), a source output enable (SOE), and a source start pulse (Source Start Pulse: SSP), polarity reverse (POL), data polarity selection (REV), odd / even pixel data (Odd / Even Data) signals, and the like.

Here, the SSC is used as a sampling clock for latching data in the data driver 120, and determines a driving frequency of the data driver IC substantially configuring the data driver 120. The SOE causes the data latched by the SSC to be transferred to the liquid crystal panel 100. The SSP is a signal indicating the start of latching or sampling of data during one horizontal synchronization period. POL is a signal indicating polarity to drive the liquid crystal positively and negatively for inversion driving of the liquid crystal. REV is a signal for selecting the polarity of the data to be transmitted, and odd / even pixel data are signals representing odd data of odd pixels and even data of even pixels.

The gate driver 110 receives the gate low voltage Vgl and the gate high voltage Vgh generated by the power supply voltage generator 200 and applies them to the gate lines GL1 to GLn according to the control signal of the timing controller 130. The gate voltages Vgl and Vgh are sequentially supplied to drive the thin film transistors 101 connected to the corresponding gate lines GL1 to GLn.

The data driver 120 converts the input R, G, B data, or the corrected R, G, B data (Do DATA) at the time of overdriving to a pixel voltage as an analog signal to each gate line GL1 to GLn. The pixel voltage for one horizontal line is supplied to the data lines DL1 to DLm + 1 during the one horizontal period in which the gate voltage is supplied to the gate voltage. At this time, the data driver 120 converts R, G, B data or corrected R, G, B data (Do DATA) into pixel voltage using a gamma voltage supplied from a gamma voltage gray scale circuit (not shown). Each horizontal line is supplied with a pixel voltage in a horizontal 1-dot inversion method, and a line inversion and frame inversion are given to the entire screen to realize an image in a horizontal 1-dot and vertical 1-dot method.

More specifically, in view of corrected R, G, and B data (Do DATA) when performing overdriving to implement a video, the data driver 120 receives corrected data (Do DATA) from the timing controller 130. The data register, the shift register for generating the sampling clock, the first and second latches connected between the shift registers and the data lines DL1 to DLm, and the gamma reference voltages Vref. A gamma gradation voltage circuit for supplying an analog to analog converter (DAC), which includes a digital / analog converter and an output unit.

Here, the data register temporarily stores the corrected data Do DATA from the ODC unit 130a and supplies the stored correction data Do DATA to the first latch.

The shift register shifts the source start pulse SSP from the timing controller 130 according to the source sampling clock SSC to generate a sampling signal. In addition, the shift register shifts the source start pulse SSP to transfer the carry signal CAR to the next shift register.

The first latch samples the corrected digital video data Do DATA from the data register in response to a sampling signal sequentially input from the shift register, and latches the corrected digital video data Do DATA by one line.

The second latch latches the corrected digital data Do DATA input from the first latch, and then simultaneously outputs the latched digital video data Do DATA in response to the SOE signal from the timing controller 130. To help.

The gamma gradation voltage circuit divides various levels of the gamma reference voltages Vref generated and sent by the reference voltage generator 230 to generate gamma gradation voltages corresponding to 64 or 256 gradations.

The DAC causes the gradation voltage of the corresponding level supplied from the gamma gradation voltage circuit to be selected and output in response to the corrected data (Do DATA) from the second latch. Of course, the gradation voltage here is selected and output as either the positive polarity (+) or the negative polarity (−) according to the polarity control signal POL from the timing controller 130.

The output circuit temporarily stores the R, G and B gray voltages of the analog type selected by the DAC in the internal buffer and outputs them to the charge pumping circuit unit 300.

In addition, the charge pumping circuit unit 300 partially sub-charges the pumping circuits CPC1 to CPCm according to a control signal from the timing controller 130 with respect to a voltage corresponding to the highest gray level input when performing overdriving for moving image. And outputs the pumped-up highest gray level voltage, while the voltage corresponding to the remaining gray levels other than the highest gray level is in the state of being overdriven according to the data (DO DATA) corrected by the timing controller 130. The voltage is output to the liquid crystal panel 100. At this time, the rearranged R, G, and B data of the analog type input from the timing controller 130 in the state in which the overdriving is not performed are similarly output to the liquid crystal panel 100 without being pumped up.

Through this process, the thin film transistor 101 on the liquid crystal panel 100 responds to the pixel voltages from the data lines DL1 to DLm + 1 in response to the gate voltages Vgl and Vgh from the gate lines GL1 to GLn. Or gray scale voltage) is supplied to the liquid crystal cell, and the liquid crystal cell controls the transmittance of light provided from the backlight 220 by driving a liquid crystal positioned between the common electrode and the pixel electrode in response to the pixel voltage. An image without an afterimage is realized by the transmittance of light passing through the panel 100.

Of course, the charge pumping circuit unit 300 according to the present invention is preferably formed at the edge region where the data pad unit is located on the liquid crystal panel 100 and is formed at the same time when forming the TFT array substrate. It is also possible to integrate and form at the same time in the drive IC. In addition, the circuit may be configured and attached to a separate substrate, and the present invention is not particularly limited thereto.

FIG. 5 is a circuit diagram of sub-charge pumping circuits CPC1 to CPCm constituting the charge pumping circuit unit of FIG. 4, and FIG. 6 is a waveform diagram illustrating an operating state of FIG. 4.

As shown in FIG. 5, each of the sub-charge pumping circuits CPC1 to CPCm constituting the charge pumping circuit unit 300 of the present invention is formed to be parallel to the gate lines GL1 to GLn on the liquid crystal panel. To fourth and fourth pumping lines PL1 to PL4 and the first to fourth pumping lines PL1 to PL4, respectively, a common voltage line Vcom line, an overdriving voltage line, and the first driving line. To first to third transistors Q1 to Q4 formed at regions where the third and third pumping lines PL1 to PL3 and the common voltage line Vcom line cross each other, and the first, second and fourth pumping lines Fourth to sixth transistors Q4 to Q6 formed at regions where PL1, PL2, and PL4) and the overdriving voltage line Vodc line intersect, respectively, and the first pumping line PL1 and the common voltage line Vcom line. ) Is formed in the region where the source electrode of the first transistor Q1 and the first pumping line PL1 and the overdriving voltage line (Vodc line) intersect each other. 4 is configured by including a capacitor (C) connected between the source electrode of the transistor (Q4).

At this time, the source electrode of the fifth transistor Q5 formed in the cross region of the second pumping line PL2 and the overdriving voltage line Vodc for each of the sub-charge pumping circuits CPC1 to CPCm is an output of the data driver. Data is input through a data voltage input line (Vdata-in line) connected to each other, and a source of the third transistor (Q3) formed at the intersection of the third pumping line (PL3) and the common voltage line (Vcom line). The electrodes are commonly connected to the source electrodes of the sixth transistor Q6 formed at the intersection of the fourth pumping line PL4 and the overdriving voltage line Vodc line, and are respectively connected to the data lines DL1 to DLm of the liquid crystal panel. Data is output through the data voltage output line (Vdata-out line).

In addition, the common voltage Vcom applied to the common electrode of the liquid crystal panel may be applied to the common voltage line Vcom-in line. However, since the common voltage Vcom in the present invention may be substantially lower than the common voltage Vcom applied to the common electrode of the liquid crystal panel, a voltage generated separately through a separate common voltage generator may be applied. Could be

In the initial design of the liquid crystal display, an overdriving voltage line Vodc line may be provided with a voltage from the power supply voltage supply unit according to a control signal from a timing controller including an ODC unit. The size may vary depending on the size of the common voltage Vcom.

In other words, the voltage difference between the common voltage Vcom and the overdriving voltage Vodc in the present invention is other than the highest gray level voltage applied by using the corrected data information in the form of a typical look-up table when overdriving the timing controller. It may be equal to the overdriving width of the remaining gradation voltage of. For example, if the normal 254-level gradation voltage is 16.58V and the 254-level gradation voltage is 16.65V when performing overdriving in the timing controller, the voltage difference between the 254-level gradation voltages during and without overdriving is 0.7V.

Therefore, each capacitor C configured in the sub-charge pumping circuits CPC1 to CPCm is equal to the overdriving width of the remaining gray voltages even when the charge corresponding to 0.7V is charged. When the sub-charge pumping circuits CPC1 to CPCm are operated, the highest gradation voltage applied from the outside and the voltage of the capacitor C are added together, so that the pumped-up charge is generally transferred to the data line of the liquid crystal panel. DL1 ~ DLm).

Hereinafter, the operation state of the circuit diagram shown in FIG. 6 will be described in detail with reference to FIGS. 4 and 5.

Although already mentioned in FIG. 4, the timing controller 130 of the liquid crystal display according to the present invention outputs the currently input frame data as it is and does not perform overdriving, and sends it to the data driver 120.

Subsequently, the data driver 120 selects a corresponding gray voltage according to the stored R, G, and B data information, and outputs it in synchronization with the SOE signal from the timing controller 130.

At this time, in synchronization with the SOE signal, the sixth transistor Q6 of the sub-charge pumping circuits CPC1 to CPCm is turned on so that the gray scale voltage is applied to each data line DL1 of the liquid crystal panel 100. ~ DLm)).

On the other hand, when the timing controller 130 performs overdriving, the current frame data is compared with previous frame data stored in a separate memory, and the overdriven data for the remaining gray level other than the highest gray level according to the comparison result. The compensation value is output from the memory stored in the form of a look-up table, and the normal value which is not overdriven for the highest gray level is output from the memory stored in the form of a look-up table and sent to the data driver 120. .

Subsequently, the data driver 120 does not perform the overdriving for the overdriven grayscale voltage with respect to the grayscale voltage of 0 to 254 levels (or the grayscale voltage of 0 to 62 levels for 64 grayscale levels) of 256 grayscale levels. As in the case of no case, the sixth transistor Q6 of the sub-charge pumping circuits CPC1 to CPCm is turned on in synchronization with the SOE signal and output to the corresponding data lines DL1 to DLm of the liquid crystal panel 100, respectively. do.

On the other hand, the data driver 120 generates the sub-charge pumping circuits CPC1 ˜ to generate the pumped-up gray level voltage for the gray level voltage corresponding to the highest 255 level among the 256 gray levels (or the gray level voltage of the highest 63 level among the 64 gray levels). The first to fifth transistors Q1 to Q5 of the CPCm are controlled and output to the corresponding data lines DL1 to DLm of the liquid crystal panel 100.

In this case, the control of the first to fifth transistors Q1 to Q5 of the sub-charge pumping circuits CPC1 to CPCm is performed by a control signal provided from the timing controller 130. In the case of normally white, a control signal is generated which is synchronized with the output time of the black data of 255 levels (or 63 levels corresponding to the highest level of 64 gray levels) corresponding to 256 gray levels.

For example, a black voltage of 5V corresponding to 256 gray levels is output from the data driver 120, and the common voltage Vcom and 0.7V of OV are respectively displayed on the common voltage line Vcom line and the overdriving voltage line Vodc line. Assume that an overdriving voltage Vodc is applied. At this time, the timing controller 130 turns on the first transistor Q1 and the fourth transistor Q4 of the sub-charge pumping circuits CPC1 to CPCm as shown in FIG. 6 at the same time as the output time of the 5V black voltage. The capacitor C is charged with a charge corresponding to 0.7V. Thereafter, the first transistor Q1 and the fourth transistor Q4 are turned off, and the second transistor Q2 and the fifth transistor Q5 of the sub-charge pumping circuits CPC1 to CPCm are turned on. When turned on, the 5 V gray voltage of the 255 level corresponding to the highest gray level is combined with the 0.7 V charged in the capacitor C to output the gray voltage pumped up to 5.7 V. The 5.7V pumped-up gray level voltage of the highest level is output to the corresponding data lines DL1 to DLm of the liquid crystal panel 100 when the third transistor Q3 is turned on.

As described above, even when the grayscale voltage corresponding to the black data of the highest level is performed during the overdriving from the timing controller 130, the overpump corresponding to the remaining level except the highest gray level voltage is performed through the charge pumping circuit unit 300. Since the pumped-up gray level voltage having the same effect as that of the gray level voltage is output to the liquid crystal panel 100, the afterimage occurring in several consecutive frames during video implementation may be removed, thereby improving image quality.

1 is a waveform diagram showing a driving state of a frame when a video is implemented in a general liquid crystal display device;

2 is a block diagram of a liquid crystal display device having an ODC according to the prior art.

3 is a waveform diagram illustrating a driving state of a frame when a video is implemented by applying the liquid crystal display of FIG. 2;

4 is a block diagram showing a driving circuit unit of a liquid crystal display according to the present invention.

5 is a circuit diagram of a sub-charge pumping circuit constituting the charge pumping circuit unit of FIG.

6 is a waveform diagram illustrating an operating state of FIG. 4.

Claims (6)

When performing overdriving, the data set to the gradation voltage other than the highest gradation selects and outputs the value overdriving than the normal value, and the data set to the highest gradation selects and outputs the normal value as it is, and outputs the highest A timing controller for separately controlling the gray level data and the remaining gray level data; A data driver that stores data from the timing controller and selects and outputs a corresponding gray voltage according to the data information; A gate driver configured to output a gate low voltage Vgl and a gate high voltage Vgh according to a control signal from the timing controller; A charge pumping circuit unit which pumps up the highest gray level voltage output from the data driver and outputs the remaining gray level voltages in an overdriven state when the timing controller performs overdriving; And And a liquid crystal panel configured to implement an image by a gray voltage provided from the charge pumping circuit unit. The liquid crystal display of claim 1, wherein the charge pumping circuit part comprises: first to fourth pumping lines PL1 to PL4 formed to be parallel to the gate lines GL1 to GLn on the liquid crystal panel; A common voltage line (Vcom line) and an overdriving voltage line (Vodc line) formed to cross the first to fourth pumping lines PL1 to PL4, respectively; First to third TFTs Q1 to Q4 formed at regions where the first to third pumping lines PL1 to PL3 and the common voltage line VcomL cross each other; Fourth to sixth TFTs Q4 to Q6 respectively formed at regions where the first, second and fourth pumping lines PL1, PL2, and PL4 intersect the overdriving voltage line (Vodc line); The source electrode of the first TFT Q1 formed at the intersection of the first pumping line PL1 and the common voltage line Vcom line, and the first pumping line PL1 and the overdriving voltage line Vodc line A capacitor C connected between the source electrode of the fourth TFT Q4 formed at the crossing region: The data voltage input line Vdata to which data is input by connecting the source electrode of the fifth TFT Q5 formed at the intersection of the second pumping line PL2 and the overdriving voltage line Vodc line to the output of the data driver, respectively. -in line); The source electrode of the third TFT Q3 formed at the intersection of the third pumping line PL3 and the common voltage line Vcom line is disposed at the intersection of the fourth pumping line PL4 and the overdriving voltage line Vodc line. And a data voltage output line (Vdata-out line) to which data is output in common and connected to the source electrodes of the sixth TFT (Q6), respectively, to the data lines (DL1 to DLm) of the liquid crystal panel. A liquid crystal display device. 2. The timing controller of claim 1, wherein the timing controller controls the first to fifth TFTs Q1 to Q5 that pump up the highest gray level voltage applied to the charge pumping circuit unit when performing the overdriving operation, and overdrives the remaining gray levels. The gray voltage may further include a control signal generator for controlling the sixth TFT Q6 to be output as it is to the liquid crystal panel. The liquid crystal display device of claim 1, wherein the charge pumping circuit part may be formed in a dummy area in which the data pad part of the liquid crystal panel is located. The liquid crystal display of claim 1, wherein the charge pumping circuit unit may be integrated and formed in the data drive IC. The liquid crystal display device of claim 1, wherein the charge pumping circuit part may be formed on a separate substrate.

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