KR20090042583A

KR20090042583A - Semiconductor device

Info

Publication number: KR20090042583A
Application number: KR1020070108424A
Authority: KR
Inventors: 배경진
Original assignee: 주식회사 하이닉스반도체
Priority date: 2007-10-26
Filing date: 2007-10-26
Publication date: 2009-04-30

Abstract

The present invention discloses a semiconductor device. The disclosed invention includes a lower conductive pattern, an upper conductive pattern formed to contact the lower conductive pattern, and an upper dummy conductive pattern formed between the upper conductive patterns, and directly contacting the upper dummy conductive pattern to the lower conductive pattern. A contact is formed between the lower conductive pattern and the upper dummy conductive pattern to measure the signal defect of the pattern.

Description

Semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to semiconductor devices for analyzing bias and signal defects inside a chip in a test.

As semiconductor devices are manufactured at high integration speeds, bias and signal variations and fluctuations inside chips are becoming sensitive and important to product characteristics and reliability.

In general, when defects or abnormalities occur in the test after the manufacture of the product during the defect analysis of the bias or the signal inside the chip in the manufacturing process of the semiconductor device, focusing ion or beam deprocessing is performed for analysis purposes. The desired bias or signal was measured by direct contact with the internal metal wiring of.

In addition, failure analysis of bias or signal inside the chip was conducted using a test pattern or a test mode.

However, since the conductive patterns inside the chip are very finely formed, there are considerable difficulties and trial and error in the method of analyzing the bias or the signal defects in the chip by directly contacting the micronized conductive pattern.

1 is a cross-sectional view showing the metal wires formed according to the prior art, with reference to this will be described for the failure analysis of the metal wires.

Referring to FIG. 1, in the structure of a conventional metal wiring in which a lower conductive pattern 121 and an upper conductive pattern 122 are formed, and a contact 141 for connecting the conductive patterns 121 and 122 is formed, the lower conductive In the case of measuring the bias or signal failure of the pattern 121, the contact 180 is directly contacted to the lower conductive pattern 121 to analyze the bias or signal failure.

However, as the lower conductive pattern 121 is formed as a fine pattern due to the gradual integration of devices, it is difficult to directly analyze the defect by directly contacting the lower conductive pattern 121 to the lower conductive pattern 121.

As a result, in the related art, due to the miniaturization of the conductive pattern, there are considerable difficulties and trial and error in measuring the signal defect of the conductive pattern, and this situation has a significant effect on the development period of the product as well as the period of analyzing the signal defect.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of easily and easily measuring a defect analysis of a bias or a signal inside a chip.

The present invention is a lower conductive pattern; An upper conductive pattern formed in contact with the lower conductive pattern; And an upper dummy conductive pattern formed between the upper conductive patterns, and contacting the upper dummy conductive pattern directly between the lower conductive pattern and the upper dummy conductive pattern to measure a signal defect of the lower conductive pattern. Contacts are formed.

Here, the upper dummy conductive pattern includes a pad shape having a size that can be in contact with the lower conductive pattern by the contact.

The pattern including the upper dummy conductive pattern and the upper conductive pattern including the contact includes at least one formed on the upper dummy conductive pattern and the upper conductive pattern.

When the lower conductive pattern is formed of a gate, the upper conductive pattern may include a bit line or a metal wiring.

When the lower conductive pattern is formed of a bit line, the upper conductive pattern includes a metal wiring.

When the lower conductive pattern is formed of the lower metal wiring, the upper conductive pattern includes an upper metal wiring.

The contact may be formed between the lower conductive pattern and the upper conductive pattern.

According to an embodiment of the present invention, a contact is formed between a lower conductive pattern and an upper dummy conductive pattern to connect the lower conductive pattern and the upper dummy conductive pattern, thereby directly contacting the upper dummy conductive pattern to thereby bias and signal the lower conductive pattern. The defect can be measured.

Therefore, the present invention can easily and quickly measure the signal defects of the metal wires to be miniaturized and can shorten the product development period as well as the analysis period.

According to an exemplary embodiment of the present invention, an upper dummy conductive pattern for failure analysis of a pad type is formed between upper conductive patterns, and a contact is formed on the lower conductive pattern to be in contact with the upper dummy conductive pattern.

2 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention.

As shown, a lower conductive pattern 221 is formed, and an upper conductive pattern 222 having a contact 241 is formed on the lower conductive pattern 221. An upper dummy conductive pattern 272 of a failure analysis pad type contacting the lower conductive pattern 221 is formed between the upper conductive patterns 222, and the lower conductive pattern 221 and a failure analysis pad type are formed. The dummy contact 231 is formed between the upper dummy conductive patterns 272.

The upper dummy conductive pattern 272 of the failure analysis pad type may have a large size that may contact the lower conductive pattern 221 with a dummy conductive pattern formed to stably form the upper conductive pattern 222. The dummy pattern 252, which is formed as a pad type and is not formed as a pad conductive dummy conductive pattern 272 for failure analysis, is formed as a normal dummy pattern.

Meanwhile, when the lower conductive pattern 221 is formed of a gate, the upper conductive pattern 222 is formed of a bit line or a metal wiring, and when the lower conductive pattern 221 is formed of a bit line, the upper portion The conductive pattern 222 is formed of a metal wiring, and when the lower conductive pattern 221 is formed of a lower metal wiring, the upper conductive pattern 222 is formed of an upper metal wiring.

As described above, according to the present invention, when the upper dummy conductive pattern 252 for stably forming the upper conductive pattern 222 is formed, a part of the upper dummy conductive pattern 252 is used for defect analysis for defect analysis for measuring a defect of a signal. And forming a dummy contact 231 on the lower conductive pattern 221 to be in contact with the defect analysis dummy conductive pattern 272 and the lower conductive pattern 221. The conductive pattern 272 and the lower conductive 221 pattern are connected to each other.

In the semiconductor device of the present invention having the above structure, when analyzing a signal failure of the lower conductive pattern 221, the signal is not analyzed in the lower conductive pattern 221 by directly contacting the lower conductive pattern 221. The signal failure of the turn of the lower conductive pad 221 may be analyzed by directly contacting the contact conductive 280 to the failure analysis dummy conductive pattern 272.

Therefore, the present invention does not directly contact the lower conductive pattern 221 formed of a fine pattern, but directly contacts 280 to the defective conductive dummy conductive pattern 272 to measure the defect of the signal of the lower conductive pattern 221. As a result, the bias or signal of the desired internal wiring can be measured.

Specifically, in the related art, the bias or signal of the conductive pattern is measured by directly contacting the conductive pattern portion to measure the bias or signal. However, since the bias or signal of the conductive pattern is not easily contacted, it has been difficult. All.

However, in the present invention, a direct contact with a micro-conductive pattern intended to measure a bias or signal failure is performed by directly contacting a wide pad type conductive pattern portion formed in contact with the conductive pattern without measuring a bias or signal failure. The bias or signal failure of the refined conductive pattern was measured.

Meanwhile, as shown in FIG. 3, an upper conductive pattern including at least one upper dummy pattern is formed on the conductive pattern on which the bias or signal defect is to be measured.

Preferably, when the conductive pattern to measure the bias or signal failure is composed of the bit line 321, a lower metal wiring 322 having a lower contact 341 is formed on the bit line 321, A lower dummy metal wire 372 for defect analysis is formed between the lower metal wires 322. The lower dummy contact 331 is formed between the defect analysis lower dummy metal wiring 372 and the bit line 321 so that the lower dummy metal wiring 372 and the bit line 321 contact each other.

An upper metal wiring 323 having an upper contact 342 is formed on the lower metal wiring 322, and an upper dummy metal wiring 373 for failure analysis is formed between the upper metal wirings 323. Is formed. Between the failure analysis upper dummy metal wiring 373 and the failure analysis lower dummy metal wiring 372 between the failure analysis upper dummy metal wiring 373 and the failure analysis lower dummy metal wiring 372. An upper dummy contact 332 is formed in the gap.

As such, when the conductive pattern for measuring bias or signal failure is configured as the bit line 321, the bias or signal failure of the bit line may be measured by directly contacting the lower dummy metal wire 317 for failure analysis. However, by directly contacting the upper dummy metal wiring 373 for the failure analysis, the bias or signal failure of the bit line 321 may be measured.

Here, although the conductive pattern to measure the bias or signal failure has been described as a bit line, the conductive pattern is not limited to the bit line and can be understood as all conductive patterns.

As described above, the present invention does not directly measure the bias or signal defect of the conductive pattern by directly contacting the conductive pattern to measure the bias or signal defect, and directly measures the pad-type conductive pattern connected to the conductive pattern without measuring the bias or signal defect of the conductive pattern. Contact to measure a bias or signal failure of the conductive pattern.

Therefore, the present invention can easily and quickly measure the bias or signal failure of a desired conductive pattern, thereby shortening the product development period.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

1 is a cross-sectional view showing metal wires formed according to the prior art.

2 is a cross-sectional view showing metal wires having a two-layer structure formed according to the present invention.

3 is a cross-sectional view showing metal wires having a three-layer structure formed according to the present invention.

Explanation of symbols on the main parts of the drawings

221: lower conductive pattern 222: upper conductive pattern

231: dummy contact 241: contact

252: upper dummy conductive pattern

272: pad conductive dummy conductive pattern for failure analysis

321: bit line 322: lower metal wiring

323: upper metallization 331: lower dummy contact

332: top dummy contact 341: bottom contact

342: upper contact 353: lower dummy metal wiring

353: upper dummy metallization

373: bottom dummy metal wiring of the pad for defect analysis

373: top dummy metallization of the pad for defect analysis

Claims

Lower conductive patterns;

An upper conductive pattern formed in contact with the lower conductive pattern;

And an upper dummy conductive pattern formed between the upper conductive patterns.

And a contact is formed between the lower conductive pattern and the upper dummy conductive pattern to directly contact the upper dummy conductive pattern to measure a signal defect of the lower conductive pattern.

The method of claim 1,

The upper dummy conductive pattern is formed in a pad shape having a size that can be in contact with the lower conductive pattern by the contact.

The method of claim 1,

And at least one pattern formed of an upper dummy conductive pattern and an upper conductive pattern including the contact on the upper dummy conductive pattern and the upper conductive pattern.

The method of claim 1,

And when the lower conductive pattern is formed of a gate, the upper conductive pattern is formed of a bit line or a metal wiring.

The method of claim 1,

And when the lower conductive pattern is formed of a bit line, the upper conductive pattern is formed of a metal wiring.

The method of claim 1,

And when the lower conductive pattern is formed of a lower metal wiring, the upper conductive pattern is formed of an upper metal wiring.

The method of claim 1,

And a contact is formed between the lower conductive pattern and the upper conductive pattern.