CN111092024A - Manufacturing method for detecting electric leakage structure between flash memory bit lines and electric leakage detection method - Google Patents
Manufacturing method for detecting electric leakage structure between flash memory bit lines and electric leakage detection method Download PDFInfo
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- CN111092024A CN111092024A CN201911360934.5A CN201911360934A CN111092024A CN 111092024 A CN111092024 A CN 111092024A CN 201911360934 A CN201911360934 A CN 201911360934A CN 111092024 A CN111092024 A CN 111092024A
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- H01—ELECTRIC ELEMENTS
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
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- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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Abstract
The invention provides a manufacturing method for detecting a leakage structure between flash memory bit lines, which comprises the following steps: providing a substrate; forming a shallow trench isolation structure and an active region on the substrate, forming a tunneling oxide layer above the active region, forming a floating gate above the tunneling oxide layer, and forming an inter-gate dielectric layer and a control gate on the floating gate; removing the control gate, the inter-gate dielectric layer and the tunneling oxide layer through control gate etching, leaking out the active region, and forming a bit line in the active region; forming a connecting layer of an active region and a first layer of metal above the active region and a first layer of metal on the connecting layer of the active region and the first layer of metal; and forming a connecting layer of the first layer of metal and the second layer of metal on the first layer of metal, and forming a second layer of metal on the connecting layer of the first layer of metal and the second layer of metal. The bit lines of the flash memory structure are respectively led out through the second layer of metal, so that whether electric leakage exists between the adjacent bit lines of the flash memory can be tested.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method and a leakage detection method for a structure for detecting leakage between bit lines of a flash memory.
Background
With the smaller and smaller chip size, the process for making the corresponding small-sized device is more and more complex, the manufacturing cost is higher and higher, and meanwhile, the method for detecting the process of the small-sized device is more and more difficult. As shown in fig. 1, when the process node is reduced to below 32nm, the conventional photolithography process cannot meet the requirement of fine-scale fabrication, and therefore, a self-aligned dual-pattern (SADP) technique is used. The process is complex and the cost is high. Basically, in the fabrication of a flash memory device with a node of 32nm or less, a self-aligned dual pattern etching process is used for an active region (active region) and a control gate 150(CG), and an SADP process is also used for a leading-out section of the active region 110 of the flash memory cell, i.e., a back-end layer of a bit line (bit line). Due to the instability of the process, the flash memory unit has small space between the bit line and is easy to conduct, thereby causing the circuit failure. In order to represent the problem of electric leakage between bit lines, according to the structure shown in fig. 1, all odd bit lines are short-circuited, all even bit lines are short-circuited, and electric leakage at two ends is tested. The active region 110 of the flash memory cell, the connection layer 120 of the active region and the first metal layer, the first metal layer 130, the connection layer 140 of the first metal layer and the second metal layer, if any one or more of these layers are conductive, will cause conduction between the bit line and the bit line, for example: the first bit line BL0 and the second bit line BL1 are conductive, or the third bit line BL2 and the fourth bit line BL3 are conductive, or the fifth bit line BL4 and the sixth bit line BL5 are conductive, or the seventh bit line BL6 and the eighth bit line BL7 are conductive. This method cannot fully detect which process is problematic. As can be seen from the layout structure diagram of fig. 1, the distance between the active region 110 and the active region 110, the distance between the active region and the first metal layer and the active region 110, and the distance between the second metal layer and the second metal layer are the smallest in the whole flash memory cell, the process is the most difficult to control, and the conduction is the easiest.
Disclosure of Invention
The invention aims to provide a manufacturing method for detecting a leakage structure between flash bit lines and a leakage detection method, which can test whether leakage exists between adjacent bit lines.
In order to achieve the above object, the present invention provides a method for manufacturing a structure for detecting leakage between bit lines of a flash memory, comprising:
providing a substrate;
forming a shallow trench isolation structure and an active region on the substrate, forming a tunneling oxide layer above the active region, forming a floating gate above the tunneling oxide layer, and forming an inter-gate dielectric layer and a control gate on the floating gate;
removing the control gate, the inter-gate dielectric layer and the tunneling oxide layer through control gate etching, leaking out the active region, and forming a bit line in the active region;
forming a connecting layer of an active region and a first layer of metal above the active region and a first layer of metal on the connecting layer of the active region and the first layer of metal;
and forming a connecting layer of a first layer of metal and a second layer of metal on the first metal layer, and forming a second layer of metal on the connecting layer of the first layer of metal and the second layer of metal.
Optionally, in the manufacturing method of the structure for detecting leakage between bit lines of the flash memory, the substrate includes a silicon substrate.
Optionally, in the manufacturing method for detecting a leakage structure between flash bit lines, a method for forming a tunneling oxide layer includes: an oxide layer is formed.
Optionally, in the manufacturing method for detecting the leakage structure between the flash memory bit lines, a self-aligned dual pattern etching process and a filling process are used to form an active region of the flash memory device.
Optionally, in the method for manufacturing the structure for detecting leakage between the bit lines of the flash memory, the active region has a ring shape.
Optionally, in the manufacturing method of the structure for detecting leakage between bit lines of the flash memory, the active region is in a shape of a long ring.
Optionally, in the manufacturing method of the structure for detecting leakage between the bit lines of the flash memory, the bit lines of the same flash memory are connected into a whole.
Optionally, in the manufacturing method for detecting the leakage structure between the bit lines of the flash memory, a plurality of flash memories are simultaneously manufactured on the substrate, a plurality of active regions exist simultaneously, and a plurality of odd column bit lines and a plurality of even column bit lines exist simultaneously.
The present invention also provides a leakage detection method for a manufacturing method of a structure for detecting leakage between flash memory bit lines, comprising: and respectively leading out the bit lines of the flash memory structure through the second layer of metal, and testing whether electric leakage exists between two adjacent flash memory bit lines.
In the manufacturing method and the leakage detection method for detecting the leakage structure between the bit lines of the flash memories, the first layer of metal corresponding to one of the bit lines, the connecting layer of the first layer of metal and the second layer of metal are led out, and whether the leakage exists between the bit lines of two adjacent flash memories is tested.
Further, the distance between the second layer metal and the second layer metal among the plurality of flash memories is increased, the occurrence of process problems caused by too small distance is reduced, and the process problems caused by too small distance between the active region and the connection layer of the active region and the first layer metal can be more characterized than the prior art.
Drawings
FIG. 1 is a schematic diagram of a prior art flash memory structure;
FIG. 2 is a flow chart of a method of fabricating a structure for detecting leakage between bit lines of a flash memory according to an embodiment of the present invention;
FIGS. 3-6 are schematic diagrams of structures for detecting leakage between bit lines of a flash memory according to embodiments of the present invention;
in the figure: 110-active region, 120-active region and first layer metal connection layer, 130-first layer metal, 140-first layer metal and second layer metal connection layer, 150-control gate, BL 0-first bit line, BL 1-second bit line, BL 2-third bit line, BL 3-fourth bit line, BL 4-fifth bit line, BL 5-sixth bit line, BL 6-seventh bit line, BL 7-eighth bit line, 210-substrate, 230-tunnel oxide layer, 250-active region, 251-first odd column bit line, 252-first even column, 253-second odd column bit line, 254-second even column, 255-third odd column bit line, 256-third even column, 257-fourth odd column, 258-fourth even column, 280-active region and first layer metal connection layer, 290-first layer metal, 300-connection layer of first layer metal and second layer metal, 310-second layer metal.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the following, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
Referring to fig. 2, the present invention provides a method for manufacturing a structure for detecting leakage between bit lines of a flash memory, comprising:
s11: providing a substrate;
s12: forming a shallow trench isolation structure and an active region on the substrate, forming a tunneling oxide layer above the active region, forming a floating gate above the tunneling oxide layer, and forming an inter-gate dielectric layer and a control gate on the floating gate;
s13: removing the control gate, the inter-gate dielectric layer and the tunneling oxide layer through control gate etching, leaking out the active region, and forming a bit line in the active region;
s14: forming a connecting layer of an active region and a first layer of metal above the active region and a first layer of metal on the connecting layer of the active region and the first layer of metal;
s15: and forming a connecting layer of a first layer of metal and a second layer of metal on the first metal layer, and forming a second layer of metal on the connecting layer of the first layer of metal and the second layer of metal.
Referring to fig. 3 and 4, first, a substrate 210 is provided, where the substrate 210 may be a silicon substrate; forming a shallow trench isolation structure 220 on the substrate 210, forming a tunneling oxide layer 230 above the shallow trench isolation structure 220, and forming a floating gate 240 above the tunneling oxide layer 230; specifically, the method for forming the tunnel oxide layer 230 includes: an oxide layer is formed, and the oxide may be silicon dioxide. Then, a polysilicon layer is deposited on tunnel oxide layer 230, and the polysilicon layer is partially etched to expose the surface of tunnel oxide layer 230, thereby forming floating gate 240.
Then, in the substrate 210, a self-aligned dual pattern etching process and a filling process are adopted to form an active area 250 of the flash memory device; as shown in fig. 5, the active region 250 of the present embodiment is in the shape of a ring and is in the shape of a rectangular ring. The two long sides will subsequently become bit lines (drawn from the second metal layer), and if the bit lines are numbered, one is an odd-numbered column bit line and the other is an even-numbered column bit line. Since multiple flash memories are fabricated simultaneously on a wafer, there will be multiple odd column bit lines and multiple even column bit lines simultaneously. As shown in FIG. 5, a first odd column bit line 251, a first even column 252, a second odd column bit line 253, a second even column 254, a third odd column bit line 255, a third even column 256, a fourth odd column bit line 257, and a fourth even column 258.
And forming an inter-gate dielectric layer and a control gate, wherein the inter-gate dielectric layer is positioned between the floating gate and the control gate. Conducting bit lines of odd columns and even columns of the same flash memory; specifically, an oxide layer, which may be silicon dioxide, is deposited on the floating gate and tunnel oxide layer 230, and the surface of tunnel oxide layer 230 is etched to expose the oxide layer to form the inter-gate dielectric layer. And the control inter-gate dielectric layer is formed on the surface of the floating gate and covers the floating gate. And then depositing a polysilicon layer on the surfaces of the control inter-gate dielectric layer and the tunneling oxide layer 230, etching the polysilicon layer to expose the surface of the tunneling oxide layer 230 between the floating gates to form control gates, forming the control gates on the surface of the control inter-gate dielectric layer and covering the control inter-gate dielectric layer. And removing the control gate, the inter-gate dielectric layer and the tunneling oxide layer through control gate etching to leak out the active region. Compared with the prior art, the embodiment of the invention does not need to form a selection gate, so that a conduction blocking layer does not exist, and the bit lines of odd columns and the bit lines of even columns of the same flash memory are directly conducted. That is, as shown in FIG. 5, the odd column bit lines and the even column bit lines are on a conductive ring. For example, a first odd column bit line 251 and a first even column 252 are conductive, a second odd column bit line 253 and a second even column 254 are conductive, a third odd column bit line 255 and a third even column 256 are conductive, and a fourth odd column bit line 257 and a fourth even column 258 are conductive.
Next, forming a connection layer 280 of the flash memory cell active region and the first layer metal, and a first layer metal 290; finally, a connection layer 300 of the first metal layer and the second metal layer of the flash memory cell, and a second metal layer 310 are sequentially formed. In the structure of the invention, if the first layer metal 290, the connecting layer 300 of the first layer metal and the second layer metal 310 corresponding to the odd-numbered columns of bit lines of all the flash memory units are not led out, only the first layer metal 290, the connecting layer 300 of the first layer metal and the second layer metal 310 corresponding to the even-numbered columns of bit lines are left, the electric leakage between the ends is tested, and the influence of the second layer metal 300 can be eliminated. Or, the first layer metal 290 corresponding to the even-numbered bit lines of all the flash memory cells, the connecting layer 300 of the first layer metal and the second layer metal, and the second layer metal 310 are not led out, and only the connecting layer 300 of the first layer metal 290 corresponding to the odd-numbered bit lines, the connecting layer 300 of the first layer metal and the second layer metal, and the second layer metal 310 are left, so that the electric leakage between the ends is tested, and the influence of the second layer metal 310 can be eliminated. The structure of the present invention can particularly well reflect all process problems under the second metal layer 310 of the flash memory cell because all dielectric layers under the second metal layer 310 are substantially the same as those of the conventional structure.
Referring to fig. 6, the distance between the second layer metal 310 and the second layer metal 310 of the plurality of flash memories is increased, the occurrence of process problems due to too small distance between the second layer metal 310 and the second layer metal 310 is reduced, and conduction between the second layer metal 310 and the second layer metal 310 can be eliminated. The method of the invention is simple, can be realized only by modifying the layout of the traditional structure, and can better represent the active regions 250 and 250 among a plurality of flash memories and the process problems caused by too small distance among the active regions 250, the active regions and the first metal connecting layer 280 compared with the traditional test structure.
In summary, in the manufacturing method and the leakage detection method for detecting the leakage between the bit lines of the flash memory according to the embodiments of the present invention, the first layer metal corresponding to one of the bit lines, the connection layer between the first layer metal and the second layer metal, and the second layer metal are extracted, and whether the leakage occurs between two adjacent flash memories is tested.
Further, the distance between the second layer metal and the second layer metal among the plurality of flash memories is increased, the occurrence of process problems caused by too small distance is reduced, and the process problems caused by too small distance between the active region and the connection layer of the active region and the first layer metal can be more characterized than the prior art.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. A manufacturing method for detecting a leakage structure between flash memory bit lines is characterized by comprising the following steps:
providing a substrate;
forming a shallow trench isolation structure and an active region on the substrate, forming a tunneling oxide layer above the active region, forming a floating gate above the tunneling oxide layer, and forming an inter-gate dielectric layer and a control gate on the floating gate;
removing the control gate, the inter-gate dielectric layer and the tunneling oxide layer through control gate etching, leaking out the active region, and forming a bit line in the active region;
forming a connecting layer of an active region and a first layer of metal above the active region and a first layer of metal on the connecting layer of the active region and the first layer of metal;
and forming a connecting layer of a first layer of metal and a second layer of metal on the first metal layer, and forming a second layer of metal on the connecting layer of the first layer of metal and the second layer of metal.
2. The method of claim 1, wherein the substrate comprises a silicon substrate.
3. The method of claim 1, wherein the tunneling oxide layer is formed by a method comprising: an oxide layer is formed.
4. The method of claim 1, wherein the flash memory device active region is formed by a self-aligned dual pattern etching process and a filling process.
5. The method of claim 1, wherein said active region is in the shape of a ring.
6. The method of claim 5, wherein said active region is in the form of a long ring.
7. The method of claim 1, wherein the flash memory bitlines are connected together as a single body.
8. The method of claim 1, wherein a plurality of flash memories are simultaneously formed on the substrate, a plurality of active regions are simultaneously present, and a plurality of odd column bit lines and a plurality of even column bit lines are simultaneously present.
9. A leakage detection method based on the manufacturing method of a structure for detecting leakage between bit lines of a flash memory according to any one of claims 1 to 8, comprising: and respectively leading out the bit lines of the flash memory structure through the second layer of metal, and testing whether electric leakage exists between two adjacent flash memory bit lines.
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| US20030071298A1 (en) * | 2001-10-17 | 2003-04-17 | Matsushita Electric Industrial Co., Ltd. | Non-volatile semiconductor memory device |
| CN1805139A (en) * | 2004-12-07 | 2006-07-19 | 三星电子株式会社 | Structure and method for failure analysis in a semiconductor device |
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