KR20090022804A - Method for manufcturing contact hole in semiconductor device - Google Patents

Method for manufcturing contact hole in semiconductor device Download PDF

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KR20090022804A
KR20090022804A KR1020070088436A KR20070088436A KR20090022804A KR 20090022804 A KR20090022804 A KR 20090022804A KR 1020070088436 A KR1020070088436 A KR 1020070088436A KR 20070088436 A KR20070088436 A KR 20070088436A KR 20090022804 A KR20090022804 A KR 20090022804A
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gas
contact hole
fluorocarbon
carbon
fluorine
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KR1020070088436A
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Korean (ko)
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신희승
신수범
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주식회사 하이닉스반도체
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Publication of KR20090022804A publication Critical patent/KR20090022804A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Abstract

A method of forming the contact hole of the semiconductor device uses the gas containing a FC gas having rate of the different fluorine large carbon as the etching gas and prevent the bowing profile, and the contact not open and top attack generated in the contact hole. The hard mask pattern(23) is formed on the insulating layer(22). The insulating layer is etched to by using the hard mask pattern as the etching barrier wall. At this time, the first CF gas and the second CF gas are mixed in the etching gas. The etching gas can use C4F6 as the main etch gas. The rate of the fluorine to carbon of the first CF gas is smaller than the rate of the fluorine to carbon of the C4F6 gas. The rate of the fluorine to carbon of second CF gas is smaller than the rate of the fluorine to carbon of the first CF gas.

Description

반도체 소자의 콘택홀 형성방법{METHOD FOR MANUFCTURING CONTACT HOLE IN SEMICONDUCTOR DEVICE}Method for forming contact hole in semiconductor device {METHOD FOR MANUFCTURING CONTACT HOLE IN SEMICONDUCTOR DEVICE}

본 발명은 반도체 소자의 제조기술에 관한 것으로, 더욱 상세하게는 반도체 소자의 콘택홀 형성방법에 관한 것이다.The present invention relates to a manufacturing technology of a semiconductor device, and more particularly to a method for forming a contact hole in a semiconductor device.

반도체 소자를 제조할 때에는 패턴에 대응하는 마스크를 제작한 다음, 기판상에 하드마스크패턴을 형성한 후, 하드마스크패턴을 식각장벽(erch barrier) 하부구조를 건식각 또는 습식각하여 패터닝하게 된다. 이어서, 하드마스크패턴을 제거한 후 패터닝된 층을 형성하고, 전술한 과정을 반복하게 된다.When fabricating a semiconductor device, a mask corresponding to a pattern is fabricated, a hard mask pattern is formed on a substrate, and then the hard mask pattern is patterned by dry etching or wet etching an etch barrier substructure. Subsequently, after removing the hard mask pattern, a patterned layer is formed, and the above-described process is repeated.

콘택홀을 형성하는 과정도 콘택홀이 형성될 절연막을 형성하고, 절연막을 선택적으로 식각하여 콘택홀을 형성하게 된다. 콘택홀에는 도전막을 매립시켜 하단에 형성된 도전막과 상단에 형성될 도전막을 전기적으로 연결하는 콘택플러그를 형성하거나, 콘택홀에 도전막, 유전물질 및 도전막을 차례로 증착하여 실린더형(cylinder) 또는 콘케이브형(concave) 구조를 갖는 MIM(Metal-Insulator-Metal) 캐패시터를 형성할 수도 있다.The process of forming the contact hole also forms an insulating film on which the contact hole is to be formed, and selectively forms the contact hole by etching the insulating film. A contact plug is formed in the contact hole to electrically connect the conductive film formed at the bottom and the conductive film to be formed at the bottom, or the conductive film, the dielectric material, and the conductive film are sequentially deposited in the contact hole to form a cylinder or cone. Metal-Insulator-Metal (MIM) capacitors having a caved structure may be formed.

최근에는 기술이 발달하면서 패터닝 폭이 50nm 이하까지 감소함에 따라 콘택홀의 폭이 점점 더 줄어들고, 깊이는 더 깊어지고 있다. 특히, DRMA에서 실린더형 MIM 캐패시터와 같이 큰 종횡비(high aspect ratio)를 갖는 콘택홀을 안정적으로 형성하는 것이 매우 어렵다.In recent years, as technology advances, the patterning width is reduced to 50 nm or less, and the contact hole becomes smaller and deeper. In particular, it is very difficult to stably form a contact hole having a high aspect ratio, such as a cylindrical MIM capacitor in DRMA.

도 1은 종래기술에 따른 콘택홀을 도시한 단면도이고, 도 2는 종래기술에 따른 콘택홀을 나타낸 전자주사현미경(Scanning Electron Microscope, SEM) 이미지이다.1 is a cross-sectional view showing a contact hole according to the prior art, Figure 2 is a scanning electron microscope (Scanning Electron Microscope, SEM) image showing a contact hole according to the prior art.

도 1 및 도 2를 참조하여, 소정의 구조물이 구비된 기판(11)상에 형성된 절연막(12)에 콘택홀(13)이 형성되어 있다. 이때, 도 1의 (a)는 정상적으로 형성된 콘택홀을 도시한 것이다.1 and 2, a contact hole 13 is formed in an insulating film 12 formed on a substrate 11 having a predetermined structure. At this time, Figure 1 (a) shows a contact hole formed normally.

하지만, 종래기술에 따른 콘택홀 형성방법은 콘택홀(13)의 폭이 점점 좁아지고 깊이가 깊어짐에 따라, 도 1의 (b)와 같이 보잉프로파일(bowing profile, X)이 발생하거나, 도 1의 (d)와 같이 콘택낫오픈(contact not open, Z)이 발생하는 문제점이 있다. 또한, 도 1의 (c)와 같이 하드마스크패턴 두께의 한계 및 절연막(12) 식각중 하드마스크패턴의 손실로 인하여 절연막(12) 상부에 탑어택(top attack, Y)이 발생하여 콘택홀(13)의 입구가 비정상적으로 형성되는 문제점이 있다.However, in the method of forming a contact hole according to the related art, as the width of the contact hole 13 becomes narrower and deeper, a bowing profile (X) occurs as shown in FIG. As shown in (d), there is a problem in that contact not open (Z) occurs. In addition, as shown in FIG. 1C, a top attack (Y) occurs on the insulating layer 12 due to the limitation of the hard mask pattern thickness and the loss of the hard mask pattern during the etching of the insulating layer 12. There is a problem that the inlet of 13) is abnormally formed.

상술한 문제점은 콘택플러그를 형성하는데 큰 문제점을 야기할 수 있다. 즉, 콘택홀(13)의 형상이 왜곡되어 형성되면, 후속공정에서 콘택플러그를 형성하더라도 콘택낫오픈(Z)으로 인하여 하단부의 도전막과 전기적으로 잘 접속되기 힘들며, 상 부 탑어택(Y)으로 인하여 이웃한 절연상태를 유지해야 하는 도전패턴까지 단락되는 현상이 발생할 수 있다. The above-described problem may cause a big problem in forming the contact plug. That is, when the shape of the contact hole 13 is distorted, even if the contact plug is formed in a subsequent process, it is difficult to be electrically connected to the lower conductive film at the lower end due to the contact sick open (Z), and the upper top attack (Y) As a result, a short circuit may occur to a conductive pattern that must maintain a neighboring insulation state.

또한, 상술한 문제점은 실린더형 MIM 캐패시터를 형성하는데 있어서, 듀얼비트페일(Dual bit fail), 싱글비트페일(Single bit fail), DC 페일을 증가시켜 반도체 소자의 제조수율을 저하시킬 수 있다.In addition, in the above-described problem, in forming a cylindrical MIM capacitor, dual bit fail, single bit fail, and DC fail may be increased to decrease the yield of semiconductor devices.

본 발명은 상기 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 콘택홀을 안정적으로 형성할 수 있는 반도체 소자의 콘택홀 형성방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the problems of the prior art, and an object thereof is to provide a method for forming a contact hole in a semiconductor device capable of stably forming contact holes.

상기 목적을 달성하기 위한 본 발명의 반도체 소자의 콘택홀 형성방법은 절연막 상에 하드마스크패턴을 형성하는 단계 및 상기 하드마스크패턴을 식각장벽으로 플루오르(F) 대 탄소(C)의 비율(C/F)이 서로 다른 불화탄소가스를 식각가스로 사용하여 상기 절연막을 식각하는 단계를 포함한다. In order to achieve the above object, a method of forming a contact hole in a semiconductor device according to the present invention may include forming a hard mask pattern on an insulating layer and a ratio of fluorine (F) to carbon (C) as an etch barrier using the hard mask pattern (C / F) etching the insulating film by using different carbon fluoride gas as an etching gas.

상기 식각가스는, 메인식각가스로 C4F6를 사용할 수 있고, 상기 C4F6가스보다 플루오르 대 탄소의 비율이 작은 제1불화탄소가스와 플루오르 대 탄소의 비율이 상기 제1불화탄소가스보다 플루오르 대 탄소의 비율이 작은 제2불화탄소가스가 혼합된 가스를 사용할 수 있다. 이때, 상기 제1불화탄소가스의 플루오르 대 탄소의 비율은 0.5 ~ 0.7 범위를 갖고, 상기 제2불화탄소가스의 플루오르 대 탄소의 비율은 0.5 보다 작을 수 있다. 상기 제1불화탄소는 C4F8 또는 C5F8 일 수 있으며, 상기 제2불화탄소는 CF4 또는 C3F8일 수 있다. The etching gas may include C 4 F 6 as a main etching gas, and the first fluorocarbon gas having a smaller fluorine-to-carbon ratio than the C 4 F 6 gas may have a fluorine-to-carbon ratio. Gases containing a mixture of a second fluorocarbon gas having a smaller ratio of fluorine to carbon can be used. In this case, the ratio of fluorine to carbon of the first fluorocarbon gas may be in a range of 0.5 to 0.7, and the ratio of fluorine to carbon of the second fluorocarbon gas may be smaller than 0.5. The first fluorocarbon is C 4 F 8 or C 5 F 8 The second fluorocarbon may be CF 4 or C 3 F 8 .

상기 메인식각가스와 제2불화탄소가스는 동일한 유량을 사용하고, 상기 제1 불화탄소가스의 유량은 상기 메인식각가스 및 제2불화탄소가스의 유량보다 작을 수 있으며, 구체적으로 상기 식각가스의 유량은 상기 메인식각가스는 10sccm ~ 30sccm 범위, 제1불화탄소는 1sccm ~ 20sccm 범위 및 제2불화탄소는 10sccm ~ 30sccm 범위에서 사용할 수 있다. The main etching gas and the second fluorocarbon gas may use the same flow rate, and the flow rate of the first fluorocarbon gas may be smaller than that of the main etching gas and the second fluorocarbon gas, and specifically, the flow rate of the etching gas. The main etching gas can be used in the range of 10sccm ~ 30sccm, the first fluorocarbon 1sccm ~ 20sccm and the second fluorocarbon 10sccm ~ 30sccm range.

또한, 상기 절연막 식각시 아르곤가스 및 산소가스를 더 포함할 수 있다. 이때, 상기 아르곤가스는 200sccm ~ 500sccm 범위의 유량을 사용할 수 있으며, 상기 산소가스는 40sccm ~ 50sccm 범위의 유량을 사용할 수 있다. In addition, the insulating layer may further include argon gas and oxygen gas during etching. In this case, the argon gas may use a flow rate in the range of 200 sccm to 500 sccm, and the oxygen gas may use a flow rate in the range of 40 sccm to 50 sccm.

본 발명은 서로 다른 플루오르 대 탄소의 비율을 갖는 불화탄소가스가 혼합된 가스를 식각가스로 사용함으로써, 콘택홀에서 보잉프로파일, 콘택낫오픈 및 탑어택이 발생하는 것을 방지할 수 있는 반도체 소자의 콘택홀 형성방법을 제공하는 효과가 있다.According to the present invention, by using a gas containing a mixture of fluorocarbon gas having a different fluorine-to-carbon ratio as an etching gas, the contact of a semiconductor device capable of preventing the occurrence of a bowing profile, contact opening and top attack in a contact hole It is effective to provide a hole forming method.

이하 본 발명이 속하는 기술분야에서 통상의 지식을 가진자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

도 3a 내지 도 3b는 본 발명의 실시예에 따른 반도체 소자의 콘택홀 형성방법을 도시한 공정단면도이다.3A through 3B are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to an embodiment of the present invention.

도 3a에 도시된 바와 같이, 트랜지스터, 워드라인 및 비트라인과 같은 소정의 구조물이 형성된 기판(21) 상부에 절연막(22)을 형성한다. 이때, 절연막(22)은 산화막계열, 질화막계열 및 질화산화막(oxynitride) 이루어진 그룹에서 선택된 어느 하나 또는 이들이 적층된 구조로 형성할 수 있다. 예컨대, 산화막계열로는 실리콘산화막(SiO2), BPSG(Boron Phosphorus Silicate Glass), PSG(Phosphorus Silicate Glass), TEOS(Tetra Ethyle Ortho Silicate), USG(Un-doped Silicate Glass), SOG(Spin On Glass), 고밀도플라즈마산화막(High Density Plasma, HDP) 또는 SOD(Spin On Dielectric)을 사용할 수 있으며, 질화막계열로는 Si3N4를 사용할 수 있다.As shown in FIG. 3A, an insulating film 22 is formed on the substrate 21 on which predetermined structures such as transistors, word lines, and bit lines are formed. In this case, the insulating film 22 may be formed of any one selected from the group consisting of an oxide film series, a nitride film series, and an oxynitride, or a stacked structure thereof. For example, the oxide layer may include a silicon oxide film (SiO 2 ), boron phosphorus silicalicate glass (BPSG), phosphorus silicalicate glass (PSG), tetra ethoxy ortho silicate (TEOS), un-doped silicate glass (USG), and spin on glass (SOG). ), High Density Plasma Oxide (HDP) or Spin On Dielectric (SOD) may be used, and Si 3 N 4 may be used as the nitride layer.

다음으로, 절연막(22) 상에 하드마스크패턴(23)을 형성한다. 이때, 하드마스크패턴(23)은 절연막(22)과 식각선택비를 갖는 산화막계열, 질화막계열, 질화산화막 및 탄소함유막으로 이루어진 그룹으로부터 선택된 어느 하나 또는 이들을 조합하여 형성할 수 있다. 예컨대, 탄소함유막으로는 비정질탄소막(Amorphous Carbon Layerm ACL) 또는 카본리치폴리머막(Carbon Rich Polymer)을 사용할 수 있다.Next, the hard mask pattern 23 is formed on the insulating film 22. In this case, the hard mask pattern 23 may be formed by combining the insulating film 22 with any one selected from the group consisting of an oxide film series having an etching selectivity, a nitride film series, a nitride oxide film, and a carbon-containing film. For example, an amorphous carbon film (Amorphous Carbon Layer ACL) or a carbon rich polymer film (Carbon Rich Polymer) may be used as the carbon-containing film.

도 3b에 도시된 바와 같이, 하드마스크패턴(23)을 식각장벽으로 절연막(22)을 식각하여 콘택홀(24)을 형성한다. 이때, 콘택홀(24)은 서로 다른 플루오르 대 탄소의 비율(이하 C/F비)을 갖는 불화탄소가스가 혼합된 가스를 식각가스로 사용하여 형성할 수 있다. As shown in FIG. 3B, the insulating layer 22 is etched using the hard mask pattern 23 as an etch barrier to form the contact hole 24. In this case, the contact hole 24 may be formed by using a mixture of fluorocarbon gas having a different fluorine-to-carbon ratio (hereinafter, C / F ratio) as an etching gas.

여기서, 식각가스는 메인식각가스로 C4F6를 사용할 수 있으며, C/F비가 메인 식각가스의 C/F비보다 작은 제1불화탄소가스와 C/F비가 제1불화탄소가스의 C/F비보다 작은 제2불화탄소가스가 혼합된 가스를 사용할 수 있다. 이때, 제1불화탄소가스의 C/F비는 0.5 ~ 0.7 범위를 가질 수 있으며, 제2불화탄소가스의 C/F비는 0.5 보다 작을 수 있다. 예컨대, 제1불화탄소가스로는 C4F8 또는 C5F8 을 사용할 수 있으며, 제2불화탄소가스로는 CF4 또는 C3F8을 사용할 수 있다.Here, the etching gas may use C 4 F 6 as the main etching gas, and the first fluorocarbon gas having a C / F ratio smaller than the C / F ratio of the main etching gas and the C / F ratio are C / F of the first fluorocarbon gas. A gas in which a second fluorocarbon gas smaller than the F ratio is mixed can be used. In this case, the C / F ratio of the first fluorocarbon gas may have a range of 0.5 to 0.7, and the C / F ratio of the second fluorocarbon gas may be smaller than 0.5. For example, C 4 F 8 or C 5 F 8 may be used as the first fluorocarbon gas, and CF 4 or C 3 F 8 may be used as the second fluorocarbon gas.

이때, 제1불화탄소가스는 C/F비 0.5를 기준으로 할 때, 플루오르에 비하여 탄소의 비율이 높다. 이로 인하여 하드마스크패턴(23)의 표면 및 콘택홀(24) 측벽에 폴리머막을 형성하여 하드마스크패턴(23)의 손실에 따른 콘택홀(24) 상부의 탑어택을 방지하는 역할 및 콘택홀(24)에 보잉프로파일이 형성되는 것을 방지하는 역할을 수행한다. At this time, the first fluorocarbon gas has a higher carbon ratio than the fluorine based on the C / F ratio of 0.5. Accordingly, a polymer film is formed on the surface of the hard mask pattern 23 and the sidewalls of the contact hole 24 to prevent the top attack on the contact hole 24 due to the loss of the hard mask pattern 23 and the contact hole 24. ) To prevent the formation of a bowing profile.

제2불화탄소가스는 C/F비 0.5를 기준으로 할 때, 탄소에 비하여 플루오르의 비율이 높다. 이로 인하여 메인식각가스와 더불어서 절연막(22)의 식각특성을 향상시켜 콘택낫오픈이 발생하는 것을 방지하는 역할을 수행한다.The second fluorocarbon gas has a higher fluorine ratio than carbon based on the C / F ratio of 0.5. As a result, in addition to the main etching gas, the etching characteristic of the insulating layer 22 is improved to prevent contact sick open from occurring.

상술한 서로 다른 C/F비를 갖는 메인식각가스, 제1불화탄소가스 및 제2불화탄소가스의 혼합비율을 적절하게 조절하면 콘택홀(24)의 탑어택, 보잉프로파일 및 콘택낫오픈을 방지할 수 있다. 예컨대, 메인식각가스와 탑어택 및 보잉프로파일 형성을 방지할 수 있는 제1불화탄소가스를 동일한 유량으로 사용하고, 콘택낫오픈을 방지할 수 있는 제2불화탄소가스를 메인식각가스 및 제1불화탄소가스의 유량보다 적게 사용하여 콘택홀(24)의 탑어택, 보잉프로파일 및 콘택낫오픈을 방지할 수 있 다. Properly adjusting the mixing ratio of the main etching gas, the first fluorocarbon gas, and the second fluorocarbon gas having the different C / F ratios described above prevents the top attack, the bowing profile, and the contact opening of the contact hole 24. can do. For example, the main etch gas and the first fluorocarbon gas that can prevent the formation of the top attack and the bowing profile at the same flow rate, and the second fluorocarbon gas that can prevent the contact knock opening, the main etch gas and the first fluoride By using less than the flow rate of carbon gas it is possible to prevent the top attack, boeing profile and contact sick open of the contact hole (24).

구제적으로, 메인식각가스는 10sccm ~ 30sccm 범위, 제1불화탄소는 1sccm ~ 20sccm 범위 및 제2불화탄소는 10sccm ~ 30sccm 범위의 유량을 사용할 수 있다.Specifically, the main etching gas ranges from 10 sccm to 30 sccm, the first fluorocarbons may range from 1 sccm to 20 sccm, and the second fluorocarbons may range from 10 sccm to 30 sccm.

또한, 절연막(22) 식각시 서로 다른 C/F비를 갖는 불화탄소가스가 혼합된 식각가스 이외에 아르곤(Ar)가스 및 산소(O2)가스를 더 사용할 수 있다. 이때, 아르곤가스는 에칭속도를 향상시키는 역할을 수행하며, 산소가스는 절연막(22) 식각시 발생하는 잔류물(residue)을 제거하는 역할을 수행한다. 아르곤가스는 200sccm ~ 500sccm 범위의 유량을 사용할 수 있으며, 산소가스는 40sccm ~ 50sccm 범위의 유량을 사용할 수 있다. In addition, in etching the insulating layer 22, argon (Ar) gas and oxygen (O 2 ) gas may be further used in addition to the etching gas in which carbon fluoride gas having different C / F ratios is mixed. At this time, the argon gas serves to improve the etching rate, the oxygen gas serves to remove the residue (residue) generated during the etching of the insulating film (22). Argon gas may use a flow rate ranging from 200 sccm to 500 sccm, and oxygen gas may use a flow rate ranging from 40 sccm to 50 sccm.

다음으로, 도면에 도시되어 있지는 않지만, 하드마스크패턴(23)을 제거하여 콘택홀(24)을 완성한다. Next, although not shown in the drawing, the contact hole 24 is completed by removing the hard mask pattern 23.

도 4는 본 발명의 실시예에 따라 형성된 반도체 소자의 콘택홀을 나타낸 전자주사현미경 이미지이다. 4 is an electron scanning microscope image showing a contact hole of a semiconductor device formed according to an embodiment of the present invention.

도 4를 참조하면, 종래기술에 따른 반도체 소자의 콘택홀에 비하여 콘택홀의 보잉프로파일이 현저하게 개선된 것을 확인할 수 있다.(도 2참조)Referring to FIG. 4, it can be seen that the bowing profile of the contact hole is remarkably improved compared to the contact hole of the semiconductor device according to the related art. (See FIG. 2).

이와 같이, 본 발명은 서로 다른 C/F비를 갖는 불화탄소가스가 혼합된 가스를 식각가스로 사용하여 콘택홀(24)을 형성함으로써, 콘택홀(24)의 보잉프로파일, 콘택낫오픈 및 탑어택이 발생하는 것을 방지할 수 있다. As described above, the present invention forms the contact hole 24 by using a mixture of fluorocarbon gas having a different C / F ratio as an etching gas, thereby forming a boeing profile, a contact sick open and a top of the contact hole 24. Attack can be prevented from occurring.

이를 통하여 상술한 본 발명의 콘택홀(24) 형성방법을 활용하여 콘택플러그 를 형성할 경우, 콘택낫오픈으로 인하여 상부 도전막과 하단부의 도전막 사이의 전기적인 단락 또는 저항증가를 방지할 수 있으며, 탑어택으로 인하여 이웃한 절연상태를 유지해야 하는 도전패턴까지 단락되는 현상을 방지할 수 있다.When the contact plug is formed by using the above-described method of forming the contact hole 24 of the present invention, electrical shorts or resistance increase between the upper conductive film and the lower conductive film may be prevented due to contact sick open. In addition, it is possible to prevent the short circuit to the conductive pattern to maintain the adjacent insulation state due to the top attack.

또한, 상술한 본 발명의 콘택홀(24) 형성방법을 활용하여 실린더형 MIM 캐패시터를 형성할 경우, 듀얼비트페일(Dual bit fail), 싱글비트페일(Single bit fail) 및 DC 페일로 인하여 반도체 소자의 제조수율이 감소하는 것을 완화시킬 수 있다. In addition, in the case of forming the cylindrical MIM capacitor using the above-described method of forming the contact hole 24 of the present invention, the semiconductor device is due to the dual bit fail, single bit fail, and DC fail. It is possible to alleviate the decrease in the production yield.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기 실시예는 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술분야의 통상의 전문가라면 본 발명의 기술사상의 범위내의 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

도 1은 종래기술에 따른 콘택홀을 도시한 단면도. 1 is a cross-sectional view showing a contact hole according to the prior art.

도 2는 종래기술에 따른 콘택홀을 나타낸 전자주사현미경 이미지.Figure 2 is an electron scanning microscope image showing a contact hole according to the prior art.

도 3a 내지 도 3b는 본 발명의 실시예에 따른 반도체 소자의 콘택홀 형성방법을 도시한 공정단면도.3A through 3B are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to an embodiment of the present invention.

도 4는 본 발명의 실시예에 따라 형성된 반도체 소자의 콘택홀을 나타낸 전자주사현미경 이미지. 4 is an electron scanning microscope image showing a contact hole of a semiconductor device formed in accordance with an embodiment of the present invention.

*도면 주요 부분에 대한 부호 설명** Description of symbols on the main parts of the drawings *

21 : 기판 22 : 절연막21 substrate 22 insulating film

23 : 하드마스크패턴 24 : 콘택홀23: hard mask pattern 24: contact hole

Claims (10)

절연막 상에 하드마스크패턴을 형성하는 단계; 및Forming a hard mask pattern on the insulating film; And 상기 하드마스크패턴을 식각장벽으로 플루오르(F) 대 탄소(C)의 비율(C/F)이 서로 다른 불화탄소가스가 혼합된 가스를 식각가스로 사용하여 상기 절연막을 식각하는 단계Etching the insulating layer using the hard mask pattern as an etching gas using a gas containing fluorine (F) to carbon fluoride gas having different ratios (C / F) as an etching barrier as an etching gas 를 포함하는 반도체 소자의 콘택홀 형성방법.Contact hole forming method of a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 식각가스는,The etching gas, C4F6를 메인식각가스로 사용하고, 상기 C4F6가스 보다 플루오르 대 탄소의 비율이 작은 제1불화탄소가스와 상기 제1불화탄소가스 보다 플루오르 대 탄소의 비율이 작은 제2불화탄소가스가 혼합된 가스를 사용하는 반도체 소자의 콘택홀 형성방법.Using a C 4 F 6 in the main etching gas and the C 4 F 6 gas than fluorine for a small proportion of carbon the first fluorocarbon gas and wherein the small second fluorocarbon ratio of fluorine to carbon than the first fluorocarbon gas A method of forming a contact hole in a semiconductor device using a gas mixed with gas. 제2항에 있어서,The method of claim 2, 상기 제1불화탄소가스의 플루오르 대 탄소의 비율은 0.5 ~ 0.7 범위를 갖고, 상기 제2불화탄소가스의 플루오르 대 탄소의 비율은 0.5 보다 작은 반도체 소자의 콘택홀 형성방법.And the fluorine to carbon ratio of the first fluorocarbon gas ranges from 0.5 to 0.7, and the fluorine to carbon ratio of the second fluorocarbon gas is smaller than 0.5. 제2항에 있어서,The method of claim 2, 상기 제1불화탄소는 C4F8 또는 C5F8인 반도체 소자의 콘택홀 형성방법.The first fluorocarbon is C 4 F 8 or C 5 F 8 The contact hole forming method of a semiconductor device. 제2항에 있어서,The method of claim 2, 상기 제2불화탄소는 CF4 또는 C3F8인 반도체 소자의 콘택홀 형성방법.Wherein the second fluorocarbon is CF 4 or C 3 F 8 . 제2항에 있어서,The method of claim 2, 상기 메인식각가스와 제2불화탄소가스는 동일한 유량을 사용하고, 상기 제1불화탄소가스의 유량은 상기 메인식각가스 및 제2불화탄소가스의 유량보다 작은 반도체 소자의 콘택홀 형성방법.The main etching gas and the second fluorocarbon gas use the same flow rate, and the flow rate of the first fluorocarbon gas is smaller than the flow rate of the main etching gas and the second fluorocarbon gas. 제2항에 있어서,The method of claim 2, 상기 메인식각가스는 10sccm ~ 30sccm 범위, 제1불화탄소는 1sccm ~ 20sccm 범위 및 제2불화탄소는 10sccm ~ 30sccm 범위의 유량을 사용하는 반도체 소자의 콘택홀 형성방법.The main etching gas is in the range of 10sccm ~ 30sccm, the first fluorocarbon 1sccm ~ 20sccm range and the second fluorocarbon contact hole forming method using a flow rate of 10sccm ~ 30sccm range. 제1항에 있어서,The method of claim 1, 상기 절연막 식각시 아르곤가스 및 산소가스를 더 포함하는 반도체 소자의 콘택홀 형성방법.And forming argon gas and oxygen gas when the insulating layer is etched. 제8항에 있어서,The method of claim 8, 상기 아르곤가스는 200sccm ~ 500sccm 범위의 유량을 사용하는 반도체 소자의 콘택홀 형성방법.The argon gas is a contact hole forming method of a semiconductor device using a flow rate of 200sccm ~ 500sccm. 제8항에 있어서,The method of claim 8, 상기 산소가스는 40sccm ~ 50sccm 범위의 유량을 사용하는 반도체 소자의 콘택홀 형성방법.The oxygen gas is a contact hole forming method of a semiconductor device using a flow rate of 40sccm ~ 50sccm.
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CN104217964A (en) * 2013-06-05 2014-12-17 中芯国际集成电路制造(上海)有限公司 Forming method of conductive plug
US9287297B2 (en) 2014-01-10 2016-03-15 Samsung Display Co., Ltd. Thin film transistor array panel and method of manufacturing the panel
US9443879B2 (en) 2013-08-21 2016-09-13 Samsung Display Co., Ltd. Display substrate and method of manufacturing the display substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104217964A (en) * 2013-06-05 2014-12-17 中芯国际集成电路制造(上海)有限公司 Forming method of conductive plug
US9443879B2 (en) 2013-08-21 2016-09-13 Samsung Display Co., Ltd. Display substrate and method of manufacturing the display substrate
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