KR20090005258A - Method of manufacturing a liquid crystal display panel - Google Patents

Abstract

A method of manufacturing a liquid crystal display panel is provided to reduce the electrostatic capacity between data line and light shield layer by forming the light shield layer which has more than three regions having different light transmittance rate. A first conductive layer(120) and a photosensitive film(180) are formed on the substrate(111). By using the mask(190) having three or more domains in which the transmission amount is different, the photosensitive film is patterned. The patterned photosensitive film is etched back, the light layer pattern is formed. A first conductive layer is patterned and the gate line, and the light shield layer in which the open area is formed in the task domain. A plurality of data lines is formed by using the second conductive layer. A contact hole is formed by etching a predetermined region after forming a protective film on the substrate.

Description

Method of manufacturing a liquid crystal display panel

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display (LCD), and more particularly, to a method of manufacturing a liquid crystal display panel capable of reducing signal delay of a data line of a liquid crystal display using a light blocking film.

Liquid crystal display (LCD) is one of the flat panel display devices that are widely used at present, and is composed of a thin film transistor substrate having a pixel electrode, a color filter substrate having a common electrode, and a liquid crystal layer interposed therebetween. An image is displayed in a manner of controlling the amount of light transmitted through the liquid crystal layer by rearranging the liquid crystal molecules of the liquid crystal layer by applying a voltage to the pixel electrode and the common electrode.

A black matrix is formed on the color filter substrate to prevent light leakage caused by portions in which the pixel electrode is not formed. Such a black matrix further needs a margin of several μm, for example, about 3 to 5 μm, in consideration of misalignment when the thin film transistor substrate and the color filter substrate are combined. This, in turn, leads to a decrease in luminance due to a decrease in aperture ratio, which in turn causes a drop in LCD quality. In order to reduce the black matrix and improve the aperture ratio, a structure for forming a light blocking film on a thin film transistor substrate has been proposed. The light blocking film is formed in a direction orthogonal to the gate line when the gate line is formed, and the data line overlaps the light blocking film. However, since the light blocking film and the data line overlap, the light blocking film and the data line form a capacitor together with the gate insulating film formed therebetween. Therefore, the signal transmitted through the data line is delayed by the RC delay, which causes serious problems in current consumption and heat generation of the driving component elements. That is, compared with the structure without using the light blocking film, the current consumption increases by about 40%, and some devices generate heat above 100 ° C.

In order to solve this problem, the portion of the light blocking layer overlapping the data line may be removed, but in this case, a mask and an etching process are added to increase the production cost.

The present invention provides a method of manufacturing a liquid crystal display panel that can reduce the signal delay of the data line by reducing the capacitance of the light blocking film and the data line.

According to the present invention, a photo-etching process using a mask having at least three regions having different transmittances is used to remove a portion overlapping with the data line of the light blocking layer formed at the same time as the gate line, thereby reducing capacitance of the light blocking layer and the data line. Provided is a method of manufacturing a liquid crystal display panel that can reduce signal delay.

A thin film transistor substrate according to an aspect of the present invention includes a plurality of gate lines extending in one direction on the substrate; A plurality of light blocking films formed in a direction perpendicular to the gate line and having open regions formed in predetermined portions; A plurality of data lines overlapping the light blocking layer and insulated from and extending from the light blocking layer; And a pixel electrode formed in an area where the gate line and the data line cross each other.

The light blocking layer is formed to be wider than the width of the data line.

The data line overlaps the open area of the light blocking layer.

And a thin film transistor connected to the gate line, the data line, and the pixel electrode, wherein the thin film transistor comprises: a gate electrode protruding from the gate line; A source electrode partially overlapping the gate electrode and protruding from the data line; And a drain electrode partially overlapping the gate electrode and connected to the pixel electrode.

According to another aspect of the present invention, there is provided a method of manufacturing a liquid crystal display panel, comprising: forming a first conductive layer and a photosensitive film on a substrate, and then patterning the photosensitive film using a mask having at least three regions having different transmittances; Etching back the patterned photoresist to form a photoresist pattern; Patterning the first conductive layer using the photoresist pattern as a mask to form a light blocking film having an open region in one region with a gate line; Forming a plurality of data lines overlapping with the open area of the light blocking layer by using a second conductive layer; Forming a contact hole by etching a predetermined region after forming a passivation layer on the substrate; And forming and patterning a third conductive layer on the substrate to form a pixel electrode in a region where the gate line and the data line cross each other.

The light blocking layer extends perpendicular to the gate line.

The mask comprises a complete transmission area, an intermediate transmission area and a complete blocking area.

The complete blocking region corresponds to a region where the gate line and the light blocking layer are formed, and the intermediate transmission region corresponds to a region where the open region is formed, and the complete transmission region corresponds to the gate line, the light blocking layer, and the open region. It corresponds to an area other than the formed area.

The photoresist pattern is reduced in width by the etch back.

According to still another aspect of the present invention, there is provided a liquid crystal display, including a plurality of gate lines extending in one direction on a first substrate, a plurality of light blocking films formed in a direction perpendicular to the gate lines, and having an open region formed in a predetermined portion thereof; A plurality of data lines overlapping the open area of the light blocking film and insulated from and extending from the light blocking film, a pixel electrode formed in an area where the gate line and the data line intersect, the gate line, data line and pixel electrode A thin film transistor substrate including a thin film transistor connected to the thin film transistor; A color filter substrate including a black matrix formed on the second substrate corresponding to the thin film transistor, a color filter formed corresponding to the pixel region, and a common electrode; And a liquid crystal layer formed between the thin film transistor substrate and the color filter substrate.

According to the present invention, the light blocking film formed at the same time as the gate line and formed under the data line is formed by a photolithography and an etching process using a mask having at least three regions having different transmittances so that the light blocking film is not formed at the portion overlapping with the data line. This reduces the RC delay of the data line by reducing the capacitance between the light blocking layer and the data line, thereby reducing the signal delay through the data line.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

1 is a plan view of a liquid crystal display panel according to an exemplary embodiment of the present invention, FIG. 2 is a cross-sectional view of the liquid crystal display of FIG. 1 taken along a line II ′ of FIG. 1, and FIG. 3 is a line II- of FIG. 1. Sectional drawing cut along the II 'line.

1, 2, and 3, the liquid crystal display panel includes a thin film transistor substrate 100 and a color filter substrate 200 facing each other, and a liquid crystal layer (not shown) disposed therebetween.

The thin film transistor substrate 100 may include a plurality of gate lines 121 formed on the first insulating substrate 111 so as to be spaced apart from each other by one direction, and formed between the gate lines 121 and two gate lines 121. The storage electrode lines 123 formed in parallel with each other and spaced apart from each other by a predetermined distance from the storage electrode lines 123 extend in other directions crossing the gate line 121 and the storage electrode lines 123. The light blocking film 124 having the 125 formed therein, a plurality of data lines 141 formed to overlap with the light blocking film 124 and to extend in another direction to be spaced apart from each other by a predetermined distance, and overlap the light blocking film 124. The pixel electrode 151 formed in the pixel region defined by the 121 and the data line 141, and the thin film transistor T connected to the gate line 121, the data line 141, and the pixel electrode 151 is disposed. Include.

The gate line 121 extends in one direction, for example, a horizontal direction, and a portion of the gate line 121 protrudes upward or downward to form a gate electrode 122.

The storage electrode line 123 may be formed in parallel with the gate line 121 between the gate lines 121, may be formed in the center portion between the gate lines 121, and may be formed to be close to the gate line 121. In some embodiments, the gate line 121 may be formed close to the gate line 121. In addition, the storage electrode line 123 forms a storage capacitor together with the pixel electrode 151 with the gate insulating layer 131 interposed therebetween in a pixel region where the gate line 121 and the data line 141 cross each other.

The light blocking layer 124 is connected to one side of the storage electrode line 123 and is formed in a direction crossing the gate line 121 and the storage electrode line 123, for example, a vertical direction, and is spaced apart from the gate line 121. It is formed. In addition, the light blocking layer 124 is partially overlapped with the data line 141 to have a wider width than the data line 141, and a part of the overlapping portion with the data line 141 is removed to form the open area 125. do. That is, if the data line 141 is formed to have a width of, for example, 4.5 μm, the open area 125 of the light blocking film 124 is formed to have a width of 3 μm, and the open area 125 is formed of the data line 141. It is formed in the center of the overlapping portion. In addition, the light blocking layer 124 may be formed by extending a portion of the other side not connected to the storage electrode line 123 to the opposite side of the gate electrode 122 of the thin film transistor T. This is to further block light leakage generated between the thin film transistor 125 and the light blocking layer 124. The gate line 121 including the gate electrode 122, the storage electrode line 123, and the light blocking layer 124 may be formed at the same time.

The data line 141 extends in a direction crossing the gate line 121, for example, in a vertical direction, and overlaps the open area A of the light blocking layer 124. In addition, a portion of the data line 141 protrudes to form a source electrode 142, and a drain electrode 143 is formed to be spaced apart from the source electrode 142 by a predetermined interval.

In addition, the gate line 121, the sustain electrode line 123, and the light blocking layer 124 may be formed of at least one metal of Al, Nd, Ag, Cr, Ti, Ta, and Mo, or an alloy containing them. Do. In addition, the gate line 121, the storage electrode line 123, and the light blocking layer 124 may be formed of a multilayer of a plurality of metal layers as well as a single layer. That is, it may be formed of a double layer including a metal layer such as Cr, Ti, Ta, Mo, etc. having excellent physicochemical properties and an Al-based or Ag-based metal layer having a low specific resistance. In addition, the data line 141, the source electrode 142, and the drain electrode 143 may also be formed of the above-described metal, or may be formed of multiple layers.

The thin film transistor T causes the pixel signal supplied to the data line 141 to be charged in the pixel electrode 151 in response to the signal supplied to the gate line 121. Accordingly, the thin film transistor T includes a gate electrode 122 connected to the gate line 121, a source electrode 142 connected to the data line 141, and a drain electrode 143 connected to the pixel electrode 151. ), A gate insulating layer 131, an active layer 132, and an ohmic contact layer 133 sequentially formed between the gate electrode 122, the source electrode 142, and the drain electrode 143. In this case, the ohmic contact layer 133 may be formed on the gate insulating layer 131 except for the channel portion.

The passivation layer 161 may be formed over the entirety, and the passivation layer 161 may be formed of an inorganic insulating layer or an organic insulating layer, or may be formed of a double layer of an inorganic insulating layer and an organic insulating layer.

The pixel electrode 151 is formed on the passivation layer 161 and is connected to the drain electrode 143 and the first contact hole 162, with the gate insulating layer 131 interposed therebetween through the second contact hole 163. The pixel electrode 151 and the storage electrode line 123 form a storage capacitor.

In addition, the pixel electrode 151 may have a cutout pattern (not shown) as a domain restricting means for adjusting the arrangement direction of the liquid crystal. The pixel electrode 151 may include protrusions instead of a cutting pattern (not shown) as domain restricting means for alignment of liquid crystal molecules. The cutting pattern (not shown) of the pixel electrode 151 is formed to divide the liquid crystal layer into a plurality of domains together with the cutting pattern (not shown) of the common electrode 251 which will be described later.

The color filter substrate 200 includes a black matrix 221, a color filter 231, an overcoat layer 241, and a common electrode 251 on the second insulating substrate 211.

The black matrix 221 is disposed on the color filter substrate 200 corresponding to the gate line 121, the data line 141, and the thin film transistor T of an area other than the pixel area, for example, the thin film transistor substrate 100. It is formed and prevents light leakage to an area other than the pixel area and optical interference between adjacent pixel areas. In addition, the black matrix 221 is made of a photosensitive organic material to which a black pigment is added. As black pigment, carbon black, titanium oxide, etc. are used. Meanwhile, since the light blocking layer 124 is formed on the thin film transistor substrate 100 so as to overlap the data line 141, the black matrix 221 may not be formed in a portion corresponding to the data line 141.

The color filter 231 is formed by repeating the red, green, and blue filters on the black matrix 221. The color filter 231 serves to impart color to light emitted from the light source and passing through the liquid crystal layer. The color filter 231 is formed of a photosensitive organic material.

The overcoat film 241 is formed on the black matrix 221 not covered by the color filter 231 and the color filter 231. The overcoat film 241 serves to protect the color filter 231 while planarizing the color filter 231 and is formed using an acrylic epoxy material.

The common electrode 251 is formed on the overcoat layer 241. The common electrode 251 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The common electrode 251 directly applies a voltage to the liquid crystal layer together with the pixel electrode 151 of the thin film transistor substrate. A cutout pattern (not shown) may be formed on the common electrode 251. The cutout pattern (not shown) of the common electrode 251 may include a plurality of liquid crystal layers together with a cutout pattern (not shown) of the pixel electrode 151. It divides into domains.

4 to 10 are cross-sectional views of devices sequentially shown to explain a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention, and each drawing (a) is along the line II ′ of FIG. 1. It is process sectional drawing of the state cut | disconnected, and (b) of FIG. 1 is process sectional drawing of the state cut along the II-II 'line | wire of FIG.

Referring to FIGS. 4A and 4B, the first conductive layer 120 is formed on the substrate 111 made of an insulating material such as glass, quartz, ceramic, or plastic. The first conductive layer 120 may be formed of at least one metal of Al, Nd, Ag, Cr, Ti, Ta, and Mo or an alloy containing them, and has a single layer as well as excellent physicochemical properties. It may also be formed of a double layer including a metal layer such as Ta, Mo, and the like or an Al-based or Ag-based metal layer having a low specific resistance. After the photoresist layer 180 is formed on the first conductive layer 120, the photoresist layer 180 is patterned by a photographic and developing process using a predetermined mask 190. Here, the mask 190 includes at least three regions having different transmission amounts, for example, a completely transmissive region A, an intermediate transmissive region B, and a completely blocked region C. The completely transmissive region A is a region which transmits 100% of light, the completely blocking region C is a region which blocks 100% of light, and the intermediate transmissive region B is completely blocked with the fully transmissive region A. It is an area | region which permeate | transmits moderate light of area | region C, for example, it is an area | region which transmits 50% of light. A slit mask or a halftone mask may be used to configure the mask 190 to have at least three regions having different transmission amounts. The slit mask is a mask for controlling the amount of light to be transmitted by adjusting the width and spacing of the slit. The narrower and wider the slit transmits more light, and the wider and narrower the slit to transmit less light. Meanwhile, the completely transmissive region A of the mask 190 corresponds to the region where the first conductive layer 120 is completely etched, and the intermediate transmissive region B is formed by the open region A of the light blocking layer 124. The full blocking region C corresponds to an area in which the first conductive layer 120 is not etched, ie, except for the gate line 121, the gate electrode 122, the storage electrode line 123, and the open region A. FIG. It corresponds to the light blocking film 124. When the photosensitive film 180 is exposed and developed by using the mask 190 configured as described above, the photosensitive film 180 of the part completely exposed by the completely transmissive region A is completely removed, and the intermediate transmissive region B is removed. The photoresist film 180 of the partially exposed portion remains at a predetermined thickness, and the photoresist film 180 of the portion not exposed by the complete blocking region C remains completely. That is, the photosensitive film 180 has a shape having a step according to the exposure amount. In this case, the photoresist layer 180 is patterned larger than the pattern for etching by using the photoresist layer 180 as an etching mask. This is followed by an etch back process for exposing the first conductive layer 120 in the portion exposed and developed by the intermediate transmission region B in a subsequent process, in which the thickness and width of the photoresist layer 180 are reduced. Because. Therefore, it is preferable to form a larger patterning size of the photosensitive film 180 in consideration of the thickness of the portion exposed and developed by the intermediate transmission region B. FIG.

Referring to FIGS. 5A and 5B, the patterned photoresist layer 180 is etched back. In this case, the photosensitive layer 180 is etched back so that the first conductive layer 120 is exposed at the portion exposed and developed by the intermediate transmission region B of the first mask 190. Accordingly, the pattern size of the photoresist layer 180 is reduced.

Referring to FIGS. 6A and 6B, the first conductive layer 120 is etched using the patterned photoresist 180 as a mask. As a result, a plurality of gate lines 121 spaced apart from each other and extending in one direction and a plurality of gate electrodes 122 protruding therefrom are formed. At the same time, the storage electrode line 123 is formed between the gate lines 121 in parallel with the gate line 121, and the light blocking film 124 is perpendicular to the gate line 121 from the storage electrode line 123. Is formed. The light blocking layer 124 is formed to be spaced apart from the gate line 121.

Referring to FIGS. 7A and 7B, the gate insulating film 131, the first semiconductor film, and the second semiconductor film are sequentially formed on the entire upper surface thereof. Here, the gate insulating film 131 may be formed using an inorganic insulating film including a SiO ₂ film or a SiNx film, the first semiconductor film may be formed using a hydrogenated amorphous silicon film, and the second semiconductor film may be a silicide or an N-type impurity. It can be formed using this highly doped amorphous silicon film. The second semiconductor layer and the first semiconductor layer are patterned by a photolithography and an etching process using the second mask. As a result, the active layer 132 and the ohmic contact layer 133 are formed. The active layer 132 and the ohmic contact layer 133 are formed to cover the gate electrode 122.

Referring to FIGS. 8A and 8B, after forming the second conductive layer on the entire structure, the second conductive layer is patterned by a photolithography and an etching process using a third mask. As a result, a plurality of data lines 141 that cross the gate line 121 and overlap the open regions 125 of the light blocking layer 124 and are spaced apart from each other by a predetermined interval are formed. In addition, at the same time, the source electrode 142 and the drain electrode 143 which are partially overlapped and spaced apart from each other by the upper portion of the gate electrode 121 are formed. In this case, the source electrode 142 protrudes from the data line 141, and the active layer 132 exposed by the source electrode 142 and the drain electrode 143 becomes a channel region. Here, it is preferable to use a metal single layer or multiple layers as the second conductive layer, and the second conductive layer may use the same material as the first conductive layer for forming the gate line 121, or may be formed of multiple layers. May be The ohmic contact layer 133 exposed by the continuous etching process is etched.

Referring to FIGS. 9A and 9B, the passivation layer 161 is formed over the entire surface. The protective film 161 may be formed using an organic insulating film, or may be formed by stacking an inorganic insulating film and an organic insulating film. BCB (Benzocyclobutane), acryl resin, etc. are used as an organic insulating film, and a silicon oxide film, a silicon nitride film, etc. are used as an inorganic insulating film. The first contact hole 162 exposing a part of the drain electrode 143 and the second contact hole 163 exposing the upper portion of the storage electrode line 123 are formed by a photolithography and an etching process using a fourth mask. .

Referring to FIGS. 10A and 10B, after forming a third conductive layer on the entire structure, the third conductive layer is patterned by a photolithography and an etching process using a fifth mask to form the pixel electrode 151. Form. The pixel electrode 151 is connected to the drain electrode 143 and the first contact hole 162, and between the storage electrode line 123 and the storage capacitor between the gate insulating layer 131 through the second contact hole 163. To achieve. Here, it is preferable to use a transparent conductive film containing indium tin oxide (ITO) or indium zinc oxide (IZO) as the third conductive layer.

As described above, the data line 141 is formed by forming an open region 125 in a central region of the light blocking layer 124 overlapping the data line 141 by a photolithography and an etching process using a mask having at least three regions having different transmittances. And the capacitance between the light blocking layer 124 and the signal delay of the data line 141 can be reduced.

The present invention can be used in the manufacturing method of the liquid crystal display device, in particular can be used in the process for solving the problems caused by the capacitance due to the overlap of the lower layer and the upper layer.

1 is a plan view of a liquid crystal display including a thin film transistor substrate according to an exemplary embodiment of the present disclosure.

2 is a cross-sectional view taken along the line II ′ of FIG. 1;

3 is a cross-sectional view taken along the line II-II ′ of FIG. 1.

4 to 10 are cross-sectional views sequentially illustrating a method of manufacturing a thin film transistor substrate according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

121: gate line 122: gate electrode

123: sustain electrode line 124: light blocking film

125: open region 131: gate insulating film

132: active layer 133: ohmic contact layer

141: data line 142: source electrode

143: drain electrode 151: pixel electrode

Claims (1)

Forming a first conductive layer and a photosensitive film on a substrate and patterning the photosensitive film by using a mask having at least three regions having different transmittances; Etching back the patterned photoresist to form a photoresist pattern; Patterning the first conductive layer using the photoresist pattern as a mask to form a light blocking film having an open region in one region with a gate line; Forming a plurality of data lines overlapping with the open area of the light blocking layer by using a second conductive layer;  Forming a contact hole by etching a predetermined region after forming a passivation layer on the substrate; And And forming and patterning a third conductive layer on the substrate to form a pixel electrode in a region where the gate line and the data line cross each other.

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