KR20090002796A - One transistor type dram and driving method therefor - Google Patents

One transistor type dram and driving method therefor Download PDF

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Publication number
KR20090002796A
KR20090002796A KR1020070067049A KR20070067049A KR20090002796A KR 20090002796 A KR20090002796 A KR 20090002796A KR 1020070067049 A KR1020070067049 A KR 1020070067049A KR 20070067049 A KR20070067049 A KR 20070067049A KR 20090002796 A KR20090002796 A KR 20090002796A
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voltage
line
data
bit line
source line
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KR1020070067049A
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Korean (ko)
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강희복
안진홍
홍석경
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주식회사 하이닉스반도체
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Publication of KR20090002796A publication Critical patent/KR20090002796A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines

Abstract

One transistor type dram and driving method therefore is provided to improve the storage efficiency of the hole carrier by controlling the bias voltage. In one transistor type dram and driving method therefore, a plurality of the bit line pair(BL0, /BL0,BL1, /BL1,) is arranged in the column direction, and a plurality of cell group(CG1,CG2) is connected between a plurality of bit line pairs. One(CG1) among a plurality of cell groups comprises a floating body transistor(FBT1,FBT2) between the source line(SL0) and the source line(SL1). The other one(CG2) of a plurality of cell groups comprises the floating body transistor(FBT3,FBT4) between the source line and the source line(SL2). Two cell groups share one source line, and two cell groups are connected to the different bit line.

Description

One-transistor DRAM and its driving method {One transistor type DRAM and driving method therefor}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a 1-transistor type DRAM and a driving method thereof, and is a technique for improving data margin while increasing cell array efficiency in a 1-transistor type DRAM using a floating body storage device. .

In general, semiconductor devices such as DRAM are integrated on a silicon wafer. However, silicon wafers used in semiconductor devices are not used for the operation of the device but only a limited thickness of several micrometers from the surface for device operation. As a result, the remaining silicon wafers, except for those required for the operation of the device, increase power consumption and reduce driving speeds.

Accordingly, there is a need for a silicon on insulator (SOI) wafer formed by forming a silicon single crystal layer having a thickness of several μm through an insulating layer on a silicon substrate. The semiconductor device integrated on the SOI wafer can be speeded up by the small junction capacity compared to the semiconductor device integrated on the conventional silicon wafer, and has the advantages of speeding up and voltage reduction due to the low voltage due to the low threshold voltage.

However, when the storage efficiency of the hole carriers stored in the floating body is low in the semiconductor device integrated in the SOI wafer, data read / write cannot be effectively performed and the data operation margin is reduced.

In addition, in the conventional semiconductor device, since the cell array is not efficiently disposed, the size of the entire array is increased, and the phenomenon of cell deterioration occurs due to interference between cells according to the bias voltage.

SUMMARY OF THE INVENTION The present invention was created to solve the above problems, and aims to prevent cell degradation while increasing the cell array efficiency in a 1-transistor DRAM using a floating body storage element. have.

In addition, the present invention improves the storage efficiency of the hole carrier by adjusting the bias voltage in the 1-transistor type DRAM using the floating body storage element to enable efficient data read / write operation and at the same time data operation. The goal is to help improve margins.

In addition, an object of the present invention is to improve the reliability of the cell by applying a non-destructive read out (NDRO) method to the 1-transistor DRAM so that the data of the cell is not destroyed during the read operation.

In addition, an object of the present invention is to implement a 1-transistor type DRAM to significantly reduce the cell size.

A method of driving a 1-transistor type DRAM according to the present invention for achieving the above object is a 1-transistor type DRAM using a floating body storage element connected between a bit line and a source line and controlled by a word line. A method of driving a data, the method comprising: a data holding step of holding data stored in a floating body storage device by applying a first voltage for holding cell data to a word line, and applying a precharge voltage to a source line and a bit line; A data storage step of applying a cell activation voltage to a word line, and applying a second voltage for writing cell data to a source line and a bit line to write first data; And discharging the hole carriers stored in the floating body storage device to the source line and the bit line by applying a first voltage to the word line, and maintaining the second voltage level at the source line and the bit line.

In addition, the present invention provides a method of driving a one-transistor type DRAM using a floating body storage element connected between a bit line and a source line and controlled by a word line, the method for maintaining cell data in a word line. A data holding step of applying one voltage and applying a precharge voltage to the source line and the bit line to hold data stored in the floating body storage device; The cell activation voltage is applied to the word line, the second voltage for writing the cell data is applied to the source line, and the precharge voltage is applied to the bit line, and the first data is generated according to the write current flowing from the bit line to the source line. A data storage step of writing the data; And applying a first voltage to a word line, a second voltage to a source line, and a precharge voltage to a bit line to generate a hole carrier in the floating body storage device. .

In addition, the present invention provides a method of driving a one-transistor type DRAM using a floating body storage element connected between a bit line and a source line and controlled by a word line, the method for maintaining cell data in a word line. A data holding step of applying one voltage and applying a precharge voltage to the source line and the bit line to hold data stored in the floating body storage device; A data storage step of applying a cell activation voltage to a word line, and applying a second voltage for writing cell data to a source line and a bit line to write first data; And a third voltage is applied to the word line, and the source line and the bit line maintain the second voltage level to release the hole carriers stored in the floating body storage device.

In addition, the present invention provides a method of driving a one-transistor type DRAM using a floating body storage element connected between a bit line and a source line and controlled by a word line, the method for maintaining cell data in a word line. A data holding step of applying one voltage and applying a precharge voltage to the source line and the bit line to hold data stored in the floating body storage device; The cell activation voltage is applied to the word line, the second voltage for writing the cell data is applied to the source line, and the precharge voltage is applied to the bit line, and the first data is generated according to the write current flowing from the bit line to the source line. A data storage step of writing the data; And applying a third voltage to a word line, a second voltage to a source line, and a precharge voltage to a bit line to generate a hole carrier in the floating body storage device.

In addition, the present invention provides a method of driving a 1-transistor type DRAM using a floating body storage element connected between a bit line and a source line and controlled by a word line, wherein a ground voltage is applied to the word line. A data holding step of applying a precharge voltage to the source line and the bit line to hold data stored in the floating body storage device; Applying a word line sensing voltage to a word line, a source line sensing voltage to a source line, and applying a precharge voltage to a bit line to read data according to a sensing current flowing from the bit line to the source line; And a ground voltage is applied to the word line, and a precharge voltage is applied to the source line and the bit line to hold the data.

In addition, the 1-transistor DRAM of the present invention is a 1-transistor DRAM using a floating body storage element connected between a bit line and a source line and controlled by a word line, wherein the plurality of DRAMs are arranged in a row direction. Source lines and word lines; A pair of bit lines arranged in the column direction; And a floating body storage device, the plurality of cell groups each arranged between the pair of bit lines, wherein a first group of the plurality of cell groups is connected to a first bit line of the pair of bit lines, and a plurality of cells The second group of groups is connected to the second bit line of the pair of bit lines.

The present invention provides the following effects.

First, the present invention can prevent cell degradation while increasing cell array efficiency in a 1-transistor type DRAM using a floating body storage element.

Second, the present invention improves the storage efficiency of the hole carrier by adjusting the bias voltage in a 1-transistor DRAM using a floating body storage element, thereby enabling efficient data read / write operation and data operation. Help improve margins.

Third, the present invention applies a non-destructive read out (NDRO) method to a 1-transistor type DRAM so that the data of the cell is not destroyed during read operation, thereby improving cell reliability.

Fourth, the present invention implements a 1-transistor type DRAM to significantly reduce the cell size.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1 is a cross-sectional view illustrating a unit cell of a 1-transistor DRAM according to the present invention.

The silicon on insulator (SOI) wafer 10 has a stacked structure of a silicon substrate 1, a buried oxide layer 2, and a silicon layer 3. An isolation layer 11 defining an active region in the silicon layer 3 of the SOI wafer 10 is formed in contact with the buried oxide film 2.

The gate 12 is formed on the active region of the silicon layer 3. In addition, source / drain regions 13a and 13b are formed in the silicon layer 3 on both sides of the gate 12 to contact the buried oxide film 2.

In the DRAM cell implemented in the SOI wafer 10, data is stored by trapping holes and electrons in a floating body 15 corresponding to a channel region under the gate 12. .

For example, as shown in FIG. 2A, the data “1” store state may be understood as a state where there are many holes in the floating body 15. As shown in FIG. 2B, the data “0” storage state may be understood as a state in which the floating body 15 has few holes or a lot of electrons.

3 is a waveform diagram illustrating the characteristics of the cell lead current of the 1-transistor DRAM according to the present invention.

3 shows a cell read when the cell gate voltage is set to 0.2V for the DRAM cell implemented in the SOI wafer 10, and the cell gate voltage is sweeped while the cell source voltage is set to ground GND. A graph showing the current.

That is, when the word line read voltage is applied to the word line WL, the read current flows from the bit line BL toward the source line SL. At this time, if the amount of sensing current flowing is larger than the reference current, data "1" is read, and if it is lower than the reference current, data "0" is read.

As shown, the 1-transistor cell in the read state flows a larger amount of sensing current when in the data "1" storage state than in the data "0" storage state. That is, the read current is largest when the data "1" is stored, and the read current is smallest when the data "0". The reference current REF has a read current value corresponding to an intermediate value between the data "1" storage state and the data "0" storage state.

4A is a circuit diagram illustrating a method of writing data “0” of a 1-transistor DRAM according to the present invention.

In the 1-transistor DRAM of the present invention, the source line SL and the bit line BL are connected to the source 13a and the drain 13b of the floating body transistor FBT, respectively, and the word line WL is connected to the gate 12.

In the present invention, the floating body transistors FBT1 and FBT2 are disposed between the bit line pairs BL and / BL. The drain terminals of the floating body transistors FBT1 and FBT2 are connected to the bit line pairs BL and / BL, respectively, and the common source line SL is shared.

In addition, the unit cell component of the present invention is composed of an NMOS transistor component and a parasitic NPN bipolar transistor component. That is, a parasitic Bipolar Junction Transistor (BJT) is formed between the floating body 15 which is the base end of the parasitic NPN bipolar transistor, the source line SL which is the emitter end, and the bit line BL which is the collector end. .

4B is a timing diagram for describing the operation of FIG. 4A.

In the 1-transistor type DRAM cell of the present invention, the timing for writing data "0" is divided into t0 to t3 sections. Here, the t0 and t3 sections are hold sections that hold data. The t1 section is a Morse and BJT operation section, the t2 section is a parasitic BJT operation section, and the t1, t2 section is a data “0” writing section.

First, in the t0 period, that is, the first hold period, the word line WL maintains a negative voltage NEG1 level. The source line SL and the bit line BL maintain the precharge voltage Vpre level. Accordingly, the data is maintained in the floating body 15 in the t0 section.

Thereafter, in the period t1, the MOS transistor operation is performed by transitioning the voltage of the word line WL to the high level of the cell activation voltage in order to write data to the cell. In addition, the source line SL and the bit line BL transition to the negative voltage NEG2 level.

Accordingly, there is a forward bias between the P-type semiconductor of the floating body 15 of the MOS transistor and the N-type semiconductor of the source line SL. Thus, the parasitic BJT starts to operate.

At this time, the voltage of the bit line BL transitions to the negative voltage NEG2 level similarly to the source line SL. Accordingly, the value of the data "0" write current Iwt0 becomes "0" in the selected cell so that the data "0" write current Iwt0 does not flow from the bit line BL toward the source line SL. Here, the bit line bar / BL maintains the ground voltage GND level as an intermediate voltage. Therefore, the hole charge remaining in the floating body 15 is emitted toward the bit line BL and the source line SL.

Thereafter, in the period t2 for writing the data "0", the word line WL transitions to the negative voltage NEG1 level. Accordingly, the t2 section is a section in which only the parasitic BJT operation is performed. At this time, the source line SL and the bit line BL maintain the negative voltage NEG2 level.

Subsequently, in the period t3, that is, the second hold period, the word line WL maintains the negative voltage NEG1 level, and the source line SL and the bit line BL transition to the precharge voltage Vpre level to enter the data hold mode. .

In the present invention, the negative voltage NEG1 has a level lower than the precharge voltage Vpre. The precharge voltage Vpre has a level higher than the ground voltage GND. In addition, the negative voltage NEG2 level is lower than the ground voltage GND and has a level higher than the negative voltage NEG1. The negative voltage NEG1 level has a lower level than the negative voltage NEG2.

5A is a circuit diagram illustrating a method of writing data “1” of a 1-transistor DRAM according to the present invention.

In the 1-transistor DRAM of the present invention, the source line SL and the bit line BL are connected to the source 13a and the drain 13b of the floating body transistor FBT, respectively, and the word line WL is connected to the gate 12.

In the present invention, the floating body transistors FBT1 and FBT2 are disposed between the bit line pairs BL and / BL. The drain terminals of the floating body transistors FBT1 and FBT2 are connected to the bit line pairs BL and / BL, respectively, and the common source line SL is shared.

FIG. 5B is a timing diagram for describing the operation of FIG. 5A.

In the 1-transistor type DRAM cell of the present invention, the timing for writing data "1" is divided into t0 to t3 sections. Here, the t0 and t3 sections are hold sections that hold data. The t1 section is a Morse and BJT operation section, the t2 section is a parasitic BJT operation section, and the t1, t2 section is a data “1” writing section.

First, in the t0 period, that is, the first hold period, the word line WL maintains a negative voltage NEG1 level. The source line SL and the bit line BL maintain the precharge voltage Vpre level. Accordingly, the data is maintained in the floating body 15 in the t0 section.

Thereafter, in the period t1, the MOS transistor operation is performed by the voltage of the word line WL transitions to a high level in order to write data to the cell. In addition, the source line SL transitions to the negative voltage NEG2 level, and the bit line BL maintains the precharge voltage Vpre level. As a result, the data " 1 " write current Iwt1 flows from the bit line BL toward the source line SL. At this time, the voltage of the bit line bar / BL maintains the ground voltage GND level.

Then, a forward bias is applied between the P-type semiconductor of the floating body 15 of the MOS transistor and the N-type semiconductor of the source line SL. As a result, the parasitic BJT starts operation.

Thereafter, in the period t2 for writing the data "1", the word line WL transitions to the negative voltage NEG1 level. Accordingly, the t2 section is a section in which only the parasitic BJT operation is performed. At this time, the source line SL maintains the negative voltage NEG2 level, and the bit line BL maintains the precharge voltage Vpre level. Accordingly, the potential of the floating body 15 rises to a high value as a large amount of hole carriers are generated.

Subsequently, in the t3 period, that is, the second hold period, the source line SL and the bit line BL transition to the precharge voltage Vpre level to enter the data hold mode.

6A and 6B illustrate another embodiment of a method of writing data “0” of a 1-transistor DRAM according to the present invention.

In the 1-transistor type DRAM cell of the present invention, the timing for writing data "0" is divided into t0 to t3 sections. Here, the t0 and t3 sections are hold sections that hold data. The t1 section is a Morse and BJT operation section, the t2 section is a parasitic BJT operation section, and the t1, t2 section is a data “0” writing section.

First, in the t0 period, that is, the first hold period, the word line WL maintains a negative voltage NEG1 level. The source line SL and the bit line BL maintain the precharge voltage Vpre level. Accordingly, the data is maintained in the floating body 15 in the t0 section.

Thereafter, in the period t1, the MOS transistor operation is performed by the voltage of the word line WL transitions to a high level in order to write data to the cell. In addition, the source line SL and the bit line BL transition to the negative voltage NEG2 level.

Accordingly, there is a forward bias between the P-type semiconductor of the floating body 15 of the MOS transistor and the N-type semiconductor of the source line SL. Therefore, the parasitic BJT starts to operate.

At this time, the voltage of the bit line BL transitions to the negative voltage NEG2 level similarly to the source line SL. Accordingly, the value of the data "0" write current Iwt0 becomes "0" in the selected cell so that the data "0" write current Iwt0 does not flow from the bit line BL toward the source line SL. Here, the bit line bar / BL maintains the ground voltage GND level as an intermediate voltage. Therefore, the hole charge remaining in the large amount of floating body 15 is discharged toward the bit line BL and the source line SL.

Thereafter, in the period t2 for writing the data "0", the word line WL transitions to the negative voltage NEG3 level. Here, the negative voltage NEG3 has a lower level than the negative voltage NEG1. Accordingly, the t2 section is a section in which only the parasitic BJT operation is performed. At this time, the source line SL and the bit line BL maintain the negative voltage NEG2 level.

Subsequently, in the period t3, that is, the second hold period, the word line WL transitions to the negative voltage NEG1 level, and the source line SL and the bit line BL transition to the precharge voltage Vpre level to enter the data hold mode. .

In the present invention, the negative voltage NEG1 has a level lower than the precharge voltage Vpre. The precharge voltage Vpre has a level higher than the ground voltage GND. In addition, the negative voltage NEG2 level is lower than the ground voltage GND and has a level higher than the negative voltage NEG1. The negative voltage NEG1 level has a lower level than the negative voltage NEG2.

7A and 7B illustrate another embodiment of a method of writing data “1” of a 1-transistor DRAM according to the present invention.

In the 1-transistor type DRAM cell of the present invention, the timing for writing data "1" is divided into t0 to t3 sections. Here, the t0 and t3 sections are hold sections that hold data. The t1 section is a Morse and BJT operation section, the t2 section is a parasitic BJT operation section, and the t1, t2 section is a data “1” writing section.

First, in the t0 period, that is, the first hold period, the word line WL maintains a negative voltage NEG1 level. The source line SL and the bit line BL maintain the precharge voltage Vpre level. Accordingly, the data is maintained in the floating body 15 in the t0 section.

Thereafter, in the period t1, the MOS transistor operation is performed by the voltage of the word line WL transitions to a high level in order to write data to the cell. In addition, the source line SL transitions to the negative voltage NEG2 level, and the bit line BL maintains the precharge voltage Vpre level. As a result, the data " 1 " write current Iwt1 flows from the bit line BL toward the source line SL. At this time, the voltage of the bit line bar / BL maintains the ground voltage GND level.

Then, a forward bias is applied between the P-type semiconductor of the floating body 15 of the MOS transistor and the N-type semiconductor of the source line SL. As a result, the parasitic BJT starts operation.

Thereafter, in the period t2 for writing the data "1", the word line WL transitions to the negative voltage NEG3 level. Accordingly, the t2 section is a section in which only the parasitic BJT operation is performed. At this time, the source line SL maintains the negative voltage NEG2 level, and the bit line BL maintains the precharge voltage Vpre level. Accordingly, the potential of the floating body 15 rises to a high value as a large amount of hole carriers are generated.

Then, in the period t3, that is, the second hold period, the word line WL transitions to the negative voltage NEG1 level, the source line SL and the bit line BL transition to the precharge voltage Vpre level, and enters the data hold mode. do.

8A is a circuit diagram illustrating a data read method of a 1-transistor DRAM according to the present invention.

In the 1-transistor DRAM of the present invention, the source line SL and the bit line BL are connected to the source 13a and the drain 13b of the floating body transistor FBT, respectively, and the word line WL is connected to the gate 12.

8B is a timing diagram for describing the operation of FIG. 8A.

In the 1-transistor type DRAM cell of the present invention, the timing for reading data is divided into t0 to t2 sections. Here, the t0 and t2 sections are hold sections that hold data. The t1 section is a section for performing data read.

First, the word line WL maintains the ground GND level in the t0 period, that is, the first hold period. The source line SL and the bit line BL maintain the precharge voltage Vpre level. Accordingly, the data is maintained in the floating body 15 in the t0 section.

Thereafter, in the period t1, the voltage of the word line WL transitions to the word line sensing voltage Vwlsense level to read data stored in the cell. At this time, the source line SL transitions to the source line sensing voltage Vslsense level, and the bit line BL maintains the precharge voltage Vpre level. As a result, a sensing current Isense flows from the bit line BL toward the source line SL.

That is, the cell data is read between the bit line BL and the source line SL by applying the drain source voltage Vds for sensing the sensing current Isense.

Subsequently, in the t2 period, that is, the second hold period, the word line WL transitions to the ground voltage GND level. The source line SL transitions to the precharge voltage Vpre level, and the bit line BL maintains the precharge voltage Vpre level.

In an embodiment of the present invention, the word line sensing voltage Vwlsense has a level higher than the ground voltage GND, and the source line sensing voltage Vslsense preferably has a level lower than the precharge voltage Vpre and higher than the ground voltage GND.

9 is a first embodiment of a cell array of a 1-transistor DRAM according to the present invention.

In the cell array of the present invention, a plurality of source lines SL0 to SL4 and a plurality of word lines WL0 to WL7 are arranged in the row direction. A plurality of bit line pairs BL, / BL are arranged in the column direction.

A plurality of cell groups CG1 and CG2 are connected between the plurality of bit line pairs BL and / BL. Here, the plurality of cell groups CG1 connected to the bit line bar / BL are arranged one by one in the row and column directions, and the plurality of cell groups CG2 connected to the bit line bar / BL are arranged one by one in the row and column directions.

One cell group CG1 includes two unit cells connected between the source line SL0 and the source line SL1, that is, the floating body transistors FBT1 and FBT2. Here, in the floating body transistors FBT1 and FBT2, each gate terminal is connected to the word lines WL0 and WL1, and a common drain terminal is connected to the bit line bar / BL0 to share a bit line contact node.

The other cell group CG2 includes two unit cells connected between the source line SL1 and the source line SL2, that is, the floating body transistors FBT3 and FBT4. Here, in the floating body transistors FBT3 and FBT4, respective gate terminals are connected to the word lines WL2 and WL3 and a common drain terminal is connected to the bit line BL0 to share the bit line BL0 contact node.

In addition, two cell groups CG1 and CG2 disposed up and down share one source line SL1. The plurality of cell groups CG1 arranged in the same row line share one source line SL1.

Of the plurality of cell groups CG1 and CG2 arranged in the same column line, the cell groups CG1 and CG2 arranged up and down adjacent to the source line SL1 are connected to different bit lines BL or bit line bars / BL, respectively. That is, the cell group CG1 disposed above the source line SL1 is connected to the bit line bar / BL0, and the cell group CG2 disposed below the source line SL1 is connected to the bit line BL0.

When a plurality of cells arranged above and below share the same bit line, when a bias voltage is applied to the bit line BL while sharing the source line SL1 in the write operation mode, the floating body transistors FBT2 and FBT3 arranged above and below The same voltage is commonly applied. Accordingly, the same bias voltage is applied to both the selected cell and the unselected cell, thereby causing an operation error in the unselected cell.

Accordingly, the present invention allows the cell groups CG1 and CG2 disposed above and below to be connected to different bit lines BL and / BL, respectively. Therefore, the bias voltage is applied only to the selected cell, and the bias voltage from the bit line is not applied to the unselected cell, thereby preventing an operation error of the cell. That is, when using the parasitic BJT, even if there is a high voltage between the bit line BL and the source line SL, when the intermediate voltage is applied to the bit line bar / BL, it is possible to prevent the high voltage degradation applied to the adjacent cells.

A sense amplifier S / A and a write driver W / D are connected to each bit line BL and a bit line bar / BL. The sense amplifier S / A and the write driver W / D are respectively connected to the bit line BL and the bit line bar / BL in a one-to-one correspondence. Here, the reference voltage ref for determining the sensing voltage is applied to the sense amplifier S / A and the write driver W / D.

The sense amplifier S / A senses cell data to distinguish data "1" from data "0". The write driver W / D supplies a driving voltage corresponding to the write data to the bit line BL when writing data to the cell.

FIG. 10 is a diagram for describing a read mode operation in the first embodiment of FIG. 9.

In the embodiment of FIG. 10, it is assumed that one source line SL1 of the plurality of source lines SL0 to SL4 is selected, and one word line WL2 of the plurality of word lines WL0 to WL7 is selected.

In this case, data stored in the plurality of cells C1 to C4 connected to the selected source line SL1 and the word line WL2 can be simultaneously read. That is, all the bit lines BL and / BL are connected to the independent sense amplifiers S / A and the write driver W / D, respectively. Accordingly, since there is no interference phenomenon in adjacent cells in the read mode, data of all selected cells C1 to C4 can be simultaneously read.

11 and 12 are diagrams for describing a write mode operation in the first embodiment of FIG. 9.

11 and 12, it is assumed that one source line SL1 of the plurality of source lines SL0 to SL4 is selected, and one word line WL2 of the plurality of word lines WL0 to WL7 is selected.

In this case, data cannot be simultaneously written to all the cells connected to the bit line pair BL // BL. Accordingly, as shown in FIG. 11, data is first written to the cells C1 and C3 connected to the bit line BL. At this time, the cells C2 and C4 connected to the bit line bar / BL are not operated. (Idle mode)

As shown in FIG. 12, data is written to the cells C2 and C4 connected to the bit line bar / BL. At this time, the cells C1 and C3 connected to the bit line BL side do not operate. (Idle mode)

Figure 13 is a second embodiment of the cell array of 1-transistor DRAM according to the present invention.

In the embodiment of FIG. 13, a plurality of source lines SL0 to SL4 and a plurality of word lines WL0 to WL7 are arranged in a row direction. Then, a plurality of bit line pairs BL, / BL are arranged in the column direction.

One sense amplifier S / A and a write driver W / D are connected to each bit line pair BL // BL. One bit line pair BL, / BL shares one sense amplifier S / A and the write driver W / D. That is, one sense amplifier S / A and one write driver W / D are disposed every two columns. Here, the reference voltage ref for determining the sensing voltage is applied to the sense amplifier S / A and the write driver W / D.

The sense amplifier S / A senses cell data to distinguish data "1" from data "0". The write driver W / D supplies a driving voltage corresponding to the write data to the bit line BL when writing data to the cell.

14 and 15 are diagrams for describing a read mode operation in the second embodiment of FIG. 13.

In the embodiments of FIGS. 14 and 15, it is assumed that one source line SL1 of the plurality of source lines SL0 to SL4 is selected, and one word line WL2 of the plurality of word lines WL0 to WL7 is selected.

In this case, data stored in the plurality of cells C1 to C4 connected to the selected source line SL1 and the word line WL2 may not be simultaneously read. That is, one bit line pair BL // BL shares one sense amplifier S / A and the write driver W / D.

Accordingly, as shown in FIG. 14, data stored in the cells C1 and C3 connected to the bit line BL is first read. At this time, the cells C2 and C4 connected to the bit line bar / BL are not operated. (Idle mode)

As shown in FIG. 15, data stored in the cells C2 and C4 connected to the bit line bar / BL is read. At this time, the cells C1 and C3 connected to the bit line BL side do not operate. (Idle mode)

16 and 17 are diagrams for describing the write mode operation in the second embodiment of FIG. 13.

In the embodiment of FIGS. 16 and 17, it is assumed that one source line SL1 of the plurality of source lines SL0 to SL4 is selected, and one word line WL2 of the plurality of word lines WL0 to WL7 is selected.

In this case, data cannot be simultaneously written to the plurality of cells C1 to C4 connected to the selected source line SL1 and the word line WL2. That is, one bit line pair BL // BL shares one sense amplifier S / A and the write driver W / D.

Accordingly, as shown in FIG. 16, data is first written to the cells C1 and C3 connected to the bit line BL. At this time, the cells C2 and C4 connected to the bit line bar / BL are not operated. (Idle mode)

As shown in FIG. 17, data is written to the cells C2 and C4 connected to the bit line bar / BL. At this time, the cells C1 and C3 connected to the bit line BL side do not operate. (Idle mode)

1 is a cross-sectional view showing a unit cell of a 1-transistor type DRAM according to the present invention.

2A and 2B show cell data storage states of a 1-transistor DRAM according to the present invention;

Figure 3 is a waveform diagram showing the characteristics of the cell lead current of the 1-transistor DRAM according to the present invention.

4A is a circuit diagram for explaining a method of writing data “0” of a 1-transistor DRAM according to the present invention;

4B is a timing diagram for explaining the operation of FIG. 4A.

FIG. 5A is a circuit diagram for explaining a method of writing data “1” of a 1-transistor DRAM according to the present invention; FIG.

5B is a timing diagram for explaining the operation of FIG. 5A.

FIG. 6A illustrates another embodiment of a method of writing data “0” of a 1-transistor DRAM according to the present invention; FIG.

6B is a timing diagram for explaining the operation of FIG. 6A.

FIG. 7A illustrates another embodiment of a method of writing data “1” of a 1-transistor DRAM according to the present invention. FIG.

FIG. 7B is a timing diagram for explaining the operation of FIG. 7A; FIG.

8A is a circuit diagram illustrating a data reading method of a 1-transistor DRAM according to the present invention.

FIG. 8B is a timing diagram for explaining the operation of FIG. 8A; FIG.

Fig. 9 is a first embodiment of a cell array of 1-transistor DRAM according to the present invention.

FIG. 10 is a view for explaining a read mode operation in the first embodiment of FIG. 9; FIG.

11 and 12 are diagrams for explaining the write mode operation in the first embodiment of FIG.

13 is a second embodiment of the cell array of 1-transistor DRAM according to the present invention;

14 and 15 are diagrams for explaining a read mode operation in the second embodiment of FIG.

16 and 17 are diagrams for explaining the write mode operation in the second embodiment of FIG.

Claims (48)

A method of driving a 1-transistor type DRAM using a floating body storage element connected between a bit line and a source line and controlled by a word line, A data holding step of holding data stored in the floating body storage device by applying a first voltage for holding cell data to the word line, and applying a precharge voltage to the source line and the bit line; A data storage step of applying a cell activation voltage to the word line, and applying a second voltage for writing cell data to the source line and the bit line to write first data; And Applying the first voltage to the word line, and maintaining the second voltage level of the source line and the bit line to emit hole carriers stored in the floating body storage device to the source line and the bit line. A method of driving a 1-transistor type DRAM comprising a. The method of claim 1, wherein the first voltage and the second voltage have a negative voltage level. The method of claim 1, wherein the precharge voltage has a positive voltage level higher than that of the first voltage. The method of claim 1, wherein the second voltage has a level higher than the first voltage. The method of claim 1, wherein the first data is data “0”. The method of claim 1, wherein after the emitting step, the first voltage is applied to the word line, and the precharge voltage is applied to the source line and the bit line to store the first data stored in the floating body storage device. The method of claim 1, further comprising the step of maintaining. A method of driving a 1-transistor type DRAM using a floating body storage element connected between a bit line and a source line and controlled by a word line, A data holding step of holding data stored in the floating body storage device by applying a first voltage for holding cell data to the word line, and applying a precharge voltage to the source line and the bit line; A cell activation voltage is applied to the word line, a second voltage for writing cell data is applied to the source line, and the precharge voltage is applied to the bit line, and the light flowing from the bit line to the source line. A data storing step of writing the first data according to the current; And Generating a hole carrier in the floating body storage device by applying the first voltage to the word line, applying the second voltage to the source line, and applying the precharge voltage to the bit line. A method of driving a 1-transistor type DRAM, characterized in that. 8. The method of claim 7, wherein the first voltage and the second voltage have a negative voltage level. The method of claim 7, wherein the precharge voltage has a higher level than the first voltage. 8. The method of claim 7, wherein the second voltage has a higher level than the first voltage. 8. The method of claim 7, wherein the first data is data " 1. " 8. The method of claim 7, further comprising: maintaining the first data by applying the first voltage to the word line and applying the precharge voltage to the source line and the bit line. -Method of driving transistor type DRAM. A method of driving a 1-transistor type DRAM using a floating body storage element connected between a bit line and a source line and controlled by a word line, A data holding step of holding data stored in the floating body storage device by applying a first voltage for holding cell data to the word line, and applying a precharge voltage to the source line and the bit line; A data storage step of applying a cell activation voltage to the word line, and applying a second voltage for writing cell data to the source line and the bit line to write first data; And And a third voltage is applied to the word line, and the source line and the bit line maintain the second voltage level to release the hole carriers stored in the floating body storage device. Driving method of type DRAM. The method of claim 13, wherein the first voltage, the second voltage, and the third voltage have a negative voltage level. The method of claim 13, wherein the precharge voltage has a level higher than that of the first voltage. The method of claim 13, wherein the second voltage has a level higher than the first voltage. The method of claim 13, wherein the third voltage has a level lower than that of the first voltage. The method of claim 13, wherein the first data is data “0”. The method of claim 13, wherein the first voltage is applied to the word line after the emission step, and the precharge voltage is applied to the source line and the bit line to store the first data stored in the floating body storage device. The method of claim 1, further comprising the step of maintaining. A method of driving a 1-transistor type DRAM using a floating body storage element connected between a bit line and a source line and controlled by a word line, A data holding step of holding data stored in the floating body storage device by applying a first voltage for holding cell data to the word line, and applying a precharge voltage to the source line and the bit line; A cell activation voltage is applied to the word line, a second voltage for writing cell data is applied to the source line, and the precharge voltage is applied to the bit line, and the light flowing from the bit line to the source line. A data storing step of writing the first data according to the current; And A third voltage is applied to the word line, The second voltage is applied to the source line, and the precharge voltage is applied to the bit line, thereby generating a hole carrier in the floating body storage device. A method of driving a 1-transistor type DRAM, characterized in that. 21. The method of claim 20, wherein the first voltage, the second voltage, and the third voltage have a negative voltage level. 21. The method of claim 20, wherein the precharge voltage has a higher level than the first voltage. 21. The method of claim 20, wherein the second voltage has a level higher than the first voltage. 21. The method of claim 20, wherein the third voltage has a lower level than the first voltage. 21. The method of claim 20, wherein the first data is data " 1. " 21. The method of claim 20, further comprising: maintaining the first data by applying the first voltage to the word line and applying the precharge voltage to the source line and the bit line. -Method of driving transistor type DRAM. A method of driving a 1-transistor type DRAM using a floating body storage element connected between a bit line and a source line and controlled by a word line, A data holding step of applying a ground voltage to the word line and a precharge voltage to the source line and the bit line to hold data stored in the floating body storage device; A word line sensing voltage is applied to the word line, a source line sensing voltage is applied to the source line, and the precharge voltage is applied to the bit line, thereby applying data according to a sensing current flowing from the bit line to the source line. Leading; And And applying the ground voltage to the word line, and applying the precharge voltage to the source line and the bit line, to hold the data. 28. The method of claim 27, wherein the word line sensing voltage has a higher level than the ground voltage. 28. The method of claim 27, wherein the source line sensing voltage has a lower level than the precharge voltage. A 1-transistor type DRAM using a floating body storage element connected between a bit line and a source line and controlled by a word line, A plurality of source lines and a plurality of word lines arranged in a row direction; A pair of bit lines arranged in the column direction; And A plurality of cell groups including said floating body storage elements, each of said cell groups arranged between said pair of bitlines; Wherein a first group of the plurality of cell groups is connected to a first bit line of the pair of bit lines, and a second group of the plurality of cell groups is connected to a second bit line of the pair of bit lines -Transistor DRAM. 31. The one-transistor DRAM according to claim 30, wherein the first group is arranged one by one in the row and column direction. 31. The DRAM of claim 30, wherein the second group is disposed one by one in the row and column direction. 31. The DRAM of claim 30, wherein the first group and the second group are alternately arranged in the row and column directions. The method of claim 30, wherein each of the plurality of cell groups A first unit cell connected between a first source line and the first bit line and controlled by a first word line; And And a second unit cell connected between a second source line and the first bit line and controlled by a second word line. 31. The DRAM of claim 30, wherein two cell groups arranged up and down among the plurality of cell groups share a source line. 31. The DRAM of claim 30, wherein cell groups arranged to the left and right of the plurality of cell groups share a source line. 31. The method of claim 30, wherein the cell groups arranged up and down adjacent to the source line among the plurality of cell groups arranged in the same column line are connected to the first bit line and the second bit line, respectively. 1-transistor DRAM. The method of claim 30, A plurality of sense amplifiers connected in a one-to-one correspondence with the first bit line and the second bit line; And And a plurality of write drivers connected in a one-to-one correspondence to the first bit line and the second bit line. 39. The DRAM of claim 38, wherein a reference voltage for determining a sensing voltage is applied to the plurality of sense amplifiers and the plurality of write drivers. 39. The DRAM of claim 38, wherein each of the plurality of cell groups is configured to simultaneously activate a plurality of unit cells connected to a selected source line and a selected word line during a read operation. 39. The 1-transistor type DRAM of claim 38, wherein each of the plurality of cell groups activates only unit cells connected to the first bit line among a plurality of unit cells connected to a selected source line and a selected word line during a write operation. . 39. The 1-transistor DRAM of claim 38, wherein each of the plurality of cell groups activates only unit cells connected to the second bit line among a plurality of unit cells connected to a selected source line and a selected word line during a write operation. . The method of claim 30, A plurality of sense amplifiers connected in one-to-one correspondence with the pair of bit lines; And And a plurality of write drivers connected in a one-to-one correspondence with the pair of bit lines. 44. The DRAM of claim 43, wherein a reference voltage for determining a sensing voltage is applied to the plurality of sense amplifiers and the plurality of write drivers. 45. The 1-transistor DRAM of claim 44, wherein each of the plurality of cell groups activates only unit cells connected to the first bit line among a plurality of unit cells connected to a selected source line and a selected word line during a read operation. . 45. The 1-transistor DRAM of claim 44, wherein each of the plurality of cell groups activates only unit cells connected to the second bit line among a plurality of unit cells connected to a selected source line and a selected word line during a read operation. . The 1-transistor DRAM according to claim 43, wherein each of the plurality of cell groups activates only the unit cells connected to the first bit line among the plurality of unit cells connected to the selected source line and the selected word line during a write operation. . 44. The 1-transistor DRAM of claim 43, wherein each of the plurality of cell groups activates only unit cells connected to the second bit line among a plurality of unit cells connected to a selected source line and a selected word line during a write operation. .
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