KR20090002803A - Method for multi-level driving of one transistor type dram - Google Patents

Abstract

A method for multi-level driving of one transistor type dram is provided to improve of the cell by preventing the break down of cell data. In a method for multi-level driving of one transistor type dram, data is maintained at the floating body for the t0 period. A MOS transistor is operated by shifting the voltage of the word line(WL) to the high level for t1 period. A low voltage(Vpre L) level is maintained at the source line(SL), the bit line(BL) is shifted to the negative voltage(NEG2) level. The word line is shifted to the negative voltage level for t2 period. The low voltage level is maintained at the source line, and the bit line is maintained by the negative voltage level. The hot carrier is emitted to the source line for t3 period and data retention(Hold) mode is performed for t4 period.

Description

Method for multi-level driving of one transistor type DRAM

The present invention relates to a multi-level driving method of a 1-transistor type DRAM. In the 1-transistor type DRAM using a floating body storage element, the amount of hot carriers in the floating body is controlled by adjusting the amount of hot carriers. It is a technology that enables reading / writing of a plurality of data.

In general, semiconductor devices such as DRAM are integrated on a silicon wafer. However, silicon wafers used in semiconductor devices are not used for the operation of the device but only a limited thickness of several micrometers from the surface for device operation. As a result, the remaining silicon wafers, except for those required for the operation of the device, increase power consumption and reduce driving speeds.

Accordingly, there is a need for a silicon on insulator (SOI) wafer formed by forming a silicon single crystal layer having a thickness of several μm through an insulating layer on a silicon substrate. The semiconductor device integrated on the SOI wafer can be speeded up by the small junction capacity compared to the semiconductor device integrated on the conventional silicon wafer, and has the advantages of speeding up and voltage reduction due to the low voltage due to the low threshold voltage.

However, in a semiconductor device integrated in such an SOI wafer, when the emission efficiency of a hot carrier stored in a floating body is low, data cannot be read / written effectively and the device cannot be stably driven. do. In addition, since the conventional 1-transistor type DRAM cell cannot store data at multiple levels, the read / write operation cannot be effectively performed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and in the 1-transistor type DRAM using a floating body storage element, it is possible to effectively read / write data by increasing the hot carrier (Hot Carrier) emission efficiency. The purpose is to enable the device to be driven stably.

In addition, the present invention, in the 1-transistor type DRAM using the floating body storage element to adjust the amount of hot carriers in the floating body to easily read / write a plurality of data Its purpose is to.

In addition, an object of the present invention is to improve the reliability of the cell by applying a non-destructive read out (NDRO) method to the 1-transistor DRAM so that the data of the cell is not destroyed during the read operation.

In addition, an object of the present invention is to implement a 1-transistor type DRAM to significantly reduce the cell size.

In order to achieve the above object, a multi-level driving method of a 1-transistor type DRAM according to the present invention maintains data stored in a floating body storage device connected between a bit line and a source line and controlled by a word line. A data maintaining step; A data storage step of generating hot carriers in the floating body storage element according to the supply of the write voltage having the multi-levels, and writing the first data having the multi-levels according to the current flowing from the source line to the bit line; And a discharge step of releasing an activated carrier in the floating body storage element according to the discharge current flowing from the bit line to the source line.

In addition, the present invention includes a data holding step connected between a bit line and a source line to hold data stored in a floating body storage element controlled by a word line; A data storage step of generating hot carriers in the floating body storage device according to the supply of the write voltage having the multi-levels and writing the first data having the multi-levels according to the current flowing from the bit line to the source line; And a first negative voltage is applied to the word line, a first voltage is applied to the source line, and a second voltage is applied to the bit line to maintain the first data.

In addition, the present invention provides a multi-level driving method of a 1-transistor DRAM using a floating body storage element connected between a bit line and a source line and controlled by a word line, wherein a negative voltage is applied to the word line. A data holding step of applying a first voltage to a source line and a second voltage to a bit line to hold multi-level data stored in the floating body storage device; Reading a multi-level data according to a sensing current flowing from a bit line to a source line by applying a read voltage to the word line; And maintaining a multi-level data by applying a negative voltage to the word line.

The present invention provides the following effects.

First, in the 1-transistor type DRAM using a floating body storage device, the efficiency of hot carriers is increased to effectively read / write data and to stably drive the device.

Second, in the 1-transistor type DRAM using a floating body storage element, the amount of hot carriers in the floating body can be adjusted to easily read / write a plurality of data. do.

Third, the present invention applies a non-destructive read out (NDRO) method to a 1-transistor type DRAM so that the data of the cell is not destroyed during read operation, thereby improving cell reliability.

Fourth, the present invention implements a 1-transistor type DRAM to provide an effect of significantly reducing the cell size.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1 is a cross-sectional view illustrating a unit cell of a 1-transistor DRAM according to the present invention.

The silicon on insulator (SOI) wafer 10 has a stacked structure of a silicon substrate 1, a buried oxide layer 2, and a silicon layer 3. An isolation layer 11 defining an active region in the silicon layer 3 of the SOI wafer 10 is formed in contact with the buried oxide film 2.

The gate 12 is formed on the active region of the silicon layer 3. In addition, source / drain regions 13a and 13b are formed in the silicon layer 3 on both sides of the gate 12 to contact the buried oxide film 2.

In the DRAM cell implemented in the SOI wafer 10, data is stored by trapping holes and electrons in a floating body 15 corresponding to a channel region under the gate 12. .

For example, as shown in FIG. 2A, the data “1” store state may be understood as a state where there are many holes in the floating body 15. In addition, as shown in FIG. 2B, the data “0” storage state may be understood as a state in which the floating body 15 has few holes or a lot of electrons.

3 is a waveform diagram illustrating characteristics of a multi-level read current of a 1-transistor DRAM according to the present invention.

3 shows a cell read when the cell gate voltage is set to 0.2V for the DRAM cell implemented in the SOI wafer 10, and the cell gate voltage is sweeped while the cell source voltage is set to ground GND. A graph showing the current.

In the embodiment of the present invention, storing 2-bit data using four levels of current is described as the embodiment.

That is, when the word line read voltage is applied to the word line WL, the read current flows from the bit line BL toward the source line SL. At this time, if the amount of the sensing current flowing is larger than the reference current ref2, the data "11" is read. If the amount of sensing current is greater than the reference current ref1, the data "10" is read. If the value of the read current is larger than the reference current ref0, the data "01" is read. If the value of the read current is smaller than the reference current ref0, the data "00" is read.

The current level of data "11" is the highest, and the current level of data "10" is lower than the current level of data "11". Then, the current level of data "01" is lower than the current level of data "10", and the current level of data "00" is lower than the current level of data "01". Values of the reference currents ref0, ref1, and ref2 exist between the four level currents to perform the multi-level read operation.

4A and 4B are circuit diagrams for describing a method of writing data “00” of a 1-transistor DRAM according to the present invention.

In the 1-transistor DRAM of the present invention, the source line SL and the bit line BL are connected to the source 13a and the drain 13b of the floating body transistor FBT, respectively, and the word line WL is connected to the gate 12.

The unit cell component of the present invention is composed of an NMOS transistor component and a parasitic NPN bipolar transistor component. That is, a parasitic Bipolar Junction Transistor (BJT) is formed between the floating body 15 which is the base end of the parasitic NPN bipolar transistor, the source line SL which is the emitter end, and the bit line BL which is the collector end. .

4C is a timing diagram for describing the operation of FIGS. 4A and 4B.

In the 1-transistor type DRAM cell of the present invention, the timing for writing data "00" is divided into t0 to t4 sections. Here, the t0 and t4 sections are hold sections that hold data. The t1 section is a Morse and BJT operation section, the t2 section is a parasitic BJT operation section, and the t1, t2 section is a data “0” write section WT0. In addition, the t3 section is a discharge section.

First, in the t0 period, that is, the first hold period, the word line WL maintains a negative voltage NEG1 level. The source line SL maintains the low voltage Vpre_L level, and the bit line BL maintains the high voltage Vpre_H level. Accordingly, the data is maintained in the floating body 15 in the t0 section.

Thereafter, in the period t1, the MOS transistor operation is performed by the voltage of the word line WL transitions to a high level in order to write data to the cell. In addition, the bit line BL transitions to the negative voltage NEG2 level while the source line SL maintains the low voltage Vpre_L level. Accordingly, the data "00" write current Iwt00 flows from the source line SL toward the bit line BL, thereby generating a high energy hole carrier in the floating body 15.

At this time, a forward bias is applied between the P-type semiconductor of the floating body 15 of the MOS transistor and the N-type semiconductor of the source line SL. Accordingly, the parasitic BJT starts operation to generate hot carriers.

Thereafter, in the period t2 for writing the data "0", the word line WL transitions to the negative voltage NEG1 level. Accordingly, the t2 section is a section in which only the parasitic BJT operation is performed. At this time, the source line SL maintains the low voltage Vpre_L level, and the bit line BL maintains the negative voltage NEG2 level.

Subsequently, in the period t3, that is, the discharge period, the bit line BL transitions to the high voltage Vpre_H level while the source line SL maintains the low voltage Vpre_L level. Accordingly, the discharge current Idischarge flows from the floating body 15 toward the source line SL. Therefore, a hole carrier that has been activated with high energy in the floating body 15 is released toward the source line SL.

That is, the potential of the floating body 15 is made high in the t1 and t2 sections, and then the hot carrier is released toward the source line SL in the t3 section to increase the emission efficiency of the carrier. Then, when the release time of the carrier passes, it enters the data hold mode in the t4 section.

5 is a waveform diagram showing the data "00" operating voltage of a 1-transistor DRAM according to the present invention.

The high voltage Vpre_H has a level higher than the read voltage Vread. The write voltage V10 is lower than the read voltage Vread and has a level higher than the low voltage Vpre_L. The low voltage Vpre_L is lower than the write voltage V10 and has a level higher than the write voltage V01.

In addition, the write voltage V01 is lower than the low voltage Vpre_L level and has a level higher than the ground voltage GND. In addition, the negative voltage NEG2 level is lower than the ground voltage GND and has a level higher than the negative voltage NEG1. The negative voltage NEG1 level has a lower level than the negative voltage NEG2.

6A is a circuit diagram illustrating a method of writing data "01" of a 1-transistor DRAM according to the present invention.

In the 1-transistor DRAM of the present invention, the source line SL and the bit line BL are connected to the source 13a and the drain 13b of the floating body transistor FBT, respectively, and the word line WL is connected to the gate 12.

6B is a timing diagram for describing the operation of FIG. 6A.

In the 1-transistor type DRAM cell of the present invention, the timing for writing data "01" is divided into t0 to t3 sections. Here, the t0 and t3 sections are hold sections that hold data. The t1 section is a Morse and BJT operation section, the t2 section is a parasitic BJT operation section, and the t1, t2 section is a data “01” writing section.

First, in the t0 period, that is, the first hold period, the word line WL maintains a negative voltage NEG1 level. The source line SL maintains the low voltage Vpre_L level, and the bit line BL maintains the high voltage Vpre_H level. Accordingly, the data is maintained in the floating body 15 in the t0 section.

Thereafter, in the period t1, the MOS transistor operation is performed by the voltage of the word line WL transitions to a high level in order to write data to the cell. In addition, the source line SL transitions to the negative voltage NEG2 level, and the bit line BL transitions to the write voltage V01 level. Accordingly, the data "01" write current Iwt01 flows from the bit line BL toward the source line SL.

Then, a forward bias is applied between the P-type semiconductor of the floating body 15 of the MOS transistor and the N-type semiconductor of the source line SL. Accordingly, the parasitic BJT starts operation to generate hot carriers.

Thereafter, in the period t2 for writing the data "01", the word line WL transitions to the negative voltage NEG1 level. Accordingly, the t2 section is a section in which only the parasitic BJT operation is performed. At this time, the source line SL maintains the negative voltage NEG2 level, and the bit line BL maintains the write voltage V01 level.

Next, in the period t3, that is, the second hold period, the source line SL transitions to the low voltage Vpre_L level, and the bit line BL transitions to the high voltage Vpre_H level. As a result, the system enters a data hold mode that maintains a hot carrier.

Accordingly, the data " 01 " writing method of the 1-transistor type DRAM according to the present invention causes the current Iwt01 to flow from the bit line BL toward the source line SL, thereby generating a high energy hole carrier in the floating body 15. Next, the hole carriers that were activated with high energy in the floating body 15 are retained.

7 is a waveform diagram showing the data "01" operating voltage of the one-transistor DRAM according to the present invention.

The high voltage Vpre_H has a level higher than the read voltage Vread. The write voltage V10 is lower than the read voltage Vread and has a level higher than the low voltage Vpre_L. The low voltage Vpre_L is lower than the write voltage V10 and has a level higher than the write voltage V01.

In addition, the write voltage V01 is lower than the low voltage Vpre_L level and has a level higher than the ground voltage GND. In addition, the negative voltage NEG2 level is lower than the ground voltage GND and has a level higher than the negative voltage NEG1. The negative voltage NEG1 level has a lower level than the negative voltage NEG2.

8A is a circuit diagram illustrating a method of writing data “10” of a 1-transistor DRAM according to the present invention.

In the 1-transistor DRAM of the present invention, the source line SL and the bit line BL are connected to the source 13a and the drain 13b of the floating body transistor FBT, respectively, and the word line WL is connected to the gate 12.

8B is a timing diagram for describing the operation of FIG. 8A.

In the 1-transistor type DRAM cell of the present invention, timing for writing data " 10 " is divided into intervals t0 to t3. Here, the t0 and t3 sections are hold sections that hold data. The t1 section is a Morse and BJT operation section, the t2 section is a parasitic BJT operation section, and the t1, t2 section is a data “01” writing section.

First, in the t0 period, that is, the first hold period, the word line WL maintains a negative voltage NEG1 level. The source line SL maintains the low voltage Vpre_L level, and the bit line BL maintains the high voltage Vpre_H level. Accordingly, the data is maintained in the floating body 15 in the t0 section.

Thereafter, in the period t1, the MOS transistor operation is performed by the voltage of the word line WL transitions to a high level in order to write data to the cell. In addition, the source line SL transitions to the negative voltage NEG2 level, and the bit line BL transitions to the write voltage V10 level. As a result, the data " 10 " write current Iwt10 flows from the bit line BL toward the source line SL.

Then, a forward bias is applied between the P-type semiconductor of the floating body 15 of the MOS transistor and the N-type semiconductor of the source line SL. Accordingly, the parasitic BJT starts operation to generate hot carriers.

Thereafter, in the period t2 for writing the data "10", the word line WL transitions to the negative voltage NEG1 level. Accordingly, the t2 section is a section in which only the parasitic BJT operation is performed. At this time, the source line SL maintains the negative voltage NEG2 level, and the bit line BL maintains the write voltage V10 level.

Next, in the period t3, that is, the second hold period, the source line SL transitions to the low voltage Vpre_L level, and the bit line BL transitions to the high voltage Vpre_H level. As a result, the system enters a data hold mode that maintains a hot carrier.

Accordingly, the data " 10 " writing method of the 1-transistor type DRAM according to the present invention causes the current Iwt01 to flow from the bit line BL toward the source line SL, thereby generating a high energy hole carrier in the floating body 15. Next, the hole carriers that were activated with high energy in the floating body 15 are retained.

9 is a waveform diagram showing the data "10" operating voltage of the one-transistor DRAM according to the present invention.

The high voltage Vpre_H has a level higher than the read voltage Vread. The write voltage V10 is lower than the read voltage Vread and has a level higher than the low voltage Vpre_L. The low voltage Vpre_L is lower than the write voltage V10 and has a level higher than the write voltage V01.

In addition, the write voltage V01 is lower than the low voltage Vpre_L level and has a level higher than the ground voltage GND. In addition, the negative voltage NEG2 level is lower than the ground voltage GND and has a level higher than the negative voltage NEG1. The negative voltage NEG1 level has a lower level than the negative voltage NEG2.

10A is a circuit diagram illustrating a method of writing data “11” of a 1-transistor DRAM according to the present invention.

In the 1-transistor type DRAM of the present invention, the source line SL and the bit line BL are connected to the source 13a and the drain 13b of the floating body transistor FBT, and the word line WL is connected to the gate 12.

10B is a timing diagram for describing the operation of FIG. 10A.

In the 1-transistor type DRAM cell of the present invention, the timing for writing data "11" is divided into t0 to t3 sections. Here, the t0 and t3 sections are hold sections that hold data. The t1 section is a Morse and BJT operation section, the t2 section is a parasitic BJT operation section, and the t1, t2 section is a data “11” writing section.

First, in the t0 period, that is, the first hold period, the word line WL maintains a negative voltage NEG1 level. The source line SL maintains the low voltage Vpre_L level, and the bit line BL maintains the high voltage Vpre_H level. Accordingly, the data is maintained in the floating body 15 in the t0 section.

Thereafter, in the period t1, the MOS transistor operation is performed by the voltage of the word line WL transitions to a high level in order to write data to the cell. In addition, the source line SL transitions to the negative voltage NEG2 level, and the bit line BL maintains the high voltage Vpre_H level. As a result, the data " 11 " write current Iwt11 flows from the bit line BL toward the source line SL.

Then, a forward bias is applied between the P-type semiconductor of the floating body 15 of the MOS transistor and the N-type semiconductor of the source line SL. Accordingly, the parasitic BJT starts operation to generate hot carriers.

Thereafter, in the period t2 for writing the data "11", the word line WL transitions to the negative voltage NEG1 level. Accordingly, the t2 section is a section in which only the parasitic BJT operation is performed. At this time, the source line SL maintains the negative voltage NEG2 level, and the bit line BL maintains the high voltage Vpre_H level.

Next, in the period t3, that is, the second hold period, the source line SL transitions to the low voltage Vpre_L level, and the bit line BL maintains the high voltage Vpre_H level. As a result, the system enters a data hold mode that maintains a hot carrier.

Accordingly, the data " 11 " writing method of the 1-transistor type DRAM according to the present invention causes the current Iwt11 to flow from the bit line BL toward the source line SL, thereby generating a high energy hole carrier in the floating body 15. Next, the hole carriers that were activated with high energy in the floating body 15 are retained.

Fig. 11 is a waveform diagram showing the data " 11 " operating voltage of the one-transistor DRAM according to the present invention.

The high voltage Vpre_H has a level higher than the read voltage Vread. The write voltage V10 is lower than the read voltage Vread and has a level higher than the low voltage Vpre_L. The low voltage Vpre_L is lower than the write voltage V10 and has a level higher than the write voltage V01.

In addition, the write voltage V01 is lower than the low voltage Vpre_L level and has a level higher than the ground voltage GND. In addition, the negative voltage NEG2 level is lower than the ground voltage GND and has a level higher than the negative voltage NEG1. The negative voltage NEG1 level has a lower level than the negative voltage NEG2.

12A is a circuit diagram illustrating a data read method of a 1-transistor DRAM according to the present invention.

In the 1-transistor DRAM of the present invention, the source line SL and the bit line BL are connected to the source 13a and the drain 13b of the floating body transistor FBT, respectively, and the word line WL is connected to the gate 12.

12B is a timing diagram for describing the operation of FIG. 12A.

In the 1-transistor type DRAM cell of the present invention, the timing for reading data is divided into t0 to t2 sections. Here, the t0 and t2 sections are hold sections that hold data. The t1 section is a section for performing data read.

First, in the t0 period, that is, the first hold period, the word line WL maintains a negative voltage NEG1 level. The source line SL maintains the low voltage Vpre_L level, and the bit line BL maintains the high voltage Vpre_H level. Accordingly, the data is maintained in the floating body 15 in the t0 section.

Thereafter, in the period t1, the voltage of the word line WL transitions to the read voltage Vread level in order to read data stored in the cell. At this time, the source line SL maintains the low voltage Vpre_L level, and the bit line BL maintains the high voltage Vpre_H level. As a result, a sensing current Isense flows from the bit line BL toward the source line SL.

In other words, the drain source voltage Vds for sensing the sensing current Isense is applied between the bit line BL and the source line SL to read the multi data.

Subsequently, in the t2 period, that is, the second hold period, the word line WL transitions to the negative voltage NEG1 level. The source line SL maintains the low voltage Vpre_L level, and the bit line BL maintains the high voltage Vpre_H level.

13A to 13D are waveform diagrams of cell read current signals in read cycles.

FIG. 13A is a waveform diagram illustrating cell read current when sensing data “11” of a read cycle, and FIG. 13B is a waveform diagram illustrating cell read current when sensing data “10” of a read cycle. FIG. 13C is a waveform diagram illustrating a cell lead current when sensing data "01" of a read cycle, and FIG. 13D is a waveform diagram illustrating a cell lead current when sensing data "00" of a read cycle.

1 is a cross-sectional view showing a unit cell of a 1-transistor type DRAM according to the present invention.

2A and 2B show cell data storage states of a 1-transistor DRAM according to the present invention;

Figure 3 is a waveform diagram showing the characteristics of the multi-level read current of the 1-transistor DRAM according to the present invention.

4A and 4B are circuit diagrams for explaining a method of writing data “00” of a 1-transistor DRAM according to the present invention;

4C is a timing diagram for explaining the operation of FIGS. 4A and 4B.

Figure 5 is a waveform diagram showing the data "00" operating voltage of the 1-transistor DRAM according to the present invention.

FIG. 6A is a circuit diagram illustrating a method of writing data “01” of a 1-transistor DRAM according to the present invention; FIG.

6B is a timing diagram for explaining the operation of FIG. 6A.

Fig. 7 is a waveform diagram showing the data " 01 " operating voltage of the 1-transistor DRAM according to the present invention.

FIG. 8A is a circuit diagram for explaining a method of writing data “10” of a 1-transistor DRAM according to the present invention; FIG.

FIG. 8B is a timing diagram for explaining the operation of FIG. 8A; FIG.

Figure 9 is a waveform diagram showing the data "10" operating voltage of the one-transistor DRAM according to the present invention.

Fig. 10A is a circuit diagram for explaining a data " 11 " writing method of a 1-transistor DRAM according to the present invention.

10B is a timing diagram for explaining the operation of FIG. 10A.

Fig. 11 is a waveform diagram showing the data " 11 " operating voltage of the one-transistor DRAM according to the present invention.

12A is a circuit diagram illustrating a multi-level read method of a 1-transistor DRAM according to the present invention.

12B is a timing diagram for explaining the operation of FIG. 12A.

13A to 13D are waveform diagrams of cell read current signals in read cycles.

Claims (35)

A data holding step of holding data stored in a floating body storage element connected between the bit line and the source line and controlled by the word line; A data storage step of generating hot carriers in the floating body storage device according to the supply of the write voltage having the multi-levels, and writing the first data having the multi-levels according to the current flowing from the source line to the bit line; And And a discharge step of discharging a carrier activated in the floating body storage device in response to a discharge current flowing from the bit line to the source line. The method of claim 1, wherein the data holding step A first negative voltage is applied to the word line, a first voltage is applied to the source line, and a second voltage is applied to the bit line. 3. The method of claim 2, wherein the second voltage has a level higher than the first voltage. 4. The method of claim 2, wherein the first negative voltage has a lower level than the first voltage. The method of claim 1, wherein storing the data Applying a high voltage to the word line, applying a first voltage to the source line, and applying a second negative voltage to the bit line; And And a first negative voltage is applied to the word line, the first voltage is applied to the source line, and the second negative voltage is applied to the bit line. Multi-level driving method of DRAM. 6. The method of claim 5, wherein the first voltage has a higher level than the second negative voltage. 6. The method of claim 5, wherein the second negative voltage has a higher level than the first negative voltage. The method of claim 1, wherein the first data is 2-bit data. 9. The method of claim 8, wherein the 2-bit data is data " 00. " The method of claim 1, wherein the discharge step A first negative voltage is applied to the word line, a first voltage is applied to the source line, and a second voltage is applied to the bit line. 11. The method of claim 10, wherein the second voltage has a level higher than the first voltage. 11. The method of claim 10, wherein the first negative voltage has a lower level than the first voltage. The method of claim 1, further comprising maintaining the first data stored in the floating body storage device after the discharge step. A data holding step of holding data stored in a floating body storage element connected between the bit line and the source line and controlled by the word line; A data storage step of generating hot carriers in the floating body storage device according to a supply of a write voltage having a multi-level to write first data having a multi-level according to a current flowing from the bit line to the source line; And And a first negative voltage is applied to the word line, a first voltage is applied to the source line, and a second voltage is applied to the bit line to maintain the first data. Multi-level driving method of 1-transistor DRAM. 15. The method of claim 14, wherein maintaining data is The first negative voltage is applied to the word line, the first voltage is applied to the source line, and the second voltage is applied to the bit line. Way. 15. The method of claim 14, wherein the second voltage has a higher level than the first voltage. 15. The method of claim 14, wherein the first negative voltage has a lower level than the first voltage. 15. The method of claim 14, wherein storing data is Applying a high voltage to the word line, applying a second negative voltage to the source line, and applying a first write voltage to the bit line; And A first negative voltage is applied to the word line, the second negative voltage is applied to the source line, and the first write voltage is applied to the bit line. Multi-level driving method of type DRAM. 19. The method of claim 18, wherein the first write voltage is higher than the first voltage and higher than the second negative voltage. 19. The method of claim 18, wherein the second negative voltage has a higher level than the first negative voltage. 19. The method of claim 18, wherein the first data is 2-bit data. 22. The method of claim 21, wherein the 2-bit data is data " 01. " 15. The method of claim 14, wherein storing data is Applying a high voltage to the word line, applying a second negative voltage to the source line, and applying a second write voltage to the bit line; And A first negative voltage is applied to the word line, the second negative voltage is applied to the source line, and the second write voltage is applied to the bit line. Multi-level driving method of type DRAM. 24. The method of claim 23, wherein the second write voltage is lower than the second voltage and has a level higher than the first voltage. 24. The method of claim 23, wherein the second negative voltage has a higher level than the first negative voltage. 24. The method of claim 23, wherein the first data is 2-bit data. 27. The method of claim 26, wherein the 2-bit data is data " 10 ". 15. The method of claim 14, wherein storing data is Applying a high voltage to the word line, applying a second negative voltage to the source line, and applying the second voltage to the bit line; And And a first negative voltage is applied to the word line, the second negative voltage is applied to the source line, and the second voltage is applied to the bit line. Multi-level driving method of DRAM. 29. The method of claim 28, wherein the second negative voltage has a higher level than the first negative voltage. 29. The method of claim 28, wherein the first data is 2-bit data. 31. The method of claim 30, wherein the 2-bit data is data " 11 ". 1. A multi-level driving method of a 1-transistor DRAM using a floating body storage element connected between a bit line and a source line and controlled by a word line. A data holding step of applying a negative voltage to the word line, a first voltage to the source line, and a second voltage to the bit line to maintain multi-level data stored in the floating body storage device; Reading a multi-level data according to a sensing current flowing from the bit line to the source line by applying a read voltage to the word line; And And applying the negative voltage to the word line to maintain the multi-level data. 33. The method of claim 32, wherein the second voltage has a higher level than the first voltage. 33. The method of claim 32, wherein the negative voltage has a lower level than the first voltage. 33. The method of claim 32, wherein the multi-level data is 2-bit data.

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