KR20090002797A - Method for driving of one transistor type dram - Google Patents

Abstract

A method for driving of one transistor type DRAM is provided to prevent the break down of cell data in reading by applying the NDRO(Non Destructive Read Out) mode. A method for driving of one transistor type DRAM is comprised of steps: controlling a word line to maintain a negative level for t0 period; controlling the source line(SL) to maintain the low voltage(Vpre L) level; controlling the bit line(BL) to maintain the high voltage(Vpre H) level; operating the MOS transistor by transiting to the voltage of the word line for t1 period to the high level in which the cell is activated; transiting the word line to negative voltage level for the t2 period; controlling the source line to maintain the low voltage level for t3 period; transiting the bit line to the high voltage level; performing the data retention(Hold) mode for t4 period.

Description

Method for driving 1-transistor type DRAM {Method for driving of one transistor type DRAM}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a 1-transistor type DRAM, and is a technique for increasing the release efficiency of a hot carrier in a 1-transistor type DRAM using a floating body storage element.

In general, semiconductor devices such as DRAM are integrated on a silicon wafer. However, silicon wafers used in semiconductor devices are not used for the operation of the device but only a limited thickness of several micrometers from the surface for device operation. As a result, the remaining silicon wafers, except for those required for the operation of the device, increase power consumption and reduce driving speeds.

Accordingly, there is a need for a silicon on insulator (SOI) wafer formed by forming a silicon single crystal layer having a thickness of several μm through an insulating layer on a silicon substrate. The semiconductor device integrated on the SOI wafer can be speeded up by the small junction capacity compared to the semiconductor device integrated on the conventional silicon wafer, and has the advantages of speeding up and voltage reduction due to the low voltage due to the low threshold voltage.

However, in a semiconductor device integrated in such an SOI wafer, when the emission efficiency of a hot carrier stored in a floating body is low, data cannot be read / written effectively and the device cannot be stably driven. do.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and in the 1-transistor type DRAM using a floating body storage element, it is possible to effectively read / write data by increasing the hot carrier (Hot Carrier) emission efficiency. The purpose is to enable the device to be driven stably.

In addition, an object of the present invention is to improve the reliability of the cell by applying a non-destructive read out (NDRO) method to the 1-transistor DRAM so that the data of the cell is not destroyed during the read operation.

In addition, an object of the present invention is to implement a 1-transistor type DRAM to significantly reduce the cell size.

In order to achieve the above object, a method of driving a 1-transistor type DRAM according to an embodiment of the present invention may include data for maintaining data stored in a floating body storage device connected between a bit line and a source line and controlled by a word line. Maintenance step; A data storage step of generating hot carriers in the floating body storage element and writing first data according to a current flowing from the source line to the bit line; And a discharge step of releasing an activated carrier in the floating body storage element according to a discharge current flowing from the bit line to the source line.

In addition, the present invention includes a data holding step connected between a bit line and a source line to hold data stored in a floating body storage element controlled by a word line; A data storage step of generating hot carriers in the floating body storage element and writing first data according to a current flowing from the bit line to the source line; And maintaining the first data stored in the floating body storage element.

In addition, the present invention provides a method of driving a 1-transistor type DRAM using a floating body storage element connected between a bit line and a source line and controlled by a word line, wherein a negative voltage is applied to the word line. A data holding step of holding a data stored in the floating body storage device by applying a first voltage to a source line and applying a second voltage to a bit line; Reading data according to a sensing current flowing from a bit line to a source line by applying a read voltage to the word line; And applying a negative voltage to the word line to hold the data.

The present invention provides the following effects.

First, in the 1-transistor type DRAM using a floating body storage device, the efficiency of hot carriers is increased to effectively read / write data and to stably drive the device.

Second, the present invention applies a non-destructive read out (NDRO) method to a 1-transistor DRAM so that data of a cell is not destroyed during a read operation, thereby improving cell reliability and reading speed.

Third, the present invention provides an effect of drastically reducing cell size by implementing a 1-transistor type DRAM.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1 is a cross-sectional view illustrating a unit cell of a 1-transistor DRAM according to the present invention.

The silicon on insulator (SOI) wafer 10 has a stacked structure of a silicon substrate 1, a buried oxide layer 2, and a silicon layer 3. An isolation layer 11 defining an active region in the silicon layer 3 of the SOI wafer 10 is formed in contact with the buried oxide film 2.

The gate 12 is formed on the active region of the silicon layer 3. In addition, source / drain regions 13a and 13b are formed in the silicon layer 3 on both sides of the gate 12 to contact the buried oxide film 2.

In the DRAM cell implemented in the SOI wafer 10, data is stored by trapping holes and electrons in a floating body 15 corresponding to a channel region under the gate 12. .

For example, as shown in FIG. 2A, the data “1” store state may be understood as a state where there are many holes in the floating body 15. As shown in FIG. 2B, the data “0” storage state may be understood as a state in which the floating body 15 has few holes or a lot of electrons.

3 is a waveform diagram illustrating the characteristics of the cell lead current of the 1-transistor DRAM according to the present invention.

3 shows a cell read when the cell gate voltage is set to 0.2V for the DRAM cell implemented in the SOI wafer 10, and the cell gate voltage is sweeped while the cell source voltage is set to ground GND. A graph showing the current.

That is, when the word line read voltage is applied to the word line WL, the read current flows from the bit line BL toward the source line SL. At this time, if the amount of sensing current flowing is larger than the reference current, data "1" is read, and if it is lower than the reference current, data "0" is read.

As shown, the 1-transistor cell in the read state flows a larger amount of sensing current when in the data "1" storage state than in the data "0" storage state. That is, the read current is largest when the data "1" is stored, and the read current is smallest when the data "0". The reference current REF has a read current value corresponding to an intermediate value between the data "1" storage state and the data "0" storage state.

4A and 4B are circuit diagrams for describing a method of writing data “0” of a 1-transistor DRAM according to the present invention.

In the 1-transistor DRAM of the present invention, the source line SL and the bit line BL are connected to the source 13a and the drain 13b of the floating body transistor FBT, respectively, and the word line WL is connected to the gate 12.

The unit cell component of the present invention is composed of an NMOS transistor component and a parasitic NPN bipolar transistor component. That is, a parasitic Bipolar Junction Transistor (BJT) is formed between the floating body 15 which is the base end of the parasitic NPN bipolar transistor, the source line SL which is the emitter end, and the bit line BL which is the collector end. .

4C is a timing diagram for describing the operation of FIGS. 4A and 4B.

In the 1-transistor type DRAM cell of the present invention, the timing for writing data "0" is divided into t0 to t4 sections. Here, the t0 and t4 sections are hold sections that hold data. The t1 section is a Morse and BJT operation section, the t2 section is a parasitic BJT operation section, and the t1, t2 section is a data “0” write section WT0. In addition, the t3 section is a discharge section.

First, in the t0 period, that is, the first hold period, the word line WL maintains a negative voltage NEG1 level. The source line SL maintains the low voltage Vpre_L level, and the bit line BL maintains the high voltage Vpre_H level. Accordingly, the data is maintained in the floating body 15 in the t0 section.

Thereafter, in the period t1, the MOS transistor operation is performed by transitioning the voltage of the word line WL to the high level of the cell activation voltage in order to write data to the cell. In addition, the bit line BL transitions to the negative voltage NEG2 level while the source line SL maintains the low voltage Vpre_L level. As a result, the data " 0 " write current Iwt0 flows from the source line SL toward the bit line BL.

Then, a forward bias is applied between the P-type semiconductor of the floating body 15 of the MOS transistor and the N-type semiconductor of the source line SL. Accordingly, the parasitic BJT starts operation to generate hot carriers.

Thereafter, in the period t2 for writing the data "0", the word line WL transitions to the negative voltage NEG1 level. Accordingly, the t2 section is a section in which only the parasitic BJT operation is performed. At this time, the source line SL maintains the low voltage Vpre_L level, and the bit line BL maintains the negative voltage NEG2 level.

Subsequently, in the period t3, that is, the discharge period, the bit line BL transitions to the high voltage Vpre_H level while the source line SL maintains the low voltage Vpre_L level. Accordingly, the discharge current Idischarge flows from the floating body 15 toward the source line SL. Therefore, a hole carrier that has been activated with high energy in the floating body 15 is released toward the source line SL.

That is, the potential of the floating body 15 is made high in the t1 and t2 sections, and then the hot carrier is released toward the source line SL in the t3 section to increase the emission efficiency of the carrier. Then, when the release time of the carrier passes, it enters the data hold mode in the t4 section.

5 is a view for explaining a method of writing data "0" of a 1-transistor DRAM according to the present invention.

First, a current Iwt0 flows from the source line SL toward the bit line BL, thereby generating a high energy hole carrier in the floating body 15. Next, the hole carriers that were activated with high energy in the floating body 15 are released toward the source line SL.

FIG. 6 is a waveform diagram illustrating a data “0” operating voltage of a 1-transistor DRAM according to the present invention. FIG.

The high voltage Vpre_H level has a level higher than the read voltage Vread voltage. The low voltage Vpre_L level is lower than the read voltage Vread voltage and higher than the ground voltage GND. In addition, the negative voltage NEG2 level is lower than the ground voltage GND and has a level higher than the negative voltage NEG1. The negative voltage NEG1 level has a lower level than the negative voltage NEG2.

FIG. 7A is a circuit diagram illustrating a method of writing data “1” of a 1-transistor DRAM according to the present invention.

In the 1-transistor DRAM of the present invention, the source line SL and the bit line BL are connected to the source 13a and the drain 13b of the floating body transistor FBT, respectively, and the word line WL is connected to the gate 12.

FIG. 7B is a timing diagram for describing the operation of FIG. 7A.

In the 1-transistor type DRAM cell of the present invention, the timing for writing data "1" is divided into t0 to t3 sections. Here, the t0 and t3 sections are hold sections that hold data. The t1 section is a Morse and BJT operation section, the t2 section is a parasitic BJT operation section, and the t1, t2 section is a data “1” write section WT1.

First, in the t0 period, that is, the first hold period, the word line WL maintains a negative voltage NEG1 level. The source line SL maintains the low voltage Vpre_L level, and the bit line BL maintains the high voltage Vpre_H level. Accordingly, the data is maintained in the floating body 15 in the t0 section.

Thereafter, in the period t1, the MOS transistor operation is performed by the voltage of the word line WL transitions to a high level in order to write data to the cell. In addition, the source line SL transitions to the negative voltage NEG2 level, and the bit line BL maintains the high voltage Vpre_H level. As a result, the data " 1 " write current Iwt1 flows from the bit line BL toward the source line SL.

Then, a forward bias is applied between the P-type semiconductor of the floating body 15 of the MOS transistor and the N-type semiconductor of the source line SL. Accordingly, the parasitic BJT starts operation to generate hot carriers.

Thereafter, in the period t2 for writing the data "1", the word line WL transitions to the negative voltage NEG1 level. Accordingly, the t2 section is a section in which only the parasitic BJT operation is performed. At this time, the source line SL maintains the negative voltage NEG2 level, and the bit line BL maintains the high voltage Vpre_H level.

Next, in the period t3, that is, the second hold period, the source line SL transitions to the low voltage Vpre_L level, and the bit line BL maintains the high voltage Vpre_H level. As a result, the system enters a data hold mode that maintains a hot carrier.

8 is a view for explaining a method of writing data "1" of a 1-transistor DRAM according to the present invention.

First, the current Iwt1 flows from the bit line BL toward the source line SL, thereby generating a high energy hole carrier in the floating body 15. Next, the hole carriers that were activated with high energy in the floating body 15 are retained.

9 is a waveform diagram showing the data "1" operating voltage of the one-transistor DRAM according to the present invention.

The high voltage Vpre_H level has a level higher than the read voltage Vread voltage. The low voltage Vpre_L level is lower than the read voltage Vread voltage and higher than the ground voltage GND. In addition, the negative voltage NEG2 level is lower than the ground voltage GND and has a level higher than the negative voltage NEG1. The negative voltage NEG1 level has a lower level than the negative voltage NEG2.

10A is a circuit diagram illustrating a data read method of a 1-transistor DRAM according to the present invention.

In the 1-transistor type DRAM of the present invention, the source line SL and the bit line BL are connected to the source 13a and the drain 13b of the floating body transistor FBT, and the word line WL is connected to the gate 12.

10B is a timing diagram for describing the operation of FIG. 10A.

In the 1-transistor type DRAM cell of the present invention, the timing for reading data is divided into t0 to t2 sections. Here, the t0 and t2 sections are hold sections that hold data. The t1 section is a section for performing data read.

First, in the t0 period, that is, the first hold period, the word line WL maintains a negative voltage NEG1 level. The source line SL maintains the low voltage Vpre_L level, and the bit line BL maintains the high voltage Vpre_H level. Accordingly, the data is maintained in the floating body 15 in the t0 section.

Thereafter, in the period t1, the voltage of the word line WL transitions to the read voltage Vread level in order to read data stored in the cell. At this time, the source line SL maintains the low voltage Vpre_L level, and the bit line BL maintains the high voltage Vpre_H level. As a result, a sensing current Isense flows from the bit line BL toward the source line SL.

That is, the cell data is read between the bit line BL and the source line SL by applying the drain source voltage Vds for sensing the sensing current Isense.

Subsequently, in the t2 period, that is, the second hold period, the word line WL transitions to the negative voltage NEG1 level. The source line SL maintains the low voltage Vpre_L level, and the bit line BL maintains the high voltage Vpre_H level.

11A and 11B are waveform diagrams of cell read current signals in read cycles.

FIG. 11A is a waveform diagram illustrating a cell read current when sensing data “1” of a read cycle. FIG. FIG. 11B is a waveform diagram illustrating a cell read current when sensing data “0” of a read cycle. FIG.

1 is a cross-sectional view showing a unit cell of a 1-transistor type DRAM according to the present invention.

2A and 2B show cell data storage states of a 1-transistor DRAM according to the present invention;

Figure 3 is a waveform diagram showing the characteristics of the cell lead current of the 1-transistor DRAM according to the present invention.

4A and 4B are circuit diagrams for explaining a method of writing data “0” of a 1-transistor DRAM according to the present invention;

4C is a timing diagram for explaining the operation of FIGS. 4A and 4B.

5 is a view for explaining a method of writing data "0" of a 1-transistor DRAM according to the present invention;

Figure 6 is a waveform diagram showing the data "0" operating voltage of the one-transistor DRAM according to the present invention.

FIG. 7A is a circuit diagram for explaining a method of writing data “1” of a 1-transistor DRAM according to the present invention; FIG.

FIG. 7B is a timing diagram for explaining the operation of FIG. 7A; FIG.

8 is a view for explaining a data " 1 " writing method of a 1-transistor DRAM according to the present invention;

9 is a waveform diagram showing a data "1" operating voltage of a one-transistor DRAM according to the present invention;

10A is a circuit diagram for explaining a data read method of a 1-transistor DRAM according to the present invention;

10B is a timing diagram for explaining the operation of FIG. 10A.

11A and 11B are waveform diagrams of cell lead current signals in lead cycles.

Claims (23)

A data holding step of holding data stored in a floating body storage element connected between the bit line and the source line and controlled by the word line; A data storage step of generating hot carriers in the floating body storage device to write first data according to a current flowing from the source line to the bit line; And And a discharge step of discharging a carrier activated in the floating body storage device according to a discharge current flowing from the bit line to the source line. The method of claim 1, wherein the data holding step A first negative voltage for data retention is applied to the word line, a first voltage for precharging is applied to the source line, and a second voltage for precharging is applied to the bit line. Method of driving 1-transistor type DRAM. The method of claim 2, wherein the second voltage has a level higher than that of the first voltage. The method of claim 2, wherein the first negative voltage has a lower level than the first voltage. The method of claim 1, wherein storing the data Applying a cell activation voltage to the word line, applying a first voltage to the source line, and applying a second negative voltage to the bit line; And And a first negative voltage is applied to the word line, the first voltage is applied to the source line, and the second negative voltage is applied to the bit line. How to drive DRAM. 6. The method of claim 5, wherein the first voltage has a higher level than the second negative voltage. 6. The method of claim 5, wherein the second negative voltage has a higher level than the first negative voltage. The method of claim 1, wherein the first data is data “0”. The method of claim 1, wherein the discharge step A first negative voltage is applied to the word line, a first voltage is applied to the source line, and a second voltage is applied to the bit line. 10. The method of claim 9, wherein the second voltage has a higher level than the first voltage. 10. The method of claim 9, wherein the first negative voltage has a lower level than the first voltage. The method of claim 1, further comprising maintaining the first data stored in the floating body storage element after the discharge step. A data holding step of holding data stored in a floating body storage element connected between the bit line and the source line and controlled by the word line; A data storage step of generating hot carriers in the floating body storage element and writing first data according to a current flowing from the bit line to the source line; And And maintaining said first data stored in said floating body storage element. The method of claim 13, wherein the data holding step and the first data holding step are performed. A first negative voltage is applied to the word line, a first voltage is applied to the source line, and a second voltage is applied to the bit line. 15. The method of claim 14, wherein the second voltage has a higher level than the first voltage. 15. The method of claim 14, wherein the first negative voltage has a lower level than the first voltage. The method of claim 13, wherein the data storage step Applying a high voltage to the word line, applying a second negative voltage to the source line, and applying a second voltage to the bit line; And And a first negative voltage is applied to the word line, the second negative voltage is applied to the source line, and the second voltage is applied to the bit line. How to drive DRAM. 18. The method of claim 17, wherein the second voltage has a higher level than the second negative voltage. 18. The method of claim 17, wherein the second negative voltage has a higher level than the first negative voltage. 14. The method of claim 13, wherein the first data is data " 1. " A method of driving a 1-transistor type DRAM using a floating body storage element connected between a bit line and a source line and controlled by a word line, Maintaining a data stored in the floating body storage device by applying a negative voltage to the word line, applying a first voltage to the source line, and applying a second voltage to the bit line; Reading data according to a sensing current flowing from the bit line to the source line by applying a read voltage to the word line; And The negative voltage on the word line  And applying the data to maintain the data. 22. The method of claim 21, wherein the second voltage has a higher level than the first voltage. 22. The method of claim 21, wherein the negative voltage has a lower level than the first voltage.

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