KR100861187B1 - One transistor type dram - Google Patents

Abstract

A one-transistor type DRAM is provided to increase efficiency of a sense amplifier by generating a reference voltage and a clamp voltage reflecting the characteristics of a main cell. According to a one-transistor type DRAM using a floating body storage device controlled by a word line as being connected between a bit line and a source line, a plurality of source lines and word lines are arranged in a row direction. A plurality of bit lines are arranged in a column direction. A plurality of clamp bit lines and reference bit lines are arranged in a column direction. A cell array(30) includes the floating body storage device, and is formed on a region where the source line, the word line and the bit line intersect with each other. A clamp cell array(20) includes the floating body storage device, and is formed on a region where the source line, the word line and the reference bit line intersect with each other. A reference cell array includes the floating body storage device, and is formed on a region where the source line, the word line and the reference bit line intersect with each other. A sense amplifier(S/A) and a write driving part(W/D) are connected to the bit line, and are applied with a clamp voltage and a reference voltage.

Description

One-transistor DRAM

The present invention relates to a 1-transistor type DRAM, which generates a clamp voltage and a reference voltage in a 1-transistor type DRAM using a floating body storage device to improve sensing efficiency of a sense amplifier. It's a technology that makes it possible.

In general, semiconductor devices such as DRAM are integrated on a silicon wafer. However, silicon wafers used in semiconductor devices are not used for the operation of the device but only a limited thickness of several micrometers from the surface for device operation. As a result, the remaining silicon wafers, except for those required for the operation of the device, increase power consumption and reduce driving speeds.

Accordingly, there is a need for a silicon on insulator (SOI) wafer formed by forming a silicon single crystal layer having a thickness of several μm through an insulating layer on a silicon substrate. The semiconductor device integrated on the SOI wafer can be speeded up by the small junction capacity compared to the semiconductor device integrated on the conventional silicon wafer, and has the advantages of speeding up and voltage reduction due to the low voltage due to the low threshold voltage.

However, if the reference voltage is not effectively controlled in the semiconductor device integrated in the SOI wafer, the sensing efficiency of the sense amplifier is reduced. Accordingly, there is a problem that the data sensing margin and yield of the entire chip is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems. In the 1-transistor type DRAM using a floating body storage device, a clamp voltage and a reference voltage are generated to reflect the characteristics of the main cell. The purpose is to increase the efficiency.

In addition, an object of the present invention is to improve the reliability of the cell by applying a non-destructive read out (NDRO) method to the 1-transistor DRAM so that the data of the cell is not destroyed during the read operation.

In addition, an object of the present invention is to implement a 1-transistor type DRAM to significantly reduce the cell size.

In the 1-transistor type DRAM of the present invention for achieving the above object, in the 1-transistor type DRAM using a floating body storage element connected between the bit line and the source line controlled by the word line, A plurality of source lines and word lines arranged in a row direction; A plurality of bit lines arranged in a column direction; A plurality of clamp bit lines and reference bit lines arranged in a column direction; A cell array including a floating body storage element, each cell array formed in an area where a source line, a word line, and a bit line cross each other; A clamp cell array including a floating body storage element, said clamp cell array formed in an area where a source line, a word line, and a clamp bit line cross each other; A reference cell array including a floating body storage element, the reference cell array formed in an area where a source line, a word line, and a reference bit line cross each other; And a sense amplifier and a write driver connected to the bit lines, respectively, to which the clamp voltage and the reference voltage are applied.

The present invention provides the following effects.

First, in a 1-transistor type DRAM using a floating body storage element, a clamp voltage and a reference voltage reflecting characteristics of a main cell may be generated to increase the efficiency of a sense amplifier.

Second, the present invention applies a non-destructive read out (NDRO) method to a 1-transistor DRAM to prevent cell data from being destroyed during a read operation, thereby improving cell reliability.

Third, the present invention implements a 1-transistor type DRAM to significantly reduce the cell size.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1 is a cross-sectional view illustrating a unit cell of a 1-transistor DRAM according to the present invention.

The silicon on insulator (SOI) wafer 10 has a stacked structure of a silicon substrate 1, a buried oxide layer 2, and a silicon layer 3. An isolation layer 11 defining an active region in the silicon layer 3 of the SOI wafer 10 is formed in contact with the buried oxide film 2.

The gate 12 is formed on the active region of the silicon layer 3. In addition, source / drain regions 13a and 13b are formed in the silicon layer 3 on both sides of the gate 12 to contact the buried oxide film 2.

In the DRAM cell implemented in the SOI wafer 10, data is stored by trapping holes and electrons in a floating body 15 corresponding to a channel region under the gate 12. .

For example, as shown in FIG. 2A, the data “1” store state may be understood as a state where there are many holes in the floating body 15. As shown in FIG. 2B, the data “0” storage state may be understood as a state in which the floating body 15 has few holes or a lot of electrons.

Figure 3 is a waveform diagram showing the characteristics of the cell lead current of the 1-transistor DRAM according to the present invention.

3 shows a cell read when the cell gate voltage is set to 0.2V for the DRAM cell implemented in the SOI wafer 10, and the cell gate voltage is sweeped while the cell source voltage is set to ground GND. A graph showing the current.

That is, when the word line read voltage is applied to the word line WL, the read current flows from the bit line BL toward the source line SL. At this time, if the amount of sensing current flowing is larger than the reference current, data "1" is read, and if it is lower than the reference current, data "0" is read.

As shown, the 1-transistor cell in the read state flows a larger amount of sensing current when in the data "1" storage state than in the data "0" storage state. That is, the read current is largest when the data "1" is stored, and the read current is smallest when the data "0". The reference current REF has a read current value corresponding to an intermediate value between the data "1" storage state and the data "0" storage state.

4A is a circuit diagram illustrating a data read method of a 1-transistor DRAM according to the present invention.

In the 1-transistor DRAM of the present invention, the source line SL and the bit line BL are connected to the source 13a and the drain 13b of the floating body transistor FBT, respectively, and the word line WL is connected to the gate 12.

4B is a timing diagram for describing the operation of FIG. 4A.

In the 1-transistor type DRAM cell of the present invention, the timing for reading data is divided into t0 to t2 sections. Here, the t0 and t2 sections are hold sections that hold data. The t1 section is a section for performing data read.

First, the word line WL maintains the ground GND level in the t0 period, that is, the first hold period. The source line SL and the bit line BL maintain the precharge voltage Vpre level. Accordingly, the data is maintained in the floating body 15 in the t0 section.

Thereafter, in the period t1, the voltage of the word line WL transitions to the word line sensing voltage Vwlsense level to read data stored in the cell. At this time, the source line SL transitions to the source line sensing voltage Vslsense level, and the bit line BL maintains the precharge voltage Vpre level. Accordingly, the sensing current Icellse for sensing the sensing current flows from the bit line BL toward the source line SL.

That is, the cell data is read by applying the drain source voltage Vds for sensing the sensing current Icellse between the bit line BL and the source line SL.

Subsequently, in the t2 period, that is, the second hold period, the word line WL transitions to the ground voltage GND level. The source line SL transitions to the precharge voltage Vpre level, and the bit line BL maintains the precharge voltage Vpre level.

In an embodiment of the present invention, the word line sensing voltage Vwlsense has a level higher than the ground voltage GND, and the source line sensing voltage Vslsense preferably has a level lower than the precharge voltage Vpre and higher than the ground voltage GND.

5 is a first embodiment of a one-transistor DRAM according to the present invention.

The present invention provides a clamp and reference cell array 20, a cell array 30, a reference offset current adjuster 40, a clamp voltage generator 50, a reference voltage generator ( 60) and sense amplifier S / A and write driver W / D.

In the clamp and reference cell array 20, a plurality of source lines SL0 to SL2 and a plurality of word lines WL0 to WL3 are arranged in a row direction. Then, the clamp bit lines CBL0, CBL1 and the reference bit line RBL are arranged in the column direction. The clamp and reference cell array 20 may implement the clamp cell CC and the reference cell RC reflecting the characteristics of the main cell to generate the clamp voltage and the reference voltage, thereby increasing the efficiency of the sense amplifier.

In the clamp and reference cell array 20, each clamp cell CC1, CC2 is connected between the source line SL0 and the source line SL1 so that the common drain terminal shares the clamp bit line CBL0. In addition, the gate terminals of the clamp cells CC1 and CC2 are connected to the word lines WL0 and WL1, respectively. Clamp cells CC1 and CC2 disposed up and down are connected to source lines SL0 and SL1 having different source terminals.

The cells included in the clamp and the reference cell array 20 all store data "0". Accordingly, the same current as the cell data "0" flows through the clamp bit lines CBL0 and CBL1 and the reference bit line RBL.

Each of the reference cells RC1 and RC2 is connected between the source line SL0 and the source line SL1 so that the common drain terminal shares the reference bit line RBL. The gate terminals of the reference cells RC1 and RC2 are connected to the word lines WL0 and WL1, respectively. The reference cells RC1 and RC2 disposed up and down are connected to source lines SL0 and SL1 having different source terminals.

In the cell array 30, a plurality of source lines SL0 to SL2 and a plurality of word lines WL0 to WL3 are arranged in the row direction. A plurality of bit lines BL0 and BL1 are arranged in the column direction.

Each cell C1, C2 in the cell array 30 is connected between the source line SL0 and the source line SL1 so that the common drain terminal shares the bit line BL0. The gate terminals of the cells C1 and C2 are connected to the word lines WL0 and WL1, respectively. The cells C1 and C2 disposed up and down are connected to source lines SL0 and SL1 having different source terminals.

Here, a source line sensing voltage Vslsense, which is a sensing bias voltage for sensing a sensing current of a cell, is applied between the bit line BL and the source line SL. Accordingly, the cell sensing current Icell flows according to the storage state of the cell data.

The reference offset current adjuster 40 is connected to the reference bit line RBL to adjust the reference offset current Iref_offset flowing through the reference bit line RBL.

The clamp voltage generation unit 50 generates the clamp voltage Vclmp voltage by controlling the clamp current Iclmp shared by the clamp bit lines CBL0 and CBL1 and flowing through the clamp bit lines CBL0 and CBL1.

The reference voltage generator 60 is connected to the reference bit line RBL to apply the clamp voltage Vclmp, and generates a reference voltage Nref by controlling the reference current Iref flowing through the reference bit line RBL.

Each of the bit lines BL0 and BL1 is connected to the sense amplifier S / A and the write driver W / D. The sense amplifiers S / A and the write driver W / D are respectively connected to the bit lines BL0 and BL1 in a one-to-one correspondence. Here, the reference voltage Nref and the clamp voltage Vclmp for determining the sensing voltage are applied to the sense amplifier S / A and the write driver W / D to control the cell current Icell.

The sense amplifier S / A senses cell data to distinguish data "1" from data "0". The write driver W / D supplies a driving voltage corresponding to the write data to the bit line BL when writing data to the cell.

6 is a second embodiment of a one-transistor DRAM according to the present invention.

The present invention provides a clamp and reference cell array 60, a cell array 70, a reference offset current adjuster 80, a clamp voltage generator 90, a reference voltage generator 100 ) And sense amplifier S / A and write driver W / D.

In the clamp and reference cell array 60, a plurality of source lines SL0 to SL3 and a plurality of word lines WL0 to WL5 are arranged in a row direction. Then, the clamp bit lines CBL0, CBL1 and the reference bit line RBL are arranged in the column direction.

In the clamp and reference cell array 60, each clamp cell CC1, CC2 is connected between the source line SL0 and the source line SL1 so that the common drain terminal shares the clamp bit line CBL0. In addition, the gate terminals of the clamp cells CC1 and CC2 are connected to the word lines WL0 and WL1, respectively. Clamp cells CC1 and CC2 disposed up and down are connected to source lines SL0 and SL1 having different source terminals.

Each of the reference cells RC1 and RC2 is connected between the source line SL0 and the source line SL1 so that the common drain terminal shares the reference bit line RBL. The gate terminals of the reference cells RC1 and RC2 are connected to the word lines WL0 and WL1, respectively. The reference cells RC1 and RC2 disposed up and down are connected to source lines SL0 and SL1 having different source terminals.

The cells included in the clamp and the reference cell array 60 all store data "0". Accordingly, the same current as the cell data "0" flows through the clamp bit lines CBL0 and CBL1 and the reference bit line RBL.

In the cell array 70, a plurality of source lines SL0 to SL3 and a plurality of word lines WL0 to WL5 are arranged in the row direction. A plurality of bit lines BL0 and BL1 are arranged in the column direction.

Each cell C1, C2 in the cell array 70 is connected between the source line SL0 and the source line SL1 so that the common drain terminal shares the bit line BL0. The gate terminals of the cells C1 and C2 are connected to the word lines WL0 and WL1, respectively. The cells C1 and C2 disposed up and down are connected to source lines SL0 and SL1 having different source terminals.

Here, a source line sensing voltage Vslsense, which is a sensing bias voltage for sensing a sensing current of a cell, is applied between the bit line BL and the source line SL. Accordingly, the cell sensing current Icell flows according to the storage state of the cell data.

The reference offset current adjuster 80 is connected to the reference bit line RBL to adjust the reference offset current Iref_offset flowing through the reference bit line RBL.

The clamp voltage generation unit 90 generates the clamp voltage Vclmp by controlling the clamp current Iclmp flowing through the clamp bit lines CBL0 and CBL1 and shared by the clamp bit lines CBL0 and CBL1.

The reference voltage generator 100 is connected to the reference bit line RBL to apply the clamp voltage Vclmp, and generates a reference voltage Nref by controlling the reference current Iref flowing through the reference bit line RBL.

A sense amplifier S / A and a write driver W / D are connected to each of the bit lines BL0 and BL1. The sense amplifiers S / A and the write driver W / D are respectively connected to the bit lines BL0 and BL1 in a one-to-one correspondence. Here, the reference voltage Nref and the clamp voltage Vclmp for determining the sensing voltage are applied to the sense amplifier S / A and the write driver W / D to control the cell current Icell.

The sense amplifier S / A senses cell data to distinguish data "1" from data "0". The write driver W / D supplies a driving voltage corresponding to the write data to the bit line BL when writing data to the cell.

The clamp reference cell array 60 of the present invention having such a configuration includes a plurality of clamp cell groups CCG1 and CCG2 connected to the clamp bit line CBL0, and a plurality of clamp cell groups CCG3 and CCG4 connected to the clamp bit line CBL1. The clamp reference cell array 60 includes reference cell groups RCG1 and RCG2 connected to the reference bit line RBL. The cell array 70 includes a plurality of cell groups CG1 and CG2 connected to the bit line BL.

Here, the plurality of clamp cell groups CCG1 and CCG2 connected to the clamp bit line CBL0 are arranged one by one in the row and column directions. That is, the left and right zigzag patterns are arranged based on the clamp bit line CBL0.

The plurality of clamp cell groups CCG3 and CCG4 connected to the clamp bit line CBL1 are arranged one by one in the row and column directions. That is, the left and right zigzag patterns are arranged based on the clamp bit line CBL1.

In addition, the reference cell groups RCG1 and RCG2 connected to the reference bit line RBL are arranged one by one in the row and column directions. That is, the left and right zigzag patterns are arranged based on the reference bit line RBL. In addition, the plurality of cell groups CG1 and CG2 connected to the bit line BL are arranged one by one in the row and column directions.

In addition, two clamp cell groups CCG1 and CCG2 disposed up and down share one source line SL1. The plurality of clamp cell groups CCG1 and CCG3, the reference cell group RCG1 and the cell group CG1 arranged in the same row line share one source line SL1.

Of the plurality of clamp cell groups CCG2 and CCG3 arranged in the same column line, the clamp cell groups CCG2 and CCG3 arranged up and down adjacent to the source line SL1 are connected to different clamp bit lines CBL0 or clamp bit lines CBL1, respectively. . That is, the clamp cell group CCG3 disposed above the source line SL1 is connected to the clamp bit line CBL1, and the clamp cell group CCG2 disposed below the source line SL1 is connected to the bit line CBL0.

When a plurality of cells arranged above and below share the same bit line If a bias voltage is applied to the bit line BL while sharing the source line SL1 in the write operation mode, the same applies to the floating body cells arranged above and below. Voltage is applied. Accordingly, the same bias voltage is applied to both the selected cell and the unselected cell, thereby causing an operation error in the unselected cell.

Accordingly, the present invention allows the cell groups CG3 and CG2 disposed above and below to be connected to different clamp bit lines CBL1 and CBL0, respectively. Therefore, the bias voltage is applied only to the selected cell, and the bias voltage from the bit line is not applied to the unselected cell, thereby preventing an operation error of the cell.

Here, clamp cell group CCG5 is not substantially connected to clamp bitline CBL, but is implemented in a cell array to maintain cell continuity on a process. Accordingly, the bias condition applied to each cell can be changed by changing the arrangement of the cell groups as shown in FIG. 6.

7 is a waveform diagram illustrating a reference current of the 1-transistor DRAM according to the present invention.

When the voltage of the word line WL transitions to the word line sensing voltage Vwlsense level in the sensing period t1 of FIG. 4B, the reference current Iref_cell equal to the cell data “0” flows in the reference cell RC of the clamp reference cell array 20.

In addition, the reference offset current adjuster 40 generates an additional current component for generating a reference current Iref corresponding to an intermediate value between the cell data “1” and the cell data “0”.

This additional current component is defined as the reference offset current Iref_offset. Therefore, the total reference current Iref is the sum of the reference current Iref_cell and the reference offset current Iref_offset.

FIG. 8 is a detailed circuit diagram of the reference offset current adjusters 40 and 80 of FIGS. 5 and 6. In the present invention, the configuration of the reference offset current adjuster 40 will be described in the embodiment.

The reference offset current adjuster 40 includes an offset current control element connected between the reference bit line RBL and the ground (GND) voltage terminal. The offset current control element adjusts the flow of the reference offset current Iref_offset flowing from the reference voltage generator 60 to the ground GND through the reference bit line RBL.

In the present invention, the offset current control element is constituted by the resistor R in the embodiment. The configuration of the offset current control element is not limited to this, but may be made of not only the resistor R but also a MOS element or any element whose resistance value is adjusted.

9 is a detailed circuit diagram of the clamp voltage generators 50 and 90 of FIGS. 5 and 6. In the present invention, the configuration of the clamp voltage generator 50 will be described in the embodiment.

The clamp voltage generator 50 includes a reference bias unit 51, a clamp voltage adjuster 52, and a clamp voltage output unit 53.

Here, the reference bias unit 51 includes a PMOS transistor P1 and an NMOS transistor N1. The PMOS transistor P1 is connected between the supply voltage VDD terminal and the NMOS transistor N1 to receive the clamp enable signal Clmp_en through the gate terminal. In addition, the NMOS transistor N1 is connected between the PMOS transistor P1 and the clamp bit line CBL0 so that the power supply voltage VDD is applied through the gate terminal.

The clamp voltage adjusting unit 52 includes the amplifier A and outputs the clamp voltage control signal Vclmp_con. The amplifier A has a negative terminal connected to the clamp bit line CBL0 to which the clamp reference signal Cref1 is applied. In the amplifier A, a positive (+) terminal is connected to the clamp bit line CBL1 to apply the clamp reference signal Cref2.

The clamp voltage output unit 53 includes PMOS transistors P2 to P4 and NMOS transistors N2 and N3. The PMOS transistor P2 is connected between the power supply voltage terminal and the PMOS transistor P3 so that the clamp enable signal Clmp_en is applied through the gate terminal. The PMOS transistor P3 is connected between the PMOS transistor P2 and the gate terminal of the NMOS transistor N2 so that the clamp voltage control signal Vclmp_con is applied through the gate terminal.

The PMOS transistor P4 is connected between the supply voltage VDD terminal and the NMOS transistor N2 to receive the clamp enable signal Clmp_en through the gate terminal. The NMOS transistor N2 is connected between the PMOS transistor P4 and the clamp bit line CBL1 so that the gate terminal is connected to the clamp voltage Vclmp terminal. The NMOS transistor N3 is connected between the clamp voltage Vclmp terminal and the ground voltage terminal, and the clamp enable signal Clmp_en is applied through the gate terminal.

Looking at the operation of the clamp voltage generation unit 50 having such a configuration as follows.

The reference bias section 51 is a circuit configuration for generating a reference voltage for generating the clamp voltage Vclmp. The reference bias unit 51 sets the load value such that the current value of the clamp reference signal Cref1 flowing through the clamp bit line CBL0 is constant.

Here, the activation condition of the clamp bias section 51 is adjusted by the clamp enable signal Clmp_en. The constant target current value is determined by the NMOS transistor N1.

The clamp voltage adjusting unit 52 is an amplifier circuit that receives the clamp reference signal Cref1 and adjusts the clamp reference signal Cref2 to be determined. That is, the amplifier A adjusts the clamp reference signal Cref2 according to the clamp reference signal Cref1 and outputs the clamp voltage control signal Vclmp_con.

The clamp voltage output section 53 is a circuit configuration for controlling the output of the clamp voltage Vclmp. The activation condition of the clamp voltage output section 53 is adjusted by the clamp enable signal Clmp_en.

When the clamp enable signal Clmp_en is deactivated to a high level, the NMOS transistor N3 is turned on, causing the clamp voltage Vclmp to maintain the ground voltage level. On the other hand, when the clamp enable signal Clmp_en is activated at a low level, the PMOS transistors P1, P2, and P4 are activated.

Accordingly, the PMOS transistor P3 is adjusted according to the clamp voltage control signal Vclmp_con to control the clamp voltage Vclmp. The NMOS transistor N2 is controlled according to the clamp voltage Vclmp to determine the voltage of the clamp reference signal Cref2.

In addition, the clamp reference signal Cref2 is input to the positive (+) terminal of the amplifier A to adjust the clamp voltage Vclmp. Accordingly, the clamp reference signals Cref1 and Cref2 always maintain a constant offset voltage.

An operation process of the clamp voltage generator 50 having such a configuration will be described below with reference to the timing diagram of FIG. 10.

That is, in the standby state, the clamp enable signal Clmp_en remains in an inactive state at a high level. Accordingly, the clamp reference signals Cref1 and Cref2, the clamp voltage control signal Vclmp_con and the clamp voltage Vclmp maintain the low level.

On the other hand, when the clamp enable signal Clmp_en is activated to a low level, the PMOS transistor P1 is turned on. As a result, the voltage of the clamp reference signal Cref1 rises to a constant bias voltage level.

Then, the voltage of the clamp reference signal Cref2 rises after a predetermined time delay, so that the clamp voltage control signal Vclmp_con becomes a low level. According to the clamp voltage control signal Vclmp_con, the PMOS transistor P3 is turned on to raise the level of the clamp voltage Vclmp.

Then, when the clamp voltage Vclmp rises, the clamp reference signal Cref2 starts to rise. When the target offset voltage reaches the voltage difference between the clamp reference signals Cref1 and Cref2, the voltage of the clamp voltage control signal Vclmp_con rises to a high level. As a result, the level of the clamp voltage Vclmp no longer rises.

FIG. 11 is a detailed circuit diagram of the current sense amplifier S / A of FIGS. 5 and 6.

The sense amplifier S / A includes an equalizing unit 110, an amplifier 120, a pull-up unit 130, an amplifier 140, an amplification activation controller 150, a current sensing rod unit 160, and the like. And a bit line voltage bias controller 170.

Here, the equalizing unit 110 includes PMOS transistors P5 to P7. The PMOS transistor P5 is connected between the supply voltage VDD supply stage and the output terminal OUT. The PMOS transistor P6 is connected between the supply voltage VDD terminal and the output terminal / OUT. PMOS transistor P7 is connected between outputs OUT and / OUT. The sense amplifier enable signal SEN is applied to the PMOS transistors P5 to P7 through the common gate terminal.

The amplifier 120 includes PMOS transistors P8 and P9 and NMOS transistors N4 and N5. PMOS transistors P8 and P9 and NMOS transistors N4 and N5 are cross coupled.

The pull-up unit 130 includes PMOS transistors P10 to P12. Here, the PMOS transistor P10 is connected between the supply voltage VDD terminal and the node Nsabl. The PMOS transistor P11 is connected between the node Nsabl and the node Nsaref. The PMOS transistor P12 is connected between the supply voltage VDD terminal and the node Nsaref. The PMOS transistors P10 to P12 receive a sense amplifier enable signal SEN through a common gate terminal.

The amplifier 140 includes NMOS transistors N6 and N7. NMOS transistor N6 is connected between node Nsabl and NMOS transistor N8 so that the gate terminal is connected to node Nbl. The NMOS transistor N7 is connected between the node Nsaref and the NMOS transistor N8 so that the reference voltage Nref is applied through the gate terminal.

The amplification activation control unit 150 is connected between the amplifying unit 140 and the ground voltage GND applying terminal to receive the sense amplifier enable signal SEN through the gate terminal.

The current sensing rod unit 160 includes a PMOS transistor P13. Here, the PMOS transistor P13 is connected between the power supply voltage VDD applying terminal and the node Nbl so that the load voltage Vload is applied through the gate terminal.

The bit line voltage bias controller 170 includes an NMOS transistor N9. Here, the NMOS transistor N9 is connected between the node Nbl and the bit line BL so that the clamp voltage Vclmp is applied through the gate terminal.

An operation process of the sense amplifier S / A having such a configuration will be described below with reference to the waveform diagram of FIG. 12.

When the clamp voltage Vclmp rises, the NMOS transistor N9 is turned on to transfer the bit line current of the main cell to the node Nbl. Here, the gate voltage of the NMOS transistor N9 is controlled by the clamp voltage Vclmp.

The current sensing load unit 160 includes a PMOS transistor P13 controlled by the load voltage Vload. The current of the bit line BL is converted into the sensing voltage value at the node Nbl by the load value of the PMOS transistor P13.

The amplification activation control unit 150 is controlled by the sense amplifier enable signal SEN. The amplifiers 120 and 140 are activated according to the state of the amplification activation controller 150. Here, the amplifier 140 amplifies the voltage of the node Nbl and the reference voltage Nref stage by using gains of the NMOS transistors N6 and N7.

Both nodes Nsabl and Nsaref are precharged to a high level during the precharge period according to the operation of the pull-up unit 130. This improves the primary amplification characteristics of the sense amplifier S / A. That is, during the t1 period, both nodes Nsabl and Nsaref have pulled-down voltage values. The voltage amplified by the amplifier 140 is transmitted to the amplifier 120 to improve the amplification characteristics of the secondary amplifier.

The amplifier 120 serves to amplify the gain of the amplifier 140 once again, thereby improving the offset characteristics of the sense amplifier S / A. The equalizing unit 110 precharges the output of the amplifying unit 120 to a high level during the patch charging period.

FIG. 13 is a detailed circuit diagram of the reference voltage generators 60 and 100 of FIGS. 5 and 6. In the present invention, the configuration of the reference voltage generator 60 will be described in the embodiment.

The reference voltage generator 60 includes a current sensing rod 61 and a bit line voltage bias controller 62.

Here, the current sensing load unit 61 includes a PMOS transistor P14 connected between the power supply voltage VDD terminal and the reference voltage Nref terminal to which the load voltage Vload is applied through the gate terminal.

The bit line voltage bias control unit 62 includes an NMOS transistor N10 connected between the reference voltage Nref terminal and the reference bit line RBL to which the clamp voltage Vclmp is applied through the gate terminal.

In the reference voltage generator 60 having such a configuration, the gate voltage of the NMOS transistor N10 is controlled by the clamp voltage Vclmp. The reference current Iref is converted into the reference voltage value at the reference voltage Nref stage by the load value of the PMOS transistor P14.

FIG. 14 is a timing diagram illustrating an operating voltage in the current sense amplifier S / A of FIG. 11.

FIG. 14 is a timing diagram of a current sensing operation of data "1" and data "0" in two read cycles.

When the column select switch CS and the reference column select switch REFCS are activated in the read cycle n, the cell and the reference REF currents start to flow. When the sense amplifier enable signal SEN is activated after a certain time, the voltage at the output terminals OUT and / OUT is amplified. At this time, since the current Icell of the cell is greater than the reference current Iref, the output terminal OUT is high and the output terminal / OUT is output at a low voltage level.

Thereafter, when the column select switch CS and the reference column select switch REFCS are activated in the read cycle n + 1, the cell and the reference REF currents start to flow. When the sense amplifier enable signal SEN is activated after a certain time, the voltage at the output terminals OUT and / OUT is amplified. At this time, since the current Icell of the cell is smaller than the reference current Iref, the output terminal OUT is low and the output terminal / OUT is output at a high voltage level.

1 is a cross-sectional view showing a unit cell of a 1-transistor type DRAM according to the present invention.

2A and 2B show cell data storage states of a 1-transistor DRAM according to the present invention;

Figure 3 is a waveform diagram showing the characteristics of the cell lead current of the 1-transistor DRAM according to the present invention.

4A is a circuit diagram for explaining a method of reading a 1-transistor type DRAM according to the present invention.

4B is a timing diagram for explaining the operation of FIG. 4A.

5 and 6 are circuit diagrams of a 1-transistor type DRAM according to the present invention.

7 is a waveform diagram illustrating a reference current of a 1-transistor DRAM according to the present invention.

FIG. 8 is a detailed circuit diagram of the reference offset current adjuster of FIGS. 5 and 6.

9 is a detailed circuit diagram of the clamp voltage generator of FIGS. 5 and 6.

10 is an operation timing diagram relating to the clamp voltage generator of FIG. 9;

FIG. 11 is a detailed circuit diagram of the current sense amplifier of FIGS. 5 and 6.

12 is an operational waveform diagram of a primary and secondary amplifier stage in the current sense amplifier of FIG.

FIG. 13 is a detailed circuit diagram of the reference voltage generator of FIGS. 5 and 6.

FIG. 14 is a timing diagram for describing an operating voltage in the current sense amplifier of FIG. 11.

Claims (23)

A 1-transistor type DRAM using a floating body storage element connected between a bit line and a source line and controlled by a word line, A plurality of source lines and word lines arranged in a row direction; A plurality of bit lines arranged in a column direction; A plurality of clamp bit lines and reference bit lines arranged in a column direction; A cell array including the floating body storage element and formed in regions where the source line, the word line, and the bit line cross each other; A clamp cell array including the floating body storage element and formed in an area where the source line, the word line, and the clamp bit line cross each other; A reference cell array including the floating body storage element and formed in an area where the source line, the word line, and the reference bit line cross each other; And And a sense amplifier and a light driver connected to the bit lines, respectively, to which a clamp voltage and a reference voltage are applied. The 1-transistor DRAM according to claim 1, wherein said clamp and reference cell array stores data " 0 ". The first and second cell arrays of claim 1, wherein the cell array is connected between a first source line and a second source line, and a common drain terminal is connected to the bit line, and each gate terminal is connected to a different word line. 1-transistor type DRAM comprising two cells. The method of claim 3, wherein the clamp and the reference cell array is First and second clamp cells connected between the first source line and the second source line, a common drain terminal is connected to the clamp bit line, and respective gate terminals are connected to different word lines; And A first and a second reference cell connected between the first source line and the second source line, a common drain terminal connected to the reference bit line, and each gate terminal connected to a different word line; 1-transistor DRAM. The method of claim 1, wherein the cell array A plurality of cell groups connected to the bit line; And a first group of the plurality of cell groups is connected to a first bit line, and a second group of the plurality of cell groups is connected to a second bit line. 6. The 1-transistor DRAM according to claim 5, wherein the first group and the second group are alternately arranged in the row and column directions. The method of claim 5, wherein the clamp and the reference cell array A plurality of clamp cell groups connected to the clamp bit lines; And a first group of the plurality of clamp cell groups is connected to a first clamp bit line, and a second group of the plurality of clamp cell groups is connected to a second clamp bit line. The method of claim 5, wherein the clamp and the reference cell array And a plurality of reference cell groups connected to the reference bit line. The 1-transistor DRAM according to claim 1, wherein the sense amplifier and the write driver are connected in one-to-one correspondence with the bit line. The method of claim 1, A reference offset current adjuster configured to adjust the offset current of the reference bit line; A clamp voltage generator connected to the clamp bit line to generate the clamp voltage; And And a reference voltage generator connected to the reference bit line to generate the reference voltage. 12. The DRAM of claim 10, wherein the current flowing through the reference bit line is a sum of a reference current of the cell and the offset current. 12. The DRAM of claim 10, wherein the reference offset current adjuster includes an offset current control element connected between the reference bit line and the ground voltage terminal to adjust an offset current. The 1-transistor DRAM according to claim 12, wherein the offset current control element is a resistance element. The method of claim 10, wherein the clamp voltage generation unit A reference bias unit for supplying a bias voltage to the clamp bit line; A clamp voltage adjusting unit configured to output a clamp voltage control signal for adjusting the clamp voltage in response to a voltage value of the clamp bit line; And And a clamp voltage output unit configured to output the clamp voltage according to the clamp voltage control signal. The method of claim 14, wherein the reference bias unit A first PMOS transistor for selectively supplying a power supply voltage according to the clamp enable signal; And And a first NMOS transistor connected between the first PMOS transistor and the first clamp bit line to receive a power supply voltage through a gate terminal. The method of claim 14, wherein the clamp voltage adjustment unit And an amplifier for comparing and amplifying the output of the first clamp bit line and the output of the second clamp bit line to output the clamp voltage control signal. The method of claim 14, wherein the clamp voltage output unit And controlling the level of the clamp voltage according to the clamp voltage control signal when the clamp enable signal is activated, and pulling down and outputting the clamp voltage when the clamp enable signal is inactivated. The method of claim 17, wherein the clamp voltage output unit First and second transistors whose activation states are controlled according to the clamp enable signal; A third transistor for controlling the level of the clamp voltage according to the clamp voltage control signal; A fourth transistor for controlling the voltage of the second clamp bit line according to the clamp voltage; And And a fifth transistor configured to pull down the clamp voltage when the clamp voltage control signal is inactivated. The method of claim 10, wherein the reference voltage generator A current sensing rod unit controlling the load of the reference voltage according to a load voltage; And And a bit line voltage bias controller configured to generate a reference voltage by controlling a reference current flowing through the reference bit line according to the clamp voltage. 20. The method of claim 19, wherein the current sensing rod portion And a second PMOS transistor connected between a power supply voltage supply terminal and an output terminal of the reference voltage, to which the load voltage is applied through a gate terminal. 20. The method of claim 19, wherein the bit line voltage bias controller And a second NMOS transistor connected between an output terminal of the reference voltage and the reference bit line to which the clamp voltage is applied through a gate terminal. The method of claim 1, wherein the sense amplifier Amplifying means for amplifying a voltage at an output terminal according to the voltage of the bit line and the reference voltage; An equalizer for precharging the output stage during the precharge period; A pull-up unit which pulls up both nodes of the amplifying means during the precharge period; An amplification activation controller for controlling activation of the amplifying means according to a sense amplifier enable signal; A current sensing rod unit controlling the voltage of the bit line according to a load voltage; And And a bit line voltage bias controller configured to control the current of the bit line according to the clamp voltage. The method of claim 22, wherein the amplifying means A first amplifier configured to amplify the voltage of the bit line and the voltage of the reference voltage terminal; And And a second amplifier configured to amplify the voltage of the first amplifier.

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