JP2000076876A - Non-volatile semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor storage device capable of preventing readout precision from being lowered due to variation of a verification voltage or a readout voltage, and easily realizing readout of a multivalued memory. SOLUTION: A source line voltage generating circuit 30 generates a reference voltage Vref based on a difference in a threshold voltage between an enhancement-type nMOS transistor and a depletion-type nMOS transistor, and further generates based thereon a source line voltage VSL to be supplied to a common source line CSL of a memory cell array 10. A source line voltage switching circuit 20 selects the source line voltage VSL in the case of a page readout so that the ource line voltage VSL is applied to the common source line CSL, while the common source line CSL is held at a ground potential in the other cases. Thus, a verification operation and a readout operation can be performed with the same level of word line voltage, and therefore, a readout error due to variation of the word line voltage at the verify and readout operations is prevented from occurring.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to non-volatile semiconductor memory devices, and more particularly, to write verification and reading of multi-valued memory devices.

[0002]

2. Description of the Related Art Nonvolatile memory transistors include a MONOS type and an MNOS type in addition to a floating gate type (FG type). These nonvolatile memory transistors are provided with a charge storage layer insulated from the surroundings,
When charges are injected into the charge storage layer by any means, the injected charges are accumulated and have a characteristic that they can be held almost permanently. Further, since the threshold voltage of the memory transistor changes according to the amount of charge stored in the charge storage layer, data corresponding to the threshold voltage can be held.

FIG. 4 shows a floating gate type MONO.
It is a simplified sectional view showing the example of composition of the S type and the MNOS type nonvolatile memory transistor. FIG. 1A shows a cross section of a floating gate type nonvolatile memory transistor. In FIG. 4A, reference numeral 1 denotes a semiconductor substrate or well having n-type or p-type conductivity (hereinafter simply referred to as a substrate for convenience), and 2 and 3 denote impurities of a conductivity type opposite to that of the substrate 1 at a high level. Sources and drains are formed in the regions formed by the implantation at the respective concentrations. A gate insulating film 4 made of a dense silicon oxide (SiO ₂ ) film is formed on the surface of the substrate 1 in a region (channel forming region) between the source 2 and the drain 3.

A floating gate 7 made of polysilicon is formed on the surface of the gate insulating film 4, and an interlayer insulating film 6 having good insulating properties is formed on the surface. The interlayer insulating film 6 is composed of, for example, a composite film composed of an ONO film (a silicon oxide film-a silicon nitride film-a silicon oxide film). A control gate (control gate) 5 made of, for example, a polysilicon film having good conductivity is formed on the surface of the interlayer insulating film 6.

[0005] Gate insulating film 4, floating gate 7
The portion composed of the interlayer insulating film 6 is usually called a laminated film, and is denoted by reference numeral 4a in FIG. An insulating film (side wall) 9 made of, for example, silicon oxide is formed on side surfaces of the control gate 5 and the stacked film 4a.

In a floating gate type non-volatile memory transistor, the threshold voltage of the memory transistor changes in accordance with the amount of charge stored in the floating gate 7. Therefore, the threshold value is controlled by controlling the amount of stored charge. The voltage can be set to a predetermined level, and data corresponding to the voltage can be stored.

FIG. 4B shows a cross section of a MONOS type nonvolatile memory transistor. Note that, as compared with the cross section of the floating gate type nonvolatile memory transistor shown in FIG. Here, the configuration of the laminated film 4b will be mainly described. As shown in the figure, on the surface of a region sandwiched between the source 2 and the drain 3 of the MONOS type nonvolatile memory transistor, there is a laminated film 4b and a control gate 5 formed on the surface. The laminated film 4b includes a gate insulating film 4 made of silicon oxide, a nitride film 8a formed on the surface thereof, and a top oxide film 6a formed on the surface of the nitride film 8a. The nitride film 8a is made of, for example, silicon nitride, and the top oxide film 6a is made of, for example, silicon oxide.

In the MONOS type nonvolatile memory transistor thus configured, the nitride film 8a is a layer formed for introducing charge storage means (carrier trap), and corresponds to a charge storage layer. . Of the carrier traps introduced by the formation of the nitride film 8a, those functioning as charge storage means are mainly a bulk trap of the nitride film 8a, the nitride film 8a, and the upper oxide film 6a.
This is a deep carrier trap formed near the interface with.

In the MNOS type nonvolatile memory transistor shown in FIG. 4C, the laminated film 4c is composed of a two-layer insulating film of a lower gate insulating film 4 and an upper nitride film 8b. The nitride film 8b is made of, for example, silicon nitride, and is formed to introduce a carrier trap similarly to the MONOS type memory transistor shown in FIG. The nitride film 8b is formed to be relatively thicker than the nitride film 8a of the MONOS type memory transistor in order to prevent hole injection.

The threshold voltage of the nonvolatile memory transistor shown in FIG. 4 is controlled according to the amount of charge stored in the charge storage layer, and data corresponding to the threshold voltage can be stored. . Therefore, by controlling the amount of accumulated charge and setting the threshold voltage of the memory transistor to a plurality of levels, a multi-valued memory capable of storing two or more bits of data in one memory transistor can be realized. .

By using a plurality of these nonvolatile memory transistors (hereinafter also referred to as memory cells), for example, the memory cells arranged in a matrix, and the memory cells arranged in the same row are arranged in the same source and in the same column. Memory cells are connected to the same bit line to form a nonvolatile memory device. In such a nonvolatile memory device, there is a page read (or serial read) method for simultaneously reading data from a large number of memory cells connected to the same word line. The page referred to here is a memory cell group including a plurality of memory cells connected to one word line.
It has a memory cell of 512 bytes.

In page reading, a large number of memory cells connected to the same word line are read at the same time.
The word line voltage _VWL applied to the selected word line is applied to the control gate of each memory cell. Setting the word line voltage V _WL applied to the selected word line to an intermediate value between the threshold voltage V _th levels corresponding to the respective storage data of the memory cells;
The data stored in each memory cell can be determined by detecting whether or not a current flows through the memory cell.

For example, as shown in FIG. 5A, by setting the threshold voltage of each memory cell to four levels, 2-bit data "00",
Any of "10", "10", and "11" can be stored. For example, at the time of writing when data “00” is stored in a memory cell, the threshold voltage V _th of the selected memory cell is set within a range of 2.8 V to 3.2 V, and data “01” is stored in the memory cell. , The threshold voltage V _th of the selected memory cell is set to 1.
The threshold voltage _Vth of the selected memory cell is set within the range of 0.4 V to 0.8 V at the time of writing when data is set in the range of 6 V to 2.0 V and data "10" is stored in the memory cell. Set. When data "11" is stored in the memory cell, the threshold voltage _Vth of the selected memory cell is set to -2.0 V or less by erasing.

By writing, the threshold voltage _Vth of the memory cell is set to a level corresponding to the write data. At the time of reading, it is possible to set the selected word line to an intermediate level between the four distribution ranges of the threshold voltage of the memory cell, and read the data stored in the memory cell depending on whether or not a current flows through the memory cell. For example, first, a read voltage V _{WL of} 2.4 V is applied to the selected word line, then a read voltage V _{WL of} 1.2 V is applied to the selected word line, and finally, a read voltage V _{WL of} 0 V is applied to the selected word line. By detecting whether or not a current flows through the memory cell at each read voltage V _WL , it is possible to determine in which range the threshold voltage V _th of the memory cell is distributed,
The stored data can be read.

On the other hand, in the verify operation at the time of writing, the verify voltage V _VR applied to the selected word line, that is, the control gate of the write memory cell is at the lowest level in each distribution range of the threshold voltage V _th of the memory cell. And 2.8V, 1.6V and 0.4V respectively. For example, erasing is performed before writing, and the threshold voltage of each memory cell is set to 0 V or less. At the time of writing, a pulse having a predetermined voltage level and time width is applied to the control gate of the selected memory cell a plurality of times via the word line, and after the pulse is applied, a verify voltage V _VR set according to the write data is applied to the word line. Is applied to the control gate of the selected memory cell through the memory cell, and whether or not the threshold voltage has reached a desired level is determined based on whether or not a current flows through the memory cell. When the threshold voltage of the memory cell reaches a desired threshold voltage, the writing ends. By performing writing in this manner, control is performed so that the threshold voltage of each memory cell is distributed within a predetermined voltage range according to write data.

In the case of the above-described multi-valued memory, the verify voltage V _VR is set to be higher than the read voltage by 0.4 V, so that a sufficient interval is maintained between the respective threshold voltage distribution ranges, and each of the verify voltages V _VR is set at the time of read. By setting the read voltage at an intermediate level in the distribution range, data stored in the memory cell can be determined.

[0017]

In the conventional multi-valued memory described above, when a larger number of bits are stored in one memory cell, for example, the threshold voltage of the memory cell is set to 16 different areas. Distribution and 4 accordingly
When bit data is stored, the interval between the distribution regions of the respective threshold voltages becomes narrow, and the voltage difference ΔV between the read voltage V _WL at the time of normal page read and the verify voltage V _{VR at} the time of verify is 0. 0.1 V (FIG. 5B).
For this reason, if a slight error occurs in the voltage generated due to fluctuations in the characteristics of the voltage generating circuit, variations in circuit elements, etc., the normal read voltage _VWL and the verify voltage _VVR become the same level, and correct data reading is performed. There is a disadvantage that it becomes difficult.

FIG. 6 shows an example of the distribution of threshold voltages of nonvolatile memory cells storing 4-bit data. As shown in the figure, when storing 4-bit data, the threshold voltages of the memory cells are programmed so as to be distributed in 16 different regions according to the respective stored data. Each distribution range is narrower than when storing 2-bit data, for example, about 0.1V. Further, for example, an interval of approximately 0.2 V is provided between the distribution ranges. In the case of reading, as shown in FIG. _6A , voltages V _g1 , V _g2 and V _{g3 in} the middle of the distribution range of each threshold voltage.
_Are sequentially applied to the selected word line as the read voltage _VWL , and by detecting the current flowing in the memory cell when each read voltage _VWL is applied, the distribution range of the threshold voltage of the memory cell can be determined. Accordingly, 4-bit data stored in the memory cell can be read.

However, as shown in FIG. 2B, when the generated voltage varies, the verify voltage V _VR
And the read voltage _VWL may be at the same level, and correct reading cannot be performed. For example, the verify voltage V _VR generated at the time of writing is 0.05
As the voltage becomes lower, the distribution range of the threshold voltage of the memory cell is set to a range lower by 0.05 V than usual. At the time of reading, if the read voltage V _WL generated by the variation of the voltage generating circuit becomes 0.05 V higher than usual, if the storage data to be read is “0001”, the read voltage V _WL is set to V _g2. No current must flow through the memory cell, but in this case the voltage V _g2
Already exists in the threshold voltage distribution range of the storage data "0001", a current may flow through the memory cell. Next, the read voltage V _WL is reduced by one step to a voltage V _g3.
In this case, since no current flows through the memory cell, the read data may not be "0001" but may be erroneously determined to be data "0010" corresponding to a further distribution range.

As described above, both the read voltage and the verify voltage at the time of normal page read cause variations,
The interval between each threshold voltage of the memory cell and the read voltage _VWL at the time of normal page reading cannot be secured.
When storing multi-valued data of bits or more, accurate reading has been difficult to achieve.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to avoid a decrease in readout accuracy due to a variation in verifying or readout voltage, and to easily implement a multilevel memory readout. It is to provide a storage device.

[0022]

In order to achieve the above object, a nonvolatile semiconductor memory device of the present invention has a charge storage layer insulated from the surroundings, and a threshold is provided by transferring charges to and from the charge storage layer. A memory cell that controls a value voltage and stores data according to the threshold voltage, and transfers a charge to and from the charge storage layer of the memory cell at the time of programming so that the threshold of the memory cell is increased. After a write operation for changing the value voltage in a predetermined direction, when a predetermined verify voltage is applied to the control gate, verify is performed by detecting the current of the memory cell to determine the threshold voltage level of the memory cell. The above-described writing and verifying are repeated until the threshold voltage of the memory cell reaches a predetermined level corresponding to the write data, A nonvolatile semiconductor memory device which determines storage data of the memory cell by applying a predetermined read voltage to the control gate and detecting the current, wherein the verify gate and the control gate of the memory cell are connected to each other at the time of the verify and read. Source voltage switching means for applying a voltage of the same level, holding the source region of the memory cell at the ground potential during the verify operation, and applying a predetermined source bias voltage to the source region of the memory cell during the read operation; .

The nonvolatile semiconductor memory device of the present invention has a plurality of memory cells whose threshold voltage is controlled in accordance with the amount of charge stored in the charge storage layer, and these memory cells are arranged in a matrix. In contrast, the control gate of each memory cell in the same row is connected to the same word line, a bit line is wired for each memory cell column, and each memory cell in the same column is connected between the bit line and a common source line. A row decoder that has a memory cell array in which cells are connected in series or in parallel and selects one word line specified by an input address signal from the plurality of word lines; Generates a voltage with a predetermined level,
A word line voltage generating circuit for applying the generated voltage to the word line selected by the row decoder; a source line bias voltage generating circuit for generating a source line bias voltage having a predetermined level; And a source line voltage switching circuit for applying the source line bias voltage to the common source line at the time of reading.

In the present invention, preferably, in order to store at least 2 bits of data in each of the memory cells, the threshold voltage of the memory cell is set to one of at least four different voltage regions in accordance with the storage data. And the source line bias voltage generating circuit generates a voltage that is substantially half of a minimum interval between the plurality of different distribution regions, and uses the generated voltage as the source bias voltage. Supply to voltage switching circuit.

In the present invention, preferably, the source line bias voltage generating circuit includes a differential circuit including a first transistor and a second transistor whose gates are kept at a ground potential; The second transistor constituting the differential circuit is connected to a drain of the second transistor, a drain is connected to a power supply voltage, a source is connected to the ground potential via a resistance element, and a connection point between the source and the resistance element Has a third transistor connected to the gate of the second transistor, and has a threshold voltage of the second and first transistors from a connection point between the source of the third transistor and the resistance element. A reference voltage generating circuit that outputs a reference voltage corresponding to the voltage difference; furthermore, the first and second transistors have different conductivity, and the reference voltage is imprinted on a gate. And a differential circuit including a fifth transistor having the same conductivity as the fourth transistor, and a fourth transistor having different conductivity connected in series between the power supply voltage and the ground potential. 6 and a seventh transistor. The gates of the sixth and seventh transistors are connected to the drain of the fourth transistor. The connection point between the drains of the sixth and seventh transistors is connected to the fifth transistor. An inverter configured to be connected to the gate of the transistor; a connection point between the drains of the sixth and seventh transistors configuring the inverter forms an output terminal of the inverter; A source line bias voltage having a level corresponding to the reference voltage is output.

In the present invention, preferably, the second transistor constituting the differential circuit of the reference voltage generating circuit is an enhancement transistor, and the first transistor has a threshold voltage. It is a depression type transistor which is lower than the threshold voltage of the enhancement type transistor.

Further, according to the present invention, in the source line voltage switching circuit, one of the impurity regions forming the source and the drain is connected to the output terminal of the inverter, the other is connected to the common source line, and the gate is connected to the common source line. A first switching element composed of a transistor to which a read signal is input, an impurity region forming a source connected to a ground potential, an impurity region forming a drain connected to the common source line, and a gate connected to the readout. A second switching element comprising a transistor to which a logically inverted signal of the signal is applied.

According to the present invention, in a nonvolatile semiconductor memory device composed of nonvolatile memory cells, the same word line voltage is applied to the selected word line at the time of verification after writing and at the time of reading. At the time of verification, the common source line is held at the ground potential. At the time of reading, a source line bias voltage having a predetermined level is applied to the common source line. As a result, the threshold voltage of each memory cell is equivalently increased by the source line bias voltage applied to each source line at the time of reading, so that a word line voltage higher than that at the time of reading is required for normal verification. However, according to the present invention, verification and reading can be realized with the same word line voltage. Note that the source line bias voltage can be set to, for example, about half of the minimum interval between adjacent threshold voltage distribution regions in the case of a multi-valued memory. The word line voltage is controlled to a substantially intermediate level in the distribution range of each threshold voltage, and the occurrence of a read error is suppressed.

[0029]

FIG. 1 is a block diagram showing one embodiment of a nonvolatile semiconductor memory device according to the present invention. As shown, the nonvolatile semiconductor memory device of the present embodiment includes a memory cell array 10, a source line voltage switching circuit 20, and a source line voltage generation circuit 30.
Further, the source line voltage generation circuit 30 includes a reference voltage generation circuit 32 and a voltage setting circuit 34.

The memory cell array 10 includes, for example, a plurality of memory cells, and the source voltage of each memory cell is set to the source line bias voltage set by the source line voltage switching circuit 20. The source line voltage switching circuit 20 is constituted by a changeover switch, selects either the source voltage generated by the source line voltage generation circuit 30 or the ground potential GND, and selects the memory cell array 1
0 is supplied to the common source line. For example, at the time of page reading, the source line voltage V _SL generated by the source line voltage generating circuit 30 is selected and applied to the common source line CSL of the memory cell 10, and at other times, the ground potential GND is selected. It is connected to a common source line CSL of the memory cells 10.

In the source line voltage generating circuit 30, the reference voltage generating circuit 32 is formed of, for example, a band gap reference (Band gap reference) circuit, for example, a reference having a predetermined level set by a threshold voltage of a transistor. A voltage _Vref is generated. Voltage setting circuit 34 receives a reference voltage V _ref generated by the reference voltage generating circuit 32 generates a source line voltage V _SL, is supplied to the source line voltage switching circuit 20 together accordingly, the memory of the memory cell array 10 It has a function of drawing electric charge so that a current flows through the cell.

FIG. 2 is a circuit diagram showing a configuration of each part in the block diagram shown in FIG. Hereinafter, the configuration of the nonvolatile semiconductor memory device of the present embodiment will be described with reference to FIG. As shown, the memory cell array 10 includes, for example, each of the bit lines BL1, BL2,.
This is a so-called NAND type nonvolatile memory cell array configured by providing a plurality of memory cell columns including a plurality of memory cells connected in series between m and a common source line CSL. Here, m is a positive integer. Bit line B
Between L1 and a common source line CSL, n (n is a positive integer) memory cells _{MC 11, MC 12, ...,} MC 1n are connected in series to form memory strings. Between the memory cell MC ₁₁ and the bit line BL1, the bit line selection transistor SB1 is connected, the memory cell M
A source line select transistor SS1 is connected between C _1n and a common source line CSL. Further, other memory cell strings connected between the other bit lines and the common source line CSL have substantially the same configuration. For example, between the bit line BLm and the common source line CSL,
MC _m1 , MC _m2 ,..., MC _mn are connected in series.
A bit line selection transistor SBm is connected between the memory cell MC _m1 and the bit line BLm, and the memory cell MC _mn
And a common source line CSL, a source line select transistor SSm is connected.

In the memory cell array 10, a plurality of memory cells arranged in the same row are connected to the same word line. For example, the memory cells MC ₁₁ , MC ₂₁ ,.
The control gates of the memory cells MC _m-1,1 and MC _m1 are commonly connected to a word line WL1. Therefore, by selecting one of the word lines WL1, WL2, WLn-1, and WLn, the m connected to the word line is selected.
All the memory cells (memory cell groups) are selected.
Further, in the memory cell array 10, since n memory cells arranged in the same column are connected in series between a bit line corresponding to the column and a common source line CSL, the same memory cell is used during verification or reading. The threshold voltage of each memory cell is determined by the bit line, and storage data is read.

Source line CS common to each memory string
L connected to the source line selection transistor S
The gates of S1, SS2,..., SSm-1, and SSm are commonly connected to, for example, a source line selection signal line SSL. Therefore, when a high-level signal, for example, a signal at the power supply voltage V _CC level is applied to the source line selection signal line SSL, the source line selection transistors SS1 and SS1
2,..., SSm−1, SSm are turned on. On the other hand, each memory string and bit lines BL1, BL2,.
, SSm-1 and SSm connected to the bit line selection signal line BSL are connected to the gates of the bit line selection transistors SB1, SB2,. Therefore, when a high-level signal, for example, a signal at the power supply voltage V _CC level is applied to the bit line selection signal line BSL, the bit line selection transistor SB
, SB2,..., SBm-1 and SBm are turned on, whereby all the memory cells of one memory cell group connected to the selected word line can be simultaneously read. realizable.

Although not shown, in the memory cell array 10, a precharge circuit and a sense amplifier are connected to each bit line. Before verification or reading, each bit line is set to a predetermined precharge potential by a precharge circuit. Then, the word line voltage V _WL is applied to the selected word line, and a high level high voltage is applied to the other unselected word lines, so that the unselected memory cells are turned on in each memory string and the selected memory cells The on / off state is determined according to the relationship between the word line voltage _VWL applied to the control gate and the threshold voltage _Vth . For example, when the word line voltage V _WL is higher than the threshold voltage V _th , the selected memory cell turns on. At this time, a current path is formed between the bit line connected to the memory string and the common source line CSL, and the bit line is connected to the common source line CSL via the bit line selection transistor, the memory string, and the source line selection transistor. Electric current flows. Therefore, the potential of the bit line decreases. On the other hand, the word line voltage V _WL
Is lower than the threshold voltage _{Vth of the} memory cell, the selected memory cell is turned off. At this time, no current path is formed between the bit line and the common source line, and no current flows through the memory string. The bit line potential does not decrease and is kept almost at the precharge potential.

[0036] By detecting the change in the bit line potential by the sense amplifier connected to the bit line, to determine the level of the threshold voltage V _th of the selected memory cell, the level of the threshold voltage V _th If determined, the data stored in the selected memory cell can be read.

In the present embodiment, the word line voltage V
Generate _WL and apply it to the selected word line. That is, the verify voltage and the read voltage are the common word line voltage _VWL . However, the verification are held at the ground potential GND to the common source line CSL when verifying, by setting the voltage V _SL of the common source line CSL at a constant level during reading, the selected word line when equivalently read In this case, a read voltage lower by the voltage V _SL than in the case of (1) is applied. For this reason, in the present embodiment, the same voltage is generated and applied to the selected word line at the time of verify and read, so that a read error due to variations in the word line voltage generation circuit can be prevented.

Hereinafter, the configuration of the source line voltage generating circuit 30 will be described. The source line voltage generation circuit 30 includes a reference voltage generation circuit 32 and a voltage setting circuit 34. In the reference voltage generation circuit 32, a differential circuit is constituted by the depletion type nMOS transistor NT1 and the enhancement type nMOS transistor NT2. The gate of the transistor NT1 is grounded. The sources of transistors NT1 and NT2 are current sources IS
1 are connected in common. pMOS transistor PT
1 and PT2 constitute a current mirror, and the current mirror constitutes a load circuit of a differential circuit including transistors NT1 and NT2.

The drain of the nMOS transistor NT3 is connected to the power source voltage V _CC, its gate transistors N
The drain of T2 is connected to the node ND1, and the source is grounded via the resistor R1. From the connection point between the source of the transistor NT3 and the resistance element R1 to the node N
D2 is formed. The reference voltage _Vref is output from the node ND2. Note that the gate of the transistor NT2 forming the differential circuit is connected to the node ND2.

Here, _assuming that the threshold voltage of the depletion type nMOS transistor NT1 is V _thD and the threshold voltage of the enhancement type nMOS transistor NT2 is V _thE , the reference voltage V _ref generated by the reference voltage generating circuit 32 Is (V _thE −V _thD ). Less than,
This will be described.

[0041] For example, when the potential of the node ND2 drops due a leakage current smaller than the current I _C which current I _d flowing through the transistor NT2 flows through the transistor NT1. On the other hand, in the current mirror constituted by the transistors PT1 and PT2, the transistor PT2
Is controlled so that almost the same current I _C flows to the drain of the transistor NT1, the connection point between the drains of the transistor PT2 and the transistor NT2, that is, the potential of the node ND1 rises. At this time, the transistor N
Since the gate potential of T3 rises, the current I
_m increases, and the source potential of the transistor NT3, that is, the potential of the node ND2 also increases. When the potential V _ref of the node ND2 is equal to the (V _thE -V _thD) increases, the current I _m not flow to the transistor NT3, the potential V _ref of the node ND2 is stabilized to the level of (V _thE -V _thD) .

As described above, the reference voltage V set by the threshold voltage difference (V _thE −V _thD ) between the enhancement type nMOS transistor NT2 and the depletion type nMOS transistor NT1 forming the differential circuit by the reference voltage generation circuit 32. _ref is supplied.

As shown, the voltage setting circuit 34 includes pMOS transistors PT3 and PT4 forming a differential circuit and a pMOS transistor PT5 forming an inverter.
And an nMOS transistor NT6.
In the voltage setting circuit 34, the nMOS transistors NT4 and NT5 form a current mirror, and form a load circuit of a differential circuit including the transistors PT3 and PT4.

The sources of the transistors PT3 and PT4 are connected to the current source IS2, the reference voltage _Vref is applied to the gate of the transistor PT3, and the output terminal of the inverter consisting of the transistors PT5 and NT6 is connected to the gate of the transistor PT4. I have. Transistor NT forming a current mirror with the drain of transistor PT3
4 are connected to each other, and the connection point forms a node ND3.

Transistor PT5 and transistor NT6
Are connected to each other, and the connection point constitutes an input terminal of the inverter and is connected to the node ND3. The source of the transistor PT5 is connected to the power supply voltage V _CC ,
The drain is connected to the drain of the transistor NT6,
An output terminal of the inverter, that is, a node ND4 is formed by a connection point between the drains. The source of the transistor NT6 is connected to the ground potential GND.

In the voltage setting circuit 34 thus configured, the source line voltage V _SL to be applied to the common source line CSL of the memory cell array 10 is set according to the reference voltage V _ref generated by the reference voltage generating circuit 32. It is generated and output from a node ND4, which is the output terminal of the inverter. Furthermore, while holding the potential of the common source line CSL to the voltage V _SL, draw charge generated by the memory cell current to a node ND4. Hereinafter, the operation of the voltage setting circuit 34 will be described.

The voltage setting circuit 34 supplies a charge from the node ND4 to the common source line CSL of the memory cell array 10 via the source line voltage switching circuit 20 at the start of page reading or the like. It is kept at the source line voltage _VSL . Then, a current flows through the memory cell during reading, so that the common source line CSL
Is drawn into the node ND4 via the source line voltage switching circuit 20.

As shown in FIG. 2, the source line voltage switching circuit 20 is provided with two nMOS transistors SGT1 and SGT2 as switching elements. The source of the transistor SGT1 is connected to a common source line CSL, and the train is an output terminal of a source line voltage generation circuit.
That is, it is connected to the node ND4. Transistor S
The drain of GT2 is connected to a common source line CSL,
The source is grounded. The read signal RD is applied to the gate of the transistor SGT1, and the transistor SGT
The inverted signal / RD of the read signal RD is applied to the second gate.

At the time of page reading, read signal RD
Are held at the high level, and the inverted signal / RD is held at the low level. In response, the transistor SGT1
But on, SGT2 is turned off so that, the source line voltage V _SL is applied to the common source line CSL. At the time other than the page read, the read signal RD is held at the low level,
The inverted signal / RD is held at a high level. In response, the transistor SGT1 is turned off and the SGT2 is turned on, so that the common source line CSL is held at the ground potential GND.

For example, when the potential of the source line CSL, that is, the potential of the node ND4 is lower than the reference voltage _{Vref at the} start of page reading, the transistor P in the differential circuit
Current I _b flowing through T4 is larger than the current I _a flowing through the transistor PT3. In the current mirror, since approximately the same current I _b flows between the drain current of the transistor PT4 to the transistor NT4, the potential of the node ND3 made from the connection point of the drains of the transistors PT3 and NT4 is reduced. At this time, the current _Ip flowing through the transistor PT5 forming the inverter increases,
Voltage V _SL of D4 is controlled in a direction to increase. Node N
When D4 potential V _SL reaches the increased reference voltage V _ref, decreased current I _p of the transistor PT5 is, the potential V _SL of the node ND4 is stabilized to the level of the reference voltage V _ref.

When a memory cell current flows through the common source line CSL during normal page reading, the current flows into the node ND4, the voltage V _SL increases, and the reference voltage V _SL
higher than _ref . In this case, the current flowing through the transistor PT4 I _b current flows through the transistor PT3 I _a
Smaller. Transistor N by current mirror
Control is performed so that the same current _Ib flows in T4. Therefore, the potential of the node ND3 rises, which was the gate voltage rise of the transistor NT6 configuring the inverter in response to increases current I _n flowing in it. As a result, the potential of the node ND4 drops, becomes equal to the reference voltage V _ref, decreases the current I _n of the transistors NT6, node N
The potential of D4 stabilizes at the level of the reference voltage _Vref .

[0052] Thus, the voltage setting circuit 34, via the source line voltage switching circuit 20 during page read, supplies the source line voltage V _SL to the common source line CSL of the memory cell array 10, the memory cell current It draws charge generated to a common source line CSL, to stabilize the voltage V _SL of the common source line CSL at a constant level.

As described above, the source line voltage generation circuit 3
0 indicates enhancement type and depletion type nM
It generates a reference voltage V _ref depending on the difference between the threshold voltage of the OS transistor, for generating a source line voltage V _SL to be supplied to the common source line CSL of the memory cell array 10 in response thereto. The source line voltage switching circuit 20 selects and applies the source line voltage V _SL to the common source line CSL at the time of page reading, and holds the common source line CSL at the ground potential GND at other times. As a result, the potential of the common source line CSL is raised by the source line voltage V _SL at the time of page read, and the threshold voltage of each memory cell is equivalently increased by V _SL. In this case, a voltage of the same level can be generated by the same voltage generation circuit and applied to the selected word line, thereby preventing a read error from occurring due to a variation in the word line voltage.

By setting the threshold voltages of the enhancement type and depletion type nMOS transistors constituting the reference voltage generating circuit, a desired reference voltage _Vref can be generated, and the source line voltage V _SL can be generated accordingly. Can be set to a desired voltage level.
For example, the threshold voltage V _tHD of the depletion type nMOS transistor is set to -0.1 V, the threshold voltage V _thE enhancement type nMOS transistor 0.
By setting to 3V, the reference voltage V _{ref of} 0.4V
Is generated, and the source line voltage V _SL can be set to 0.4 V accordingly.

FIG. 3 is a threshold voltage distribution diagram showing one operation example of the present embodiment in a multilevel memory in which the threshold voltage of a memory cell is set to four levels. FIG.
Are the distribution of the threshold voltage of the memory cell at the time of write verification and the respective voltage values V _g1 and V _{g1 of} the selected word line voltage V _WL .
V _g2 and V _g3 are shown. For example, when writing data “00” to a memory cell, the word line voltage V _WL applied to the selected word line at the time of verification is V _g1 (2.8
V). As a result, the threshold voltage of the memory cell storing the data “00” is controlled so as to be distributed in the range of 2.8V to 3.2V. Similarly, when writing data "01" to the memory cell, applying a voltage V _g2 of 1.6V to the selected word line when the verification. Accordingly, the threshold voltage of the memory cell storing data "01" is distributed in the range of 1.6V to 2.0V.

At the time of normal page read, a read voltage set at an intermediate level in the distribution range of each threshold voltage is applied to the selected word line, and a read current flowing through the memory cell is detected, thereby detecting the memory cell. The distribution range of the threshold voltage is determined, and the stored data is read. In the present embodiment, by applying a predetermined source line voltage V _SL to the common source line CSL of the memory cell array when the page read, it is possible to apply the same level of voltage and a verify operation to the selected word line.

[0057] For example, to set the source line voltage V _SL to 0.4V, when the page read, supplied to the common source line CSL the source line voltage V _SL via a source line voltage switching circuit 20. In this case, first, reading is performed by applying a voltage V _g1 of 2.8 V to the selected word line. At this time, the source line voltage V of 0.4 V is applied to the common source line CSL.
_{Since SL} is applied, the threshold voltage of each memory cell is raised by that amount. For example, data “00”
Threshold voltage of the memory cell storing
The threshold voltage of the memory cell storing data "01" is distributed in a range of 2.0V to 2.4V.

Therefore, when a voltage V _g1 of 2.8 V is applied to the selected word line, the memory cell storing data “00” remains off, and data “01” and “01” other than data “00” are left. Since all the memory cells storing "10" and "11" are turned on, by detecting the current flowing through each memory cell connected to the selected word line,
The stored data “00” can be read from the memory cell storing the data “00”.

Similarly, while holding the common source line CSL at the source line voltage V _SL , the voltages V _g2 , V _g
By applying _g3 , data stored in each memory cell can be read.

As described above, in the nonvolatile semiconductor memory device of the present embodiment, by switching the potential of the common source line CSL of the memory cell array at the time of verify and page read, the same as the selected word line at the time of verify or page read. A word line voltage can be applied, and read errors caused by variations in the word line voltage generation circuit can be prevented.

FIG. 3 shows an example of the distribution of the threshold voltages of the memory cells and the word line voltages when two bits of data are stored in one memory cell. However, the present invention is not limited to this. For example, even when 4-bit data is stored in one memory cell, the distribution of the threshold voltage and the word line voltage of each memory cell can be set by the same principle. However, in this case, the distribution range of each threshold voltage of the memory cell is narrowed, and the interval between the threshold voltage distribution ranges is also narrowed. Therefore, the source line voltage V _SL applied to the common source line CSL is It is set to a lower level than when storing 2-bit data. As an example, for example, FIG.
In the example of the threshold voltage distribution shown in (1), the source line voltage V _SL should be set to 0.1V.

In the above description, the memory cell array 10 has a so-called NAND configuration, but the present invention is not limited to this. For example, the control gates of the memory cells in each row are the same. It is needless to say that the present invention can be applied to a so-called NOR type nonvolatile memory in which the drains of the memory cells in each column are connected to the same bit line, and the sources are connected to a common source line. Absent.

[0063]

As described above, according to the nonvolatile semiconductor memory device of the present invention, the minimum level of the distribution range of the threshold voltage corresponding to each storage data in the memory cell and the gate of the memory cell at the time of reading. An interval with a voltage can be reliably ensured, reading of a multi-valued memory can be easily realized, and occurrence of a reading error can be suppressed. Further, by applying the same voltage to the word line at the time of verify and read, there is an advantage that the effect of generating a word line voltage, for example, the influence of variations in characteristics of the booster circuit can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a nonvolatile semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram showing a specific example of the nonvolatile semiconductor memory device of the present invention.

FIG. 3 is a diagram showing a distribution of a memory cell threshold voltage and a gate voltage at the time of verify and read in the nonvolatile semiconductor memory device of the present invention.

FIG. 4 Floating gate (FG) type, MONOS
FIG. 2 is a simplified cross-sectional view showing a configuration of a non-volatile memory cell of a type and an MNOS type.

FIG. 5 is a diagram showing an example of a distribution of threshold voltages of memory cells in a multilevel memory.

FIG. 6 is a diagram showing a principle of occurrence of a read error due to a variation in gate voltage at the time of reading in a multi-valued memory.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate (well), 2 ... Source region, 3 ... Drain region, 4 ... Gate insulating film, 4a ... Laminated film, 5 ... Control gate, 6 ... Interlayer insulating film, 6a ... Top oxide film, 7 ... Floating gate , 8a, 8b ... nitride film,
9 ... side wall, 10 ... memory cell array, 20 ...
Source line voltage switching circuit, 30: source line voltage generation circuit, 32: reference voltage generation circuit, 34: voltage setting circuit, V
_CC : power supply voltage, GND: ground potential.

Claims (8)

[Claims] A charge storage layer insulated from the surroundings;
A threshold voltage is controlled by transfer of charge to the charge storage layer, the memory cell stores data corresponding to the threshold voltage, and charge is transferred to the charge storage layer of the memory cell during programming. After a write operation for changing the threshold voltage of the memory cell in a predetermined direction by performing transmission / reception, when a predetermined verify voltage is applied to the control gate, the current of the memory cell is detected by detecting the current of the memory cell. A verify operation for determining a threshold voltage level is performed, and the write and verify operations are repeated until the threshold voltage of the memory cell reaches a predetermined level corresponding to write data. Non-volatile semiconductor memory device that determines the data stored in the memory cell by applying a voltage and detecting the current A voltage of the same level is applied to a control gate of the memory cell at the time of the verify and read, a source region of the memory cell is held at the ground potential at the time of the verify, and the memory cell is read at the time of the read A non-volatile semiconductor memory device having source voltage switching means for applying a predetermined source bias voltage to the source region. 2. A program for storing at least two bits of data in the memory cell, wherein a threshold voltage of the memory cell is distributed in one of at least four different voltage regions according to storage data. A source bias voltage generating circuit that generates a voltage substantially half of the minimum interval between the plurality of different distribution regions and applies the generated voltage as the source bias voltage to the source region of the memory cell at the time of reading. The nonvolatile semiconductor memory device according to claim 1. 3. A memory cell having a plurality of memory cells whose threshold voltage is controlled in accordance with the amount of charge stored in a charge storage layer, wherein each of the memory cells arranged in a matrix is Are connected to the same word line, a bit line is wired for each memory cell column, and each memory cell in the same column is connected in series or parallel between the bit line and a common source line. A row decoder for selecting one word line specified by an input address signal from the plurality of word lines, and generating a voltage having a predetermined level at the time of verification and reading; A word line voltage generating circuit for applying the generated voltage to the word line selected by the row decoder; and a source line bias voltage for generating a source line bias voltage having a predetermined level. A nonvolatile semiconductor memory comprising: a generation circuit; and a source line voltage switching circuit that connects the common source line to a ground potential at the time of the verification and applies the source line bias voltage to the common source line at the time of the reading. apparatus. 4. In order to store at least two bits of data in each of the memory cells, a threshold voltage of the memory cells is programmed so as to be distributed in any of at least four different voltage regions according to storage data. The source line bias voltage generation circuit generates a voltage that is substantially half of a minimum interval between the plurality of different distribution regions, and supplies the generated voltage to the source line voltage switching circuit as the source bias voltage. 3. The nonvolatile semiconductor memory device according to 3. 5. The source line bias voltage generating circuit according to claim 1, wherein the differential circuit includes a first transistor and a second transistor having a gate maintained at a ground potential, and the gate includes the differential circuit. A drain of the second transistor, a drain connected to a power supply voltage, a source connected to the ground potential via a resistor, and a connection point between the source and the resistor connected to a gate of the second transistor. And a reference voltage corresponding to a difference between a threshold voltage of the second and first transistors from a connection point between the source of the third transistor and the resistance element. 4. The non-volatile semiconductor memory device according to claim 3, further comprising a reference voltage generating circuit for outputting the reference voltage. 6. The source line bias voltage generating circuit according to claim 1, wherein the first and second transistors have different conductivity, and the fourth transistor having the gate to which the reference voltage is applied is the same as the fourth transistor. A differential circuit comprising a fifth transistor having conductivity; and a sixth and seventh transistor having different conductivity connected in series between the power supply voltage and the ground potential. An inverter configured such that the gate of the seventh transistor is connected to the drain of the fourth transistor, and the connection point between the drains of the sixth and seventh transistors is connected to the gate of the fifth transistor. A connection point between the drains of the sixth and seventh transistors that form the inverter forms an output terminal of the inverter; Claim source line bias voltage having a level corresponding to the reference voltage is output 5
14. The nonvolatile semiconductor memory device according to claim 1. 7. The differential transistor of the reference voltage generating circuit, wherein the second transistor is an enhancement transistor, and the first transistor has a threshold voltage of the threshold voltage of the enhancement transistor. 6. A lower depletion type transistor.
14. The nonvolatile semiconductor memory device according to claim 1. 8. The source line voltage switching circuit according to claim 1, wherein one of the impurity regions forming the source and the drain is connected to the output terminal of the inverter, the other is connected to the common source line, and the gate receives a read signal. A first switching element comprising an input transistor; an impurity region forming a source connected to ground potential; an impurity region forming a drain connected to the common source line; and a gate having a logical inversion of the read signal. 7. The nonvolatile semiconductor memory device according to claim 6, further comprising a second switching element including a transistor to which a signal is applied.