CN113223588A - Bit line voltage reading device - Google Patents

Bit line voltage reading device Download PDF

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CN113223588A
CN113223588A CN202110656014.9A CN202110656014A CN113223588A CN 113223588 A CN113223588 A CN 113223588A CN 202110656014 A CN202110656014 A CN 202110656014A CN 113223588 A CN113223588 A CN 113223588A
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bit line
voltage
gate
gated
inverter
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CN113223588B (en
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何卫锋
林初雄
覃雨轩
孙亚男
毛志刚
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Shanghai Jiaotong University
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Shanghai Jiaotong University
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

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Abstract

The present invention provides a bit line voltage reading apparatus, including: a first gate-controlled skew inverter connected to the bit line for detecting a change in the bit line voltage from 1/2VDD to VDD and outputting a voltage which is inverted from VDD to zero when the bit line voltage changes; a second gate-controlled skew inverter, connected to the bit line, for detecting a change in the bit line voltage from 1/2VDD to zero and outputting a voltage that flips from zero to VDD when the bit line voltage changes; and the time-to-digital conversion circuit is communicated with the first gate-controlled skew inverter and the second gate-controlled skew inverter and is used for detecting the overturning time of the output voltage of the first gate-controlled skew inverter and the second gate-controlled skew inverter so as to detect the initial voltage and the data holding time before the access starts in a row of memory cells being accessed. The present invention detects a data retention time of a memory cell connected to a bit line by reading a change in a bit line voltage.

Description

Bit line voltage reading device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a bit line voltage reading device.
Background
A Dynamic Random Access Memory (DRAM) is a Random Access Memory using Dynamic Memory cells, which is called a DRAM for short. DRAM is one of the important components of modern computing systems. However, the access speed of DRAM has not increased much over the past many years compared to the increase in processor clock frequency and performance, causing DRAM to become a performance bottleneck for the system. Meanwhile, as future DRAM capacity further increases, in future 64Gb DRAMs, a refresh operation may result in approximately 50% performance loss and power consumption overhead.
The multi-refresh-rate DRAM refresh technology utilizes the characteristic that different memory cells in the DRAM have different data retention times, adopts a normal 64-millisecond refresh interval for a small part of the memory cells with short data retention time in the DRAM to ensure the data correctness, and adopts a larger refresh interval for a large part of the memory cells with long data retention time in the DRAM to ensure the data correctness, such as 128 milliseconds, 256 milliseconds and the like. The DRAM refreshing technology with multiple refreshing rates effectively reduces the refreshing times of the DRAM and greatly reduces the circuit refreshing cost.
Obtaining data retention time for DRAM memory cells is critical to multi-refresh rate DRAM refresh technology. In order to obtain the data retention time of the DRAM memory cell, a common method is to perform data retention time pre-analysis on the DRAM. Writing determined known data such as all 0, all 1 and the like into a certain row of a DRAM, then closing the refreshing of the DRAM, waiting for a period of time such as 64 milliseconds, 128 milliseconds and the like, then reading the data stored in the row and judging whether the data is consistent with the written data, and if errors occur, indicating that the current waiting time is greater than the data retention time of an error storage unit; if the data is not in error, indicating that the current wait time is less than the data retention time of the memory cell, then repeat the above steps while increasing the wait time until the wait time is found that the data happens to be in error. Through the steps, the waiting time of the data which is just wrong is the data holding time of the storage unit. The above steps may be performed for each row in the DRAM for data retention time pre-analysis of all memory cells in the DRAM.
However, since the data retention time of the memory cells of the DRAM is related to the data pattern stored in the DRAM, and the DRAM memory cells have a Variable data retention time (VRT) phenomenon, that is, the data retention time of the memory cells varies with time, the method of data retention time pre-analysis takes a long time (several hours to several days) to obtain the data retention time of different memory cells in the DRAM. Meanwhile, the data retention time pre-analysis method also needs to analyze the data retention time according to the worst possible situation (for example, the temperature is 85 degrees centigrade, etc.) when the DRAM works, and since the actual working temperature of the DRAM may be far lower than the worst situation (usually, not more than 65 degrees centigrade), the data retention time obtained by the data retention time pre-analysis method also has a large amount of timing margin, and cannot reflect the data retention time when the DRAM actually works.
Disclosure of Invention
An object of the present invention is to provide a bit line voltage reading apparatus which can detect a data retention time of a memory cell connected to a bit line by reading a change in a bit line voltage.
In order to achieve the above object, the present invention provides a bit line voltage reading apparatus for detecting a bit line voltage of a dynamic random access memory array, thereby detecting a data retention time of a memory cell connected to a bit line, wherein a supply voltage of the dynamic random access memory array is VDD, the dynamic random access memory array includes a plurality of rows of memory cells, each row of memory cells is connected to a bit line, including:
a first gated skew inverter in communication with the bitline, the first gated skew inverter for detecting a change in the bitline voltage from 1/2VDD to VDD and outputting a voltage that flips from VDD to zero when the bitline voltage changes;
a second gated skew inverter in communication with the bit line, the second gated skew inverter for detecting a change in the bit line voltage from 1/2VDD to zero and outputting a voltage that flips from zero to VDD when the bit line voltage changes;
and the time-to-digital conversion circuit is communicated with the first gate-controlled skew inverter and the second gate-controlled skew inverter and is used for detecting the overturning time of the output voltage of the first gate-controlled skew inverter and the second gate-controlled skew inverter so as to detect the initial voltage and the data holding time before the access starts in a row of memory cells being accessed.
Optionally, in the bit line voltage reading apparatus, each of the bit lines communicates with one of the first gated skew inverters and one of the second gated skew inverters, and a plurality of the first gated skew inverters and a plurality of the second gated skew inverters communicate with one of the time-to-digital conversion circuits.
Optionally, in the bit line voltage reading apparatus, the first gated skew inverter includes:
the NMOS transistor comprises a first NMOS transistor, a second NMOS transistor and a first PMOS transistor;
the source electrode of the first NMOS tube is grounded, the grid electrode of the first NMOS tube is connected with a detection enabling signal, the drain electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube, and the grid electrode of the second NMOS tube is connected with the grid electrode of the first PMOS tube and is commonly connected with the bit line;
the drain electrode of the second NMOS tube is connected with the source electrode of the first PMOS tube and is commonly connected with the input end of the time-to-digital conversion circuit;
the drain electrode of the first PMOS tube is connected with a first power supply voltage.
Optionally, in the bit line voltage reading apparatus, the first supply voltage is greater than or equal to a supply voltage of the dynamic random access memory array.
Optionally, in the bit line voltage reading apparatus, the driving capability of the first PMOS transistor is stronger than that of the second NMOS transistor.
Optionally, in the bit line voltage reading apparatus, when the output of the first gated skew inverter is constantly VDD, the connected bit line voltage changes from 1/2VDD to 0, and the storage logic value of the memory cell being accessed connected to the bit line is 0; when the output of the first gate-controlled skew inverter is inverted from VDD to 0, the voltage of the connected bit line is changed from 1/2VDD to VDD, and the storage logic value of the memory cell connected with the bit line and being accessed is 1.
Optionally, in the bit line voltage reading apparatus, when a memory cell connected to the bit line being accessed stores a logic value of 1, and a time when an output voltage of the first gated skew inverter is inverted is a time when the bit line voltage connected to the first gated skew inverter reaches a switching threshold of the first gated skew inverter.
Optionally, in the bit line voltage reading apparatus, the earlier the output voltage of the first gated skew inverter flips, the higher the stored logic value of the memory cell connected to the first gated skew inverter is "1" and the stored charge amount is, the longer the data retention time of the memory cell is.
Optionally, in the bit line voltage reading apparatus, the second gate-controlled skew inverter includes:
a third NMOS transistor, a fourth NMOS transistor and a second PMOS transistor;
the source electrode of the third NMOS tube is grounded, the grid electrode of the third NMOS tube is connected with a detection enabling signal, the drain electrode of the third NMOS tube is connected with the source electrode of the fourth NMOS tube, and the grid electrode of the fourth NMOS tube is connected with the grid electrode of the second PMOS tube and is connected with a bit line together;
the drain electrode of the fourth NMOS tube is connected with the source electrode of the second PMOS tube and is commonly connected with the input end of the time-to-digital conversion circuit;
and the drain electrode of the second PMOS tube is connected with a second power supply voltage.
Optionally, in the bit line voltage reading apparatus, the second supply voltage is less than or equal to a supply voltage of the dynamic random access memory array.
Optionally, in the bit line voltage reading apparatus, the driving capability of the second PMOS transistor is stronger than that of the fourth NMOS transistor.
Optionally, in the bit line voltage reading apparatus, when the output of the second gate-controlled skewed inverter is constantly 0, the bit line voltage connected to the second gate-controlled skewed inverter changes from 1/2VDD to VDD, and the memory cell connected to the bit line being accessed stores a logic value of 1; when the output of the second gate-controlled skew inverter is inverted from 0 to VDD, the voltage of a connected bit line is changed from 1/2VDD to 0, the storage logic value of an accessed storage unit connected with the bit line is 0, and the time when the output voltage of the second gate-controlled skew inverter is inverted is the time when the voltage of the connected bit line reaches the switching threshold value of the second gate-controlled skew inverter.
Optionally, in the bit line voltage reading apparatus, the inversion time of the output voltage of the second gate-controlled skew inverter is related to the amount of stored charge of the memory cell connected thereto and being accessed; the earlier the output voltage of the second gate-controlled skew inverter is inverted, the lower the logic value "0" and the amount of stored charge of the memory cell connected to the second gate-controlled skew inverter are stored, and the longer the data retention time of the memory cell is.
Optionally, in the bit line voltage reading apparatus, the time-to-digital conversion circuit includes:
an input end of the OR gate device is connected with the output voltage of the first gate-controlled skew inverter and is used for detecting the time of the last overturn of the output voltage of the first gate-controlled skew inverter;
the input end of the AND gate device is connected with the output voltage of the second gate-controlled skew inverter and is used for detecting the time of the last overturn of the output voltage of the second gate-controlled skew inverter;
and the time-to-digital conversion unit is used for merging the detection results of the OR gate device and the AND gate device and converting the turnover time of the detection result into a number.
The bit line voltage reading device provided by the invention comprises: a first gated skew inverter in communication with the bitline, the first gated skew inverter for detecting a change in the bitline voltage from 1/2VDD to VDD and outputting a voltage that flips from VDD to 0 when the bitline voltage changes; a second gated skew inverter in communication with the bit line, the second gated skew inverter for detecting a change in the bit line voltage from 1/2VDD to zero and outputting a voltage that flips from zero to VDD when the bit line voltage changes; and the time-to-digital conversion circuit is communicated with the first gate-controlled skew inverter and the second gate-controlled skew inverter and is used for detecting the overturning time of the output voltage of the first gate-controlled skew inverter and the second gate-controlled skew inverter so as to detect the initial voltage and the data holding time before the access starts in a row of memory cells being accessed. The bit line voltage reading device can read a bit line voltage in real time and detect a data retention time of a memory cell connected to the bit line by reading a change in the bit line voltage, and thus can detect the data retention time of the memory cell connected to the bit line in real time.
Drawings
FIG. 1 is a schematic diagram of a bit line voltage reading apparatus according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a time-to-digital conversion circuit according to an embodiment of the invention;
FIGS. 3 and 4 are schematic diagrams of the DRAM array and bit line voltage reading device connections according to an embodiment of the present invention;
FIG. 5 is a timing diagram illustrating the operation of the bit line voltage reading apparatus according to the embodiment of the present invention;
FIG. 6 is a diagram illustrating the operation of the time-to-digital conversion circuit according to the embodiment of the present invention;
in the figure: m0-first NMOS transistor, M1-second NMOS transistor, M2-first PMOS transistor, M3-third NMOS transistor, M4-fourth NMOS transistor, M5-second PMOS transistor, 100-gated skew inverter, 110-first gated skew inverter, 120-second gated skew inverter, 200-time digital conversion circuit, 210-OR gate device, 220-AND gate device, 230-NOT gate device, 240-second OR gate, 250-time digital conversion unit based on counter, 300-dynamic random access memory array, 310-memory unit, 400-sense amplifier.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the following, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
Referring to fig. 3, when a row of memory cells 310 of the dynamic memory is accessed or refreshed, the amount of charge retained in the memory cells 310 is different, so that the variation of the bit line voltage connected to the memory cells 310 is different when the memory cells 310 are accessed or refreshed. Thus, by detecting the change in the bit line voltage, the charge on the memory cell 310 can be estimated.
Therefore, referring to fig. 1 and fig. 3, the present invention provides a bit line voltage reading apparatus for detecting a bit line voltage of a dynamic random access memory array, thereby detecting a data retention time of a memory cell connected to the bit line, wherein a supply voltage of the dynamic random access memory array is detected to be VDD, the dynamic random access memory array includes a plurality of rows of memory cells 310, each row of memory cells 310 is connected to a bit line, and the apparatus includes:
a first gate-skew inverter 110 connected to the bit line, the first gate-skew inverter 110 for detecting a change of the bit line voltage from 1/2VDD to VDD and outputting a voltage, the output voltage being inverted from VDD to zero when the bit line voltage changes;
a second gated skew inverter 120 connected to the bit line, the second gated skew inverter 120 being configured to detect a change in the bit line voltage from 1/2VDD to zero and output a voltage that flips from zero to VDD when the bit line voltage changes;
and a time-to-digital conversion circuit 200 in communication with the first gated skew inverter 110 and the second gated skew inverter 120, the time-to-digital conversion circuit 200 configured to detect a flip time of output voltages of the first gated skew inverter 110 and the second gated skew inverter 120 to detect a worst initial voltage (near 1/2VDD) and a minimum data retention time before an access starts in a row of memory cells 310 being accessed.
Wherein: fig. 1 shows the ith bit line and the (i + 1) th bit line, and since the bit line voltage reading device connected to each bit line is the same, the description will be made by taking the bit line voltage reading device connected to the ith bit line as an example.
Further, each bit line is connected to a first gated skew inverter 110 and a second gated skew inverter 120, and a plurality of the first gated skew inverters 110 and a plurality of the second gated skew inverters 120 are connected to a time-to-digital conversion circuit 200. The gated skew inverter 100 (including the first gated skew inverter 110 and the second gated skew inverter 120) in the detection circuit detects the voltage on the bit line and generates a corresponding output result; the gated skewed inverter output results on different bit lines are connected to the time-to-digital conversion circuit 200 and generate the final detection result. That is, there may be a plurality of bit lines, each having a gated skew inverter 100 (including a first gated skew inverter 110 and a second gated skew inverter 120).
Specifically, the first gated skew inverter 110 includes: a first NMOS transistor M0, a first NMOS transistor M1 and a first PMOS transistor M2; the source electrode of the first NMOS transistor M0 is grounded, the gate electrode of the first NMOS transistor M0 is connected with a detection enabling signal, the drain electrode of the first NMOS transistor M0 is connected with the source electrode of the first NMOS transistor M1, and the gate electrode of the first NMOS transistor M1 is connected with the gate electrode of the first PMOS transistor M2 and is connected with a bit line in common; the drain electrode of the first NMOS transistor M1 and the source electrode of the first PMOS transistor M2 are connected and are commonly connected with the input end of the time-to-digital conversion circuit 200; the drain of the first PMOS transistor M2 is connected to the first supply voltage. The first supply voltage VDDH is greater than or equal to the supply voltage VDD of the dynamic random access memory array.
In the embodiment of the present invention, the first PMOS transistor M2 has stronger driving capability than the first NMOS transistor M1, and the first PMOS transistor M2 has stronger driving capability than the first NMOS transistor M1, for example, the second PMOS transistor M5 may have larger size or lower threshold voltage than the fourth NMOS transistor M4. The stronger driving capability of the first PMOS transistor M2 than the first NMOS transistor M1 can make the Switching threshold (denoted as V) of the first gated skewed inverter 110M) Above 1/2 VDD.
Further, the first NMOS transistor M0 turns off the first gated skew inverter 110 when the bit line voltage is not detected, thereby reducing power consumption of the first gated skew inverter 110.
Further, when the output of the first gated skew inverter 110 is VDD constantly, the voltage of the connected bit line changes from 1/2VDD to 0, and the storage logic value of the bit line connected memory cell 310 being accessed is 0; when the output of the first gated-skew inverter 110 flips from VDD to 0, the voltage of the bit line connected thereto changes from 1/2VDD to VDD, and the memory logic value of the memory cell 310 being accessed to which the bit line is connected is 1.
Further, the memory cell 310 being accessed with the connected bit line stores a logic value of 1, and the output voltage of the first gated skew inverter 110 is inverted at the time when the connected bit line voltage reaches the switching threshold of the first gated skew inverter 110.
Further, the output inversion time of the first gated skew inverter 110 is related to the amount of charge stored in the connected memory cell 310 being accessed, and the earlier the output voltage of the first gated skew inverter 110 is inverted, the higher the stored logic value of the connected memory cell 310 being accessed is "1" and the amount of charge stored is, the larger the data retention time of the memory cell 310 is.
Further, the second gate-controlled skew inverter 120 includes: a third NMOS transistor M3, a fourth NMOS transistor M4 and a second PMOS transistor M5; the source electrode of the third NMOS transistor M3 is grounded, the gate electrode of the third NMOS transistor M3 is connected with a detection enabling signal, the drain electrode of the third NMOS transistor M3 is connected with the source electrode of the fourth NMOS transistor M4, and the gate electrode of the fourth NMOS transistor M4 is connected with the gate electrode of the second PMOS transistor M5 and is connected with a bit line in common; the drain of the fourth NMOS transistor M4 is connected to the source of the second PMOS transistor M5 and is commonly connected to the input terminal of the time-to-digital conversion circuit 200; the drain of the second PMOS transistor M5 is tied to the second supply voltage VDDL.
The second supply voltage VDDL is less than or equal to the supply voltage VDD of the DRAM array. The fourth NMOS transistor M4 has stronger driving capability than the second PMOS transistor M5, for example, the fourth NMOS transistor M4 may have larger size or lower threshold voltage than the second PMOS transistor M5. The stronger driving capability of the fourth NMOS transistor M4 than that of the second PMOS transistor M5 enables the switching threshold V of the second gate-controlled skew inverter 120MBelow 1/2 VDD.
Further, the third NMOS transistor M3 is used to turn off the second gated skew inverter 120 when the bit line voltage is not detected, thereby reducing the power consumption of the circuit.
Further, when the output of the second gate-controlled skew inverter 120 is constantly 0, the voltage of the connected bit line changes from 1/2VDD to VDD, and the accessed memory cell 310 connected to the bit line stores a logic value of 1; when the output of the second gated skew inverter 120 is inverted from 0 to VDD, the voltage of the connected bit line changes from 1/2VDD to 0, the accessed memory cell 310 connected to the bit line stores a logic value of 0, and the output voltage of the second gated skew inverter 120 is inverted at the moment that the voltage of the connected bit line reaches the switching threshold V of the second gated skew inverter 120MTime of (d).
Further, the inversion timing of the output voltage of the second gate-controlled skewed inverter 120 is related to the amount of stored charge of the memory cell 310 connected thereto being accessed; the earlier the output voltage of the second gated skew inverter 120 flips, the lower the logic value "0" and the amount of stored charge stored in the memory cell 310 being accessed to which it is coupled, the greater the data retention time of that memory cell 310.
Further, the time-to-digital conversion circuit 200 includes: an OR gate device 210 having an input terminal connected to the output voltage of the first gated skew inverter 110 for detecting the output of the first gated skew inverter 110The output signal of the last flip of the voltage is DETHslwst(ii) a An and gate device 220 having an input terminal connected to the output voltage of the second gated skew inverter 120, for detecting a time of a last inversion of the output voltage of the second gated skew inverter 120; a NOT gate 230 for inverting the output of the AND gate 220 and outputting DETLslwst(ii) a A second or gate device 240 having an input terminal connected to the output voltages of the or gate device 210 and the not gate device 230 for combining the detection results of the or gate device 210 and the not gate device 230 and an output signal DETslwst(ii) a A counter-based time-to-digital conversion unit 250 for converting DETslwstThe flip time of (a) is converted into a number. As shown in fig. 2, the number of the or gate device 210 is at least one, and two input terminals of the or gate device 210 are respectively connected to the output signal of the first gate-controlled skewed inverter 110, that is, the input terminals are connected to the drain of the first NMOS transistor M1 and the source of the first PMOS transistor M2. The output of each first gated inverter 110 is connected to one input of an or gate device 210. If there are N bit lines, there are N first gated skew inverters 110, and 1/2N or gate devices 210 are used to directly connect to the first gated skew inverters 110, and signals of the first gated skew inverters 110 obtained by 1/2N or gate devices 210 need to be collected and then transmitted to the counter-based time-to-digital conversion unit 250 to be converted into specific numbers. Specifically, the output terminals of 1/2N or gate devices 210 are further connected to the input terminals of the or gate devices 210, so that, if there are N first gated skewed inverters 110, 1/2N stages of or gate devices 210, respectively 1 st stage to 1/2N stages, each stage including 1 st to 1/2N or gate devices 210, specifically, each stage of or gate devices 210 includes the same number of or gate devices 210 as the number of stages, for example, 1 st stage has 1 or gate device 210, 2 nd stage has two or gate devices 210, the output terminal of one or gate device 210 of the 2 nd stage is connected to one input terminal of the or gate device 210 of the 1 st stage, and the output terminal of the other or gate device 210 of the 2 nd stage is also connected to the other input terminal of the or gate device 210 of the 1 st stage. By analogy, the outputs of the 1/2N OR-gate devices 210 of the 1/2N-th stage are all connected to the 1/2N-1 th stage (the 1/2N-1 st stage is the 1/2N-th stage)The previous stage) of the or gate device 210. Similarly, the number of the and gate devices 220 is at least one, and two input terminals of the and gate device 220 are respectively connected to the output signal of the second gate-controlled skew inverter 120, that is, the input terminals are connected to the drain of the fourth NMOS transistor M4 and the source of the second PMOS transistor M5. The output of each second gated inverter 120 is connected to an input of an and gate arrangement 220. If there are N bit lines, there are N second gated skew inverters 120, and 1/2N and gate devices 220 are used to directly connect to the second gated skew inverters 120, and signals of the second gated skew inverters 120 obtained by 1/2N and gate devices 220 need to be collected and then transmitted to the counter-based time-to-digital conversion unit 250 to be converted into specific numbers. Specifically, the output terminals of 1/2N and gate devices 220 are further connected to the input terminals of the and gate device 220, so that, if there are N second gated skewed inverters 120, 1/2N stages of and gate devices 220 are used, each stage includes 1 to 1/2N stages, each stage includes 1 to 1/2N and gate devices 220, specifically, each stage of and gate devices 220 includes the same number of and gate devices 220 as the stage number, for example, 1 and gate device 220 in the 1 st stage, two and gate devices 220 in the 2 nd stage, the output terminal of one and gate device 220 in the 2 nd stage is connected to one input terminal of the and gate device 220 in the 1 st stage, and the output terminal of the other and gate device 220 in the 2 nd stage is also connected to the other input terminal of the and gate device 220 in the 1 st stage. By analogy, the outputs of the 1/2N AND gate devices 220 of the 1/2N-th stage are all connected to the inputs of the AND gate devices 220 of the 1/2N-1 th stage (the 1/2N-1 st stage is the previous stage to the 1/2N-th stage). The output of the 1 st stage and gate device 220 needs to pass through a not gate device 230, the input terminal of the not gate device 230 is connected to the output terminal of the 1 st stage and gate device 220, and the output terminal of the not gate device is DETLslwstA signal. And the output of the 1 st stage or gate device 210 and the output of the not gate device 230 need to go through the combination of the second or gate 240 and then enter the time-to-digital conversion unit 250 based on the counter. That is, the output terminal of the 1 st stage OR gate device 210 is connected to the input terminal of the second OR gate 240, the output terminal of the NOT gate device 230 is connected to the input terminal of the second OR gate 240, and the output terminal of the second OR gate 240 is connected to the time-digital number based on the counterThe input terminal of the conversion unit 250, and the output terminal of the time-to-digital conversion unit 250 based on the counter can output the detection result. During detection, the and gate device 210 finds the last flip output of the first gated skewed inverter 110 on a different bit line, the or gate device 220 finds the last flip output of the second gated skewed inverter 120 on a different bit line, and then the not gate device 230 and the second or gate 240 find the last flip output of all the first gated skewed inverter 110 and the second gated skewed inverter 120; the time-to-digital conversion circuit 250 converts the detected time of the rollover into a digital signal by being based on a counter and outputs as a detection result. The flip time of the final output result of the counter-based time-to-digital conversion unit 250 represents the retention time of the shortest data in the row of memory cells 310 of the dynamic random access memory array being accessed, and the earlier the flip time of the output result, the longer the retention time of the shortest data in the row of memory cells 310 being accessed.
Preferably, embodiments of the present invention may further comprise a sense amplifier 400 connected to each bit line. The dynamic random access memory array performs read, write or refresh operations on a certain row of memory cells 310 by selecting corresponding bit lines; data is written to the memory cell 310 or read from the memory cell 310 through the bit line; sense amplifier 400 is responsible for accelerating the amplification of the voltage on the bit line.
Specifically, the bit line voltage is sensed by integrating the sensing circuit into the dram array 300, as shown in fig. 3. The DRAM array 300 includes rows and columns of memory cells 310, each row of memory cells 310 connected to the same wordline, each column of memory cells 310 connected to the same bitline, each bitline connected to a sense amplifier 400. The dynamic random access memory array 300 performs read, write or refresh operations on a row of memory cells 310 by selecting corresponding bit lines; data is written to the memory cell 310 or read from the memory cell 310 through the bit line; sense amplifier 400 is responsible for accelerating the amplification of the voltage on the bit line. Subsequently, the gate-controlled skew inverter 100 processes the amplified voltage, and the time-to-digital conversion circuit 200 processes an output signal of the gate-controlled skew inverter 100. Here, the gated skew inverter 100 includes: a first gated skew inverter 110 and a second gated skew inverter 120.
An example of the operation of the detection circuit is shown for the access of one memory cell 310 in the dram array 300. In the present example, it is assumed that the memory cell 310 stores a logic value of 1, and the output of the second gated skew inverter 120 remains unchanged, so that only the connection relationship between the input and the output of the first gated skew inverter 110 and the variation process thereof are shown. As shown in FIG. 4, assume that the ith memory cell 310 is on the ith bit line. The ith memory cell 310 is a conventional DRAM 1T1C structure, i.e., includes a transistor and a capacitor. When the i-th memory cell 310 stores a logic value of 1, ideally, the voltage generated by the charge on the capacitor is VDD. However, due to leakage of the transistor in the memory cell 310, the charge on the capacitor generates a voltage Vc, init (Vc, init ≦ VDD) before the i-th memory cell 310 is accessed.
Fig. 5 shows the variation of the capacitance voltage, the bit line voltage, and the output signal DETHi of the first gated skew inverter 110 during sensing. Initially, the capacitor voltage Vc, init, and the bit line voltage are precharged to 0.5VDD, and the first gated skewed inverter 110 outputs VDD because the bit line voltage is below the switching threshold VM of the first gated skewed inverter 110. Thereafter, the word line of the memory cell 310 is pulled high, the transistor inside is turned on, and the charge on the internal capacitor begins to be shared with the bit line, so that the capacitor voltage gradually decreases and the bit line voltage gradually increases until the two voltages become equal, at which time the bit line voltage deviates from the initial 0.5VDD by Δ V0.
Thereafter, the sense amplifier 400 starts operating and amplifies Δ V0 so that both the capacitor voltage and the bitline voltage are gradually charged to VDD. In this process, when the bitline voltage is less than the switching threshold VM of the first gated skewed inverter 110, the output is VDD; when the bit line voltage gradually rises, eventually exceeding VM, the first gated skew inverter 110 output DETHi falls to 0. The time at which the output signal DETHi of the first gated skew inverter 110 flips is denoted tDET. Since the data retention time of the memory cell 310 is different, the capacitor voltage Vc, init of the memory cell 310 is also different after the leakage: the longer the data retention time, the larger Vc init after the same refresh window. The higher the capacitor voltage Vc, init, the larger Δ V0, so that sense amplifier 400 charges the bit line voltage and capacitor voltage to VDD earlier and faster, and thus tDET will be smaller.
Through the above analysis, the first gated skew inverter 110 can detect different capacitor voltages Vc, init and generate different DETHi signals, and we can estimate the capacitor voltages Vc, init and calculate corresponding data retention time according to the difference of the turning times tDET. In addition, since each bit line has a pair of gated skewed inverters and the refresh interval of the DRAM array is determined by the memory cell 310 with the largest data retention time in a row. Therefore, the detection signals DETHi (and DETLi) of the different bit lines are all connected to the time-to-digital conversion circuit 200. As shown in fig. 6, the clock signal in the figure is a clock signal of the counter-based time-to-digital conversion unit 250, and the signal includes a plurality of periods, for example, marked with period 0, period 1, period 2, and period; DETH 0-DETHN-1Is the detection signal DETHi (i takes a value of 1 to N-1) generated by the first gated skew inverter 110; DETL 0-DETLN-1Is the detection signal DETLi (i takes a value of 1 to N-1) generated by the second gated skew inverter 120; DET (DET)slwstIs a signal input to the input of the counter-based time-to-digital conversion unit 250; CNT is the result of the detection. As can be seen from the figure, the time-to-digital conversion circuit 200 first finds the latest inverted DETHi signal through the or gate device 210, which appears in the diagram at DETHN-1On the signal; and finds the latest flipped DETLi signal through the and gate 220 and not 230 devices, which in this figure appears at DETLN-1On the signal. The later of the latest flipped DETHi signal and the latest flipped DETLI signal is then found by the second OR gate 240, in this figure DETHN-1Since the signal is the latest, DETH is usedN-1Is the latest flip signal, namely DETslwst. The counter-based time-to-digital conversion unit 250 inverts the latest signal (denoted as DETs)lwst) Is converted intoThe digital signal CNT is used as the final detection output signal. CNT starts counting at the beginning of detection (i.e., cycle 0), increasing by one every clock cycle; when the signal DET is turned over at the latestslwstOn flipping, the CNT stops counting, which is shown in cycle 2, so the final CNT count is 2 (shown as 2' b10 in binary). Thus, by the counter-based time-to-digital conversion unit 250, the latest flip signal DET can be convertedslwstThe flip time is converted into a digital result CNT.
The bit line voltage reading device is integrated in the sense amplifier 400 of the dynamic random access memory array, and can detect the bit line voltage in real time; the bit line voltage reading device can acquire the electric quantity information of the memory cell 310 while performing normal refreshing and access operations on the memory cell by real-time detection, so that the bit line voltage reading device does not affect the normal function of the dynamic random access memory array compared with a data retention time pre-analysis method, and meanwhile, the time required for the bit line voltage reading device to acquire the electric quantity information of the memory cell 310 and estimate the data retention time of the memory cell is shorter; the bit line voltage reading device is connected to the bit line, the bit line voltage is detected on the line ground, and the position of the bit line voltage reading device can be close to the physical position of the dynamic random access memory array storage array, so that the bit line voltage reading device and the storage unit 310 to be accessed have the same working conditions, namely, similar temperature, voltage and the like, and therefore the bit line voltage reading device can accurately detect the electric quantity information of the storage unit 310 to be accessed at the current moment, and therefore compared with a data retention time pre-analysis method, unnecessary time sequence allowance can be eliminated more fully and accurately, and the performance and the energy efficiency of the dynamic random access memory array are improved.
In summary, the bit line voltage reading apparatus according to the embodiment of the invention includes: a first gated skew inverter in communication with the bitline, the first gated skew inverter for detecting a change in the bitline voltage from 1/2VDD to VDD and outputting a voltage that flips from VDD to 0 when the bitline voltage changes; a second gated skew inverter in communication with the bit line, the second gated skew inverter for detecting a change in the bit line voltage from 1/2VDD to zero and outputting a voltage that flips from zero to VDD when the bit line voltage changes; a time-to-digital conversion circuit in communication with the first gated skew inverter and the second gated skew inverter, the time-to-digital conversion circuit configured to detect a flip time of output voltages of the first gated skew inverter and the second gated skew inverter to detect a worst initial voltage and a minimum data retention time in a row of memory cells being accessed. The bit line voltage reading device can read a bit line voltage in real time and detect a data retention time of a memory cell connected to the bit line by reading a change in the bit line voltage, and thus can detect the data retention time of the memory cell connected to the bit line in real time.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (14)

1. A bit line voltage reading apparatus for detecting a bit line voltage of a dynamic random access memory array to detect a data retention time of memory cells connected to a bit line, wherein a supply voltage of the dynamic random access memory array is VDD, the dynamic random access memory array including a plurality of rows of memory cells, each row of memory cells being in communication with a bit line, comprising:
a first gated skew inverter in communication with the bitline, the first gated skew inverter for detecting a change in the bitline voltage from 1/2VDD to VDD and outputting a voltage that flips from VDD to zero when the bitline voltage changes;
a second gated skew inverter in communication with the bit line, the second gated skew inverter for detecting a change in the bit line voltage from 1/2VDD to zero and outputting a voltage that flips from zero to VDD when the bit line voltage changes;
and the time-to-digital conversion circuit is communicated with the first gate-controlled skew inverter and the second gate-controlled skew inverter and is used for detecting the overturning time of the output voltage of the first gate-controlled skew inverter and the second gate-controlled skew inverter so as to detect the initial voltage and the data holding time before the access starts in a row of memory cells being accessed.
2. The bit line voltage reading apparatus of claim 1, wherein each of the bit lines communicates with one of the first gated skew inverters and one of the second gated skew inverters, and a plurality of the first gated skew inverters and a plurality of the second gated skew inverters communicate with a time-to-digital conversion circuit.
3. The bit line voltage reading apparatus of claim 1, wherein the first gated skewed inverter comprises:
the NMOS transistor comprises a first NMOS transistor, a second NMOS transistor and a first PMOS transistor;
the source electrode of the first NMOS tube is grounded, the grid electrode of the first NMOS tube is connected with a detection enabling signal, the drain electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube, and the grid electrode of the second NMOS tube is connected with the grid electrode of the first PMOS tube and is connected with a bit line together;
the drain electrode of the second NMOS tube is connected with the source electrode of the first PMOS tube and is commonly connected with the input end of the time-to-digital conversion circuit;
the drain electrode of the first PMOS tube is connected with a first power supply voltage.
4. The bit line voltage reading apparatus of claim 3, wherein the first supply voltage is greater than or equal to a supply voltage of the dynamic random access memory array.
5. The bit line voltage reading apparatus of claim 3, wherein the first PMOS transistor has stronger driving capability than the second NMOS transistor.
6. The bit line voltage reading apparatus of claim 1, wherein when the output of the first gated-skewed inverter is VDD constantly, the bit line voltage connected thereto changes from 1/2VDD to 0, and the storage logic value of the bit line connected to the memory cell being accessed is 0; when the output of the first gate-controlled skew inverter is inverted from VDD to 0, the voltage of the connected bit line is changed from 1/2VDD to VDD, and the storage logic value of the memory cell connected with the bit line and being accessed is 1.
7. The bit line voltage reading apparatus of claim 6, wherein when a memory cell of the bit line connection being accessed stores a logic value of 1, and the output voltage of the first gated skew inverter flips at a time when the bit line voltage to which it is connected reaches a switching threshold of the first gated skew inverter.
8. The bit line voltage reading apparatus of claim 7, wherein the earlier the output voltage of the first gated skewed inverter flips, the greater the memory cell connected thereto has a stored logic value of "1" and a higher amount of stored charge, the greater the data retention time of the memory cell.
9. The bit line voltage reading apparatus of claim 1, wherein the second gated skew inverter comprises:
a third NMOS transistor, a fourth NMOS transistor and a second PMOS transistor;
the source electrode of the third NMOS tube is grounded, the grid electrode of the third NMOS tube is connected with a detection enabling signal, the drain electrode of the third NMOS tube is connected with the source electrode of the fourth NMOS tube, and the grid electrode of the fourth NMOS tube is connected with the grid electrode of the second PMOS tube and is connected with a bit line together;
the drain electrode of the fourth NMOS tube is connected with the source electrode of the second PMOS tube and is commonly connected with the input end of the time-to-digital conversion circuit;
and the drain electrode of the second PMOS tube is connected with a second power supply voltage.
10. The bit line voltage reading apparatus of claim 9, wherein the second supply voltage is less than or equal to a supply voltage of the dynamic random access memory array.
11. The bit line voltage reading apparatus of claim 9, wherein the second PMOS transistor has stronger driving capability than the fourth NMOS transistor.
12. The bit line voltage reading apparatus of claim 9, wherein when the output of the second gated-skewed inverter is constantly 0, the bit line voltage connected thereto changes from 1/2VDD to VDD, and the memory cell connected thereto being accessed stores a logic value of 1; when the output of the second gate-controlled skew inverter is inverted from 0 to VDD, the voltage of a connected bit line is changed from 1/2VDD to 0, the storage logic value of an accessed storage unit connected with the bit line is 0, and the time when the output voltage of the second gate-controlled skew inverter is inverted is the time when the voltage of the connected bit line reaches the switching threshold value of the second gate-controlled skew inverter.
13. The bit line voltage reading apparatus of claim 1, wherein a timing of a flip of an output voltage of the second gate-controlled skewed inverter is related to a stored charge amount of a memory cell connected thereto being accessed; the earlier the output voltage of the second gate-controlled skew inverter is inverted, the lower the logic value "0" and the amount of stored charge of the memory cell connected to the second gate-controlled skew inverter are stored, and the longer the data retention time of the memory cell is.
14. The bit line voltage reading apparatus of claim 1, wherein the time-to-digital conversion circuit comprises:
an input end of the OR gate device is connected with the output voltage of the first gate-controlled skew inverter and is used for detecting the time of the last overturn of the output voltage of the first gate-controlled skew inverter;
the input end of the AND gate device is connected with the output voltage of the second gate-controlled skew inverter and is used for detecting the time of the last overturn of the output voltage of the second gate-controlled skew inverter;
and the time-to-digital conversion unit is used for merging the detection results of the OR gate device and the AND gate device and converting the turnover time of the detection result into a number.
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