KR20080113839A - Semiconductor device with line pattern and method for manufacturing the same - Google Patents

Abstract

The semiconductor device and manufacturing method thereof having line pattern are provided to improve the reliability of device and prevent the leaning phenomenon of the line pattern by forming the dummy contact served as a supporter of the line pattern. The method of manufacturing the semiconductor device having the line pattern comprises as follows. A step is for forming underlayer(21) on the substrate(20) including the end area of cell. A step is for forming the dummy contact(23) in the underlayer a part of the end area of cell. A step is for forming a plurality of line patterns(24) on the underlayer. The dummy contact is connected to a part of line pattern among a plurality of line patterns.

Description

A semiconductor device having a line pattern and a method of manufacturing the same {SEMICONDUCTOR DEVICE WITH LINE PATTERN AND METHOD FOR MANUFACTURING THE SAME}

1A and 1B are photographs for explaining a lining phenomenon occurring when forming a conventional line pattern.

2A and 2B are plan and cross-sectional views illustrating a method of manufacturing a semiconductor device having a line pattern according to an embodiment of the present invention.

3 is a photograph showing a line pattern of a semiconductor device formed in accordance with one embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

20: substrate 21: lower film

22: dummy contact hole 23: dummy contact

24: line pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly, to a semiconductor device having a line pattern and a method of manufacturing the same.

The line pattern of the semiconductor device generally has a structure in which a plurality of films are stacked. For example, a bitline is formed by sequentially stacking a conductive film and a hard mask.

Recently, as semiconductor devices have been highly integrated, there is a problem in that a leaning phenomenon in which a line pattern is inclined frequently occurs and causes device defects (see cross-sectional view of FIG. 1A).

There are various views as to the cause of such a phenomenon. Looking at this in more detail, the view that the line pattern is due to the decrease in size and aspect ratio of the line pattern due to the high integration of the semiconductor device, the view that is due to the thermal stress or mechanical stress difference between the materials constituting the line pattern, line pattern The view that the change occurs in the upper film deposited on the lower film due to the surface roughness of the lower film to be configured, or thermally generated during the subsequent process (for example, the spacer formation process or the interlayer insulation film formation process, etc.) There is a view that it is due to mechanical stress.

In any view, the phenomenon of line pattern lining may cause gap fill defects in the subsequent interlayer insulating film formation process, or excessive hardmask loss in subsequent contact formation processes, resulting in short between contacts. This can cause device defects.

In particular, such a lining phenomenon occurs intensively in a cell end region where a separate pattern is not formed in an adjacent region rather than a cell center region (see plan view in FIG. 1B), and thus, a line pattern lining phenomenon in the cell end region can be prevented Development of technology is required.

The present invention has been proposed to solve the above problems of the prior art, by forming a dummy contact acting as a support of the line pattern under the line pattern of the cell end region prior to the formation of the line pattern, the line pattern SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a line pattern capable of preventing the phenomenon and improving the reliability and yield of the device.

A method of manufacturing a semiconductor device having a line pattern of the present invention for achieving the above object comprises the steps of forming a lower film on a substrate including a cell end region; Forming a dummy contact on a portion of the lower layer of the cell end region; And forming a plurality of line patterns on the lower layer, wherein the dummy contact is connected to some line patterns of the plurality of line patterns.

In addition, the semiconductor device having a line pattern of the present invention for achieving the above object, the substrate comprising a cell end region; A lower layer formed on the substrate and having a dummy contact formed in a portion of the cell end region; And a plurality of line patterns on the lower layer, wherein the dummy contact is connected to some line patterns of the plurality of line patterns.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2A and 2B are plan and cross-sectional views illustrating a method of manufacturing a semiconductor device having a line pattern according to an embodiment of the present invention. In particular, the cross-sectional views of FIGS. 2A and 2B are cross-sectional views of the "B" portion of the plan view.

As shown in FIG. 2A, a lower layer 21 is formed on the substrate 20 including the cell end region A under the line pattern. On the lower layer 21, a line pattern is formed that is repeated a plurality of times in a subsequent process. Thus, the planar region 24 'is shown as a dotted line in the plan view.

Subsequently, a dummy contact 23 is formed in a part of the region 24 ′ which is predetermined as the line pattern of the cell end region A. FIG. More specifically, a portion of the lower layer 21 of the predetermined area 24 ′ is etched to a predetermined depth in a line pattern of the cell end region A to form a dummy contact hole 22, and then the dummy A dummy contact 23 is formed in a portion of the lower layer 21 by filling a contact material in the contact hole 22.

In particular, some of the line patterns of the cell end region A are generally dummy processed so as not to be electrically connected to the lower layer. Therefore, the dummy contact 23 is preferably formed under a portion of the line pattern that is dummy processed among the line patterns of the cell end region A. FIG. The dummy process for the line pattern of the cell end region A may be performed for the line pattern repeated in the range of 1 to 10, so that the dummy contact 23 is also repeated in the range of 1 to 10. It may be formed under the line pattern.

As described above, in the case where the dummy contact 23 is formed in a part of the region 24 'predetermined as the line pattern of the cell end region A, since the subsequent line pattern is supported by the dummy contact 23, the cell end region ( The line pattern lining phenomenon in A) is prevented. Here, since the dummy contact 23 is a dummy pattern that is not electrically connected to the lower layer, it is irrelevant to the actual cell operation, and merely serves as a support for the subsequent line pattern.

As shown in Fig. 2B, a line pattern 24 is formed that is repeated a plurality of times on the lower layer 21 of the region 24 'predetermined as the line pattern.

As a result, the dummy contact 23 formed under the line pattern 24 of the cell end region A in which the lining phenomenon occurs intensively comes into contact with the line pattern 24 to act as a support, and thus the cell end region A The phenomenon of lining the line pattern 24 of () is prevented.

3 is a photograph showing a line pattern of a semiconductor device formed according to an embodiment of the present invention.

Referring to FIG. 3, it can be seen that the line pattern lining phenomenon, in particular, the line pattern lining phenomenon in the cell end region is minimized.

The line pattern of the present invention includes a gate line, a bit line or a metal wiring.

Although the technical spirit of the present invention has been specifically recorded in accordance with the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The semiconductor device having a line pattern according to the present invention and a method of manufacturing the same according to the present invention are formed by forming a dummy contact acting as a support of a line pattern under a region intended as a line pattern of a cell end region before forming the line pattern. By preventing the phenomenon of lining, it is possible to improve the reliability and yield of the device.

Claims (9)

Forming a lower layer on the substrate including the cell end region; Forming a dummy contact on a portion of the lower layer of the cell end region; And Forming a plurality of line patterns on the lower layer Including, Here, the dummy contact is connected to some line patterns of the plurality of line patterns. A method of manufacturing a semiconductor device having a line pattern. The method of claim 1, The dummy contact forming step, Forming a dummy contact hole by etching a portion of the lower layer in a region predetermined by the line pattern of the cell end region; And Embedding a contact material in the dummy contact hole; A method of manufacturing a semiconductor device having a line pattern. The method of claim 1, The partial line pattern of the cell end region connected to the dummy contact may be dummy processed. A method of manufacturing a semiconductor device having a line pattern. The method of claim 3, The dummy process is performed on the partial line pattern of the cell end region repeated in the range of 1 to 10. A method of manufacturing a semiconductor device having a line pattern. The method of claim 1, The line pattern is a gate line, a bit line or a metal wiring A method of manufacturing a semiconductor device having a line pattern. A substrate including a cell end region; A lower layer formed on the substrate and having a dummy contact formed in a portion of the cell end region; And A plurality of line patterns on the lower layer Including, Here, the dummy contact is connected to some line patterns of the plurality of line patterns. A semiconductor device having a line pattern. The method of claim 6, The partial line pattern of the cell end region connected to the dummy contact may be dummy processed. A semiconductor device having a line pattern. The method of claim 7, wherein The dummy process is performed on the partial line pattern of the cell end region repeated in the range of 1 to 10. A semiconductor device having a line pattern. The method of claim 6, The line pattern is a gate line, a bit line or a metal wiring A semiconductor device having a line pattern.

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